JPS5546659A - Data information reproduction system - Google Patents

Data information reproduction system

Info

Publication number
JPS5546659A
JPS5546659A JP12026978A JP12026978A JPS5546659A JP S5546659 A JPS5546659 A JP S5546659A JP 12026978 A JP12026978 A JP 12026978A JP 12026978 A JP12026978 A JP 12026978A JP S5546659 A JPS5546659 A JP S5546659A
Authority
JP
Japan
Prior art keywords
circuit
pll2
bpf1
data information
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12026978A
Other languages
Japanese (ja)
Inventor
Tatsuki Hayashi
Kazuo Murano
Shigeyuki Umigami
Fumio Amano
Yasukazu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12026978A priority Critical patent/JPS5546659A/en
Publication of JPS5546659A publication Critical patent/JPS5546659A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
    • H04L27/06—Demodulator circuits; Receiver circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To attain IC-implementation by omitting a phase shifting circuit by composing PLL and BPF of digital circuits. CONSTITUTION:BPF1' and PLL2' are composed of digital circuit, and an input signal is A/D-converted 7; and the center frequency of BPF1' is shifted by a fixed value to the carrier frequency of the input signal and the output of BPF1' is supplied to PLL2', thereby regenerating a discrimination timing signal with the best phase needed for data information discrimination circuit 5. Further A/D converter 7 is controlled by using an output from PLL2' and a demodulating carrier is suplied to demodulation circuit 3'. As a result, the need to shift the phase of a discrimination timing pulse is eliminated and IC-implementation of this circuit is possible.
JP12026978A 1978-09-29 1978-09-29 Data information reproduction system Pending JPS5546659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12026978A JPS5546659A (en) 1978-09-29 1978-09-29 Data information reproduction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12026978A JPS5546659A (en) 1978-09-29 1978-09-29 Data information reproduction system

Publications (1)

Publication Number Publication Date
JPS5546659A true JPS5546659A (en) 1980-04-01

Family

ID=14782029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12026978A Pending JPS5546659A (en) 1978-09-29 1978-09-29 Data information reproduction system

Country Status (1)

Country Link
JP (1) JPS5546659A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892162A (en) * 1981-11-27 1983-06-01 Hitachi Ltd Method and apparatus for timing phase control
JPH01296745A (en) * 1988-05-25 1989-11-30 Hitachi Ltd Digital demodulation circuit and digital signal processing type demodulation system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892162A (en) * 1981-11-27 1983-06-01 Hitachi Ltd Method and apparatus for timing phase control
JPH01296745A (en) * 1988-05-25 1989-11-30 Hitachi Ltd Digital demodulation circuit and digital signal processing type demodulation system

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