JPS55149554A - Carrier reproducing circuit - Google Patents

Carrier reproducing circuit

Info

Publication number
JPS55149554A
JPS55149554A JP5724279A JP5724279A JPS55149554A JP S55149554 A JPS55149554 A JP S55149554A JP 5724279 A JP5724279 A JP 5724279A JP 5724279 A JP5724279 A JP 5724279A JP S55149554 A JPS55149554 A JP S55149554A
Authority
JP
Japan
Prior art keywords
output
circuit
signal
fed
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5724279A
Other languages
Japanese (ja)
Other versions
JPS6154303B2 (en
Inventor
Hiroyuki Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5724279A priority Critical patent/JPS55149554A/en
Publication of JPS55149554A publication Critical patent/JPS55149554A/en
Publication of JPS6154303B2 publication Critical patent/JPS6154303B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • H04L27/2277—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using remodulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To obtain the carrier reproducing circuit having the functions which can detect asynchronism of the carrier reproducing PLL and that of clock synchronous circuit, by adding one detection circuit. CONSTITUTION:The digital phase modulation wave input to the input terminal 1 is in phase comparison with the reproduced carrier fed from PLL5 at the demodulator 6, and the output is in A/D conversion and output from the terminals 2, 2' as the digital demodulation signal. The output of the A/D converter 62 is fed to the clock synchronous circuit 7 and the clock in synchronizing with the demodulation data is obtained as the output of VCO75. This clock signal is adjusted of the phase by the phase shifter 8 and then formed of the pulse width at the circuit 9 and fed to PLL5. The A/D conversion output of the demodulator 6 is input to the inverse modulator 4, and the input signal is in inverse modulation with the data signal. The output of the inverse-modulator 4 is fed to PLL5 as the carrier of nonmodulation. The input signal of VCO54 in the PLL circuit 5 is branched and detected at the detection circuit 10, then output as the signal representing asynchronized state.
JP5724279A 1979-05-10 1979-05-10 Carrier reproducing circuit Granted JPS55149554A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5724279A JPS55149554A (en) 1979-05-10 1979-05-10 Carrier reproducing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5724279A JPS55149554A (en) 1979-05-10 1979-05-10 Carrier reproducing circuit

Publications (2)

Publication Number Publication Date
JPS55149554A true JPS55149554A (en) 1980-11-20
JPS6154303B2 JPS6154303B2 (en) 1986-11-21

Family

ID=13050057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5724279A Granted JPS55149554A (en) 1979-05-10 1979-05-10 Carrier reproducing circuit

Country Status (1)

Country Link
JP (1) JPS55149554A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4507617A (en) * 1981-08-10 1985-03-26 Fujitsu Limited Carrier recovery circuit for a PSK modulated signal
US4525676A (en) * 1981-02-24 1985-06-25 Nippon Electric Co., Ltd. PSK Demodulation system having carrier frequency variation compensation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525676A (en) * 1981-02-24 1985-06-25 Nippon Electric Co., Ltd. PSK Demodulation system having carrier frequency variation compensation
US4507617A (en) * 1981-08-10 1985-03-26 Fujitsu Limited Carrier recovery circuit for a PSK modulated signal

Also Published As

Publication number Publication date
JPS6154303B2 (en) 1986-11-21

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