JPH0666694B2 - D / A converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is suitable for use in, for example, audio equipment for converting a digital signal into an analog signal (hereinafter referred to as D / A conversion). Regarding the device.

[Conventional technology]

One of the digital transmission methods is called a digital audio interface transmission method. In the digital audio interface, one digital cable transmits data for two L channels and two R channels. Therefore, as shown in FIG. 14A, a time division multiplex transmission system is used in which L channel data and R channel data are alternately transmitted and received. When the sampling frequency is 44.1 kHz as in a compact disc, 44100 pieces of data for each of the L channel and the R channel are transmitted per second, and 88200 pieces of data for both channels are transmitted. The length of one channel data section (word) is 11.34μ
Seconds. Also, one word consists of 32 bits,
In this case, the bit division is performed as shown in FIG. 14B. That is, in the figure, the first 4 bits are a SYNC portion for establishing synchronization, and a preamble to be described later is set therein. Next is the part that contains audio data,
There is a 24-bit field. However, as with compact discs, audio data often has 16 bits, and currently uses only 18 bits behind it. The last 4 bits are the control part that carries information accompanying data such as emphasis ON / OFF and subcode.

As shown in FIG. 14C, the data thus assembled is subjected to a modulation called a so-called biphase mark in which data “0” is inverted once and data “1” is inverted twice. To be The exception is the SYNC part, which has a special pattern called a preamble. Inversion of data is ignored in the preamble, and the high level continues longer than any other part.

[Problems to be solved by the invention]

However, a D / A conversion device for D / A converting a digital audio interface signal in which audio data is conventionally modulated by a specific modulation method such as the biphase mark modulation method as described above has not been developed yet.

The present invention has been made in view of the above point, and is capable of D / A converting an input signal such as a digital audio interface signal including at least a synchronizing signal and audio data modulated by a predetermined modulation method. An A conversion device is provided.

[Means for solving problems]

The present invention is directed to a detection circuit (2) for detecting a sync signal from an input signal including at least a sync signal and audio data modulated by a predetermined modulation method, and a wideband first circuit for phase-locking to the detected sync signal. Response to the clock signal and the input signal from the PLL circuit (7), the narrow band second PLL circuit (19) that locks the phase to the synchronization signal detected by the detection circuit, and the first PLL circuit (7) A demodulation circuit (8) for obtaining a demodulation signal by using the D / A conversion means (9) for converting the demodulation signal from the demodulation circuit (8) from a digital signal to an analog signal; A conversion means (9),
Sample holding means (11), (12) for sampling and holding the output of (10) from the demodulation signal and the sampling timing signal formed from the clock signal from the second PLL circuit (19) I am configuring.

[Action]

The detection circuit (2) detects a synchronization signal from the input signal, and phase locks the detected synchronization signal to form a clock signal of a predetermined frequency in the PLL circuit (7), and demodulates the clock signal and the input signal. The signal is supplied to (8) to demodulate the input signal based on the clock signal, and the demodulated signal is converted from a digital signal to an analog signal in the D / A conversion means (9) and (10) to obtain a demodulated signal and a clock signal. Based on the sampling timing signal formed based on
By sampling and holding the / A conversion output, a desired analog signal can be obtained at the output side of the sample and hold means.

〔Example〕

Hereinafter, various embodiments of the present invention will be described in detail with reference to FIGS. 1 to 13.

FIG. 1 shows a first embodiment of the present invention, in which (1) is an input terminal to which an input signal in the format as shown in FIG. 14 is supplied, and (2) is an input terminal (1 )
The detection circuit detects a sync signal having a frequency twice the sampling frequency fs of the audio data from the input signal from. As the detection circuit (2), for example, as shown in FIG. 2, an exclusive OR circuit (2a) having one input end connected to the input terminal (1) and an exclusive OR circuit (2a) The inverters (2b), (2c) and the capacitor (2d) that are provided between the other input end and the input terminal (1) to form a delay circuit, and the output side of the exclusive OR circuit (2a) A retriggerable mono multivibrator (2e) having a predetermined set time tw _1, eg tw ₁ ≈450 n sec, and a predetermined set time tw ₂ eg tw ₂ provided on the output side of this mono multivibrator (2e). A retrigable mono-multivibrator (2f) having ≈5 μsec can be used. The mono multivibrator (2f) may be an ordinary mono multivibrator without using the retriggerable type.

Returning to FIG. 1 again, (3) shows that the output of the detection circuit (2) is 1
For example, a negative edge comparison type phase comparator supplied to the input side, (4) is a loop filter provided on the output side of the phase comparator (3), and (5) is its oscillation frequency depending on the output of the loop filter (4). Is controlled, and a clock signal having a frequency of 256 times the sampling frequency fs is obtained at the output side of the oscillator (5). The frequency of this clock signal may be any value as long as it is a frequency required for demodulation. (6) is an oscillator (5)
Of the frequency divider (6), and the output of the frequency divider (6) is supplied to the other input side of the phase comparator (3). The phase comparator (3), the loop filter (4), the oscillator (5) and the frequency divider (6) form a so-called PLL circuit (7).

(8) is a demodulation circuit that demodulates (decodes) the input signal from the input terminal (1) based on the clock signal from the PLL circuit (7). For example, 16-bit serial data DATA and its shift Clock BCK, L channel, R
The channel identification clock LRCK is output. (9) converts the demodulated signal from the demodulation circuit (8) from a serial signal to a parallel signal (hereinafter referred to as S / P conversion) S / P
The conversion circuit outputs 16-bit parallel data per channel at the falling edge of the clock LRCK, that is, at the end of the R channel, as will be described later. Reference numeral (10) is a 16-bit parallel input current output type D / A conversion circuit for converting the output of the S / P conversion circuit (9) from a digital signal to an analog signal.

(11) is a sample and hold circuit that samples and holds the output of the D / A conversion circuit (10). A D-type flip-flop circuit (12) is provided to form a sampling timing signal for the sample-hold circuit (11), and an input terminal D of the flip-flop circuit (12) is provided.
Is supplied with the clock LRCK from the demodulation circuit (8), and its clock terminal CK is supplied with the output of the frequency divider (6) of the PLL circuit (7) through the inverter (13). And
The outputs of the output terminal Q and the inverting output terminal of the flip-flop circuit (12) are supplied to the sample hold circuit (11) as sampling timing signals.

As the sample and hold circuit (11), for example, the one shown in FIG. 3 is used. That is, a differential amplifier (11a) is provided, and the inverting input terminal of this differential amplifier (11a) is connected to the D / A conversion circuit (1
0) (Fig. 1) connected to the output side of the switch circuit (11
A switch circuit (11c) is provided on the input side and ground side of b). The inverting input terminal of the differential amplifier (11a) is grounded, the capacitor (11d) is connected between the inverting input terminal and the output terminal, and the output terminal of the differential amplifier (11a) and the switch circuit (11b) are connected. ) Is connected to the resistor (11e) on the input side. The switch circuits (11b) and (11c) are controlled by the inverted output and the output of the flip-flop circuit (12), respectively. The sample and hold circuit (11) is the third
As shown in the figure, when the switch circuit (11b) is off and the switch circuit (11c) is on, it is in the hold state. Contrary to the state in the figure, the switch circuit (11b) turns on and the switch circuit (11c) When is off, the sample status is set.

Further, in FIG. 1, (14) is a filter provided on the output side of the sample and hold circuit (11), and (15) is an output terminal.

Next, the rotating operation of FIG. 1 will be described with reference to FIG.

Now, the input signal Rx as shown in FIG. 4A is supplied from the input terminal (1). The upper side of FIG. 4A shows the input signal Rx in detail in a waveform, and the lower side of FIG. 4A schematically shows the same input signal Rx. Such an input signal Rx is supplied to the detection circuit (2), and the detection circuit (2) directly supplies the input signal Rx to the exclusive OR circuit (2a) as shown in FIG. By supplying after the delay, all edges of the input signal Rx are extracted at the output side of the exclusive OR circuit (2a) although not shown. When all the extracted edges are passed through the retriggerable mono multivibrator (2e), the distance between the edges is about 450n sec.
The pulse is output in the above part. For input signal Rx,
The portion where this pulse is output is only the portion where the L channel and R channel synchronization signals (SYNC) are present.
The output of this pulse is one on the R channel, but two on the L channel in succession.
By passing this through a retriggerable mono multivibrator (2f), a sync signal 2FSR as shown in FIG. 2B of 1 edge (falling edge) per 1 SYNC is detected. This synchronization signal 2FSR has a frequency twice the sampling frequency fs as described above.

The synchronization signal 2FSR from the detection circuit (2) is supplied to the phase comparator (3) of the PLL circuit (7), where it is phase-compared with the feedback signal 2FSV (Fig. 4F) from the frequency divider (6). It Then, the phase comparison error signal is converted into a DC voltage by the loop filter (4), the oscillation frequency of the oscillator (5) is controlled based on this DC voltage, and the output side of the PLL circuit (7), that is, the output of the oscillator (5). On the side, the clock signal RxCP for input signal Rx decoding is obtained. The relationship between the input signal Rx and the clock signal RxCP when the input signal Rx has no jitter is shown in FIG.

As a characteristic of the PLL circuit (7), if a feedback signal 2FSV from the frequency divider (6) can follow the closed loop transfer function when the phase input is added as jitter to the synchronization signal 2FSR, It can be divided into a flat follow-up region as shown by a curve a in FIG. 5 and a downward-sloping cut-off region as shown by a curve b. The frequency of this flat part is the frequency of the PLL circuit, and here we show the case where there is a difference of 94 Hz and 8.5 kHz, or a ratio value of about 90 times. In this case, the shaded area shown in FIG. 5 represents the difference in the jitter tracking characteristics which differs depending on the band of the PLL circuit.

The clock signal RxCP from the PLL circuit (7) thus obtained is supplied to the demodulation circuit (8) together with the input signal Rx from the input terminal (1). The input signal Rx and the clock signal RxCP supplied to the demodulation circuit (8) are represented as shown in FIG. 6 when the input signal Rx has no jitter, and one cell of the input signal Rx shown in FIG. 6A is shown. If there are two positive edges of the clock signal RxCP shown in FIG. 6B, the decoding is possible. As a result, the fourth side is provided on the output side of the demodulation circuit (8).
16-bit serial data DATA as shown in FIG. C, a clock BCK for shifting the data, and LRCK for identifying the L channel and the R channel are obtained.

These outputs are supplied to the S / P conversion circuit (9), and 16-bit parallel data PDATA per channel as shown in FIG. 4D is S / P converted at the falling edge of the clock LRCK, that is, at the end of the R channel. It is available at the output of the circuit (9). This parasal data PDATA is the D / A conversion circuit (1
0) and output current I _OUT corresponding to the parallel data PDATA as shown in FIG. 4E is taken out as an analog signal. This output current I _OUT
The settling time required for switching is about 350 nsec. The output current I _OUT has a relationship of ± 1 mA with respect to the full bit, that is, 16 bits. This output signal I _OUT is supplied to the sample and hold circuit (11).

The clock LRCK from the demodulation circuit (8) is supplied to the input terminal D of the flip-flop circuit (12), and the feedback signal 2FSV from the frequency divider (6) is inverted by the inverter (13) to flip-flop circuit (12). The signal APT shown in FIG. 4G is obtained at the inverting output terminal of the flip-flop circuit (12) by supplying the signal APT to the clock terminal CK of the output terminal Q.
, A signal ▲ ▼ shown in FIG. 4H is obtained.
These signals APT and ▲ ▼ are supplied to the sample hold circuit (11) as sampling timing signals.

When the signal APT is "0" and the signal ▲ ▼ is "1", the sample-hold circuit (11) turns off the switch circuit (11b) and turns on the switch circuit (11c) in the hold state. On the other hand, signal APT is "1" and signal ▲ ▼
Is 0, the switch circuit (11b) is turned on, the switch circuit (11c) is turned off, and the sample state is reached. By repeating this operation, the sample and hold circuit (11)
An output voltage V _OUT as shown in FIG. _4I is obtained at the output side of. This output voltage V _OUT is taken out to the output terminal (15) as a desired analog signal after removing unnecessary components such as harmonic components by the filter (14). In this way, D / A conversion can be easily performed even if the audio data is biphase mark modulated.

By the way, the data cell of the input signal Rx and the clock signal RxCP
When the position of is as shown in FIG. 6 and there is no jitter, accurate decoding was possible as described above. However, if the band of the PLL circuit (7) is narrowed, if the input signal Rx has jitter (above that band), the input signal Rx and the clock signal RxCP will not match in phase, and decoding will not be possible. For example, the band of the PLL circuit (7) is set to a narrow band of 94 Hz,
When jitter such as that shown in Fig. 7 is added to the input signal Rx,
The relationship between the input signal Rx and the clock signal RxCP is as shown in FIG. 8, and almost no decoding was possible. The seventh
In the figure, A ₁ has an average jitter amplitude of 20 to 30 nsec.
₂ shows that the amplitude reaches about ± 100 nsec as a pop noise.

On the other hand, when the bandwidth of the PLL circuit (7) is expanded to 8.5kHz, the relationship between the input signal Rx and the clock signal RxCP becomes as shown in Fig. 9, and almost the relative jitter of the input signal Rx and the clock signal RxCP can be observed. It's gone, and decoding is complete.
From this, it can be seen that a wider band of the PLL circuit is better for decoding.

Next, if decoding is not enough, for example,
When experimenting with the presence of jitter as shown in Fig. 10,
It was confirmed that the wider the band of the PLL circuit (7), the worse the distortion rate. Fig. 11 shows this state. The curve a shows the case where the band is 8.5 kHz and the curve b shows the case where the band is 94 Hz. The distortion rate is worse in the case of the band 8.5 kHz than in the case of the band 94 Hz. You can see that

This occurs by the mechanism shown in FIG. That is, when the frequency band of the PLL circuit (7) is wide, the output 2FSV of the frequency divider (6) of the PLL circuit (7) contains jitter, and this is used as a clock signal in the flip-flop circuit (12). The signal APT as the sampling timing signal of the sample and hold circuit (11) obtained at the output side,
Jitter is also mixed in ▲ ▼, and the output voltage V _OUT of the sample and hold circuit (11) when no jitter is mixed is the timing signal APT as shown on the left side of FIG.
(And ▲ ▼) changes, but if jitter is introduced, the output voltage V of the sample and hold circuit (11)
_OUT changes as shown on the right side of FIG. That is, when the sample time becomes short due to the influence of jitter, the code a
As shown in, the level becomes lower by the curve corresponding to the sampling time constant, and when the sample and hold times become shorter, the level becomes narrower by the area indicated by the symbol b,
These are factors that worsen the distortion rate. In FIG. 12, t ₁ , t ₂ , and t ₃ indicate that the timing time is shortened by the jitter.

As described above, there is a drawback whether the band of the PLL circuit (7) is wide or narrow, because the requirements for the PLL circuit (7) are different between the decoding performance and the sample-hold performance. That is, from the viewpoint of decoding performance, it is preferable that the bandwidth of the PLL circuit is wide, and conversely, from the viewpoint of sample and hold performance, that is, the distortion factor, it is preferable that the bandwidth of the PLL circuit is narrow.

FIG. 13 shows a second embodiment of the present invention made in view of such a point. In FIG. 13, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. To do.

In this embodiment, the phase comparator (16), the loop filter (1
PLL circuit (19) consisting of 7) and voltage controlled oscillator (18)
For supplying the output of the detection circuit (2) to one input side of the phase comparator (16) and supplying the output of the oscillator (18) to the other input side of the phase comparator (16). .
The output of the oscillator (18) is supplied to the clock terminal CK of the flip-flop circuit (12) via the inverter (13). Other configurations are the same as in FIG.

The oscillation frequency of the oscillator (18) of the PLL circuit (19) is twice the sampling frequency fs, and therefore the signal A2FS supplied from the oscillator (18) to the other input side of the phase comparator (16).
Is the same in frequency as the signal 2FSV supplied to the other input side of the phase comparator (3) of the PLL circuit (7). However, while the signal 2FSV contains a lot of jitter, the signal 2FSV
A2FS has less jitter. That is, in this embodiment, the decoding PLL circuit (7) is used with a wide band and the sample and hold PLL circuit (19) is used with a narrow band. As a result, even if the jitter shown in FIG. 7 is added to the input signal Rx, it can be accurately decoded by the demodulation circuit (8), and the distortion factor characteristic at this time is the 94 Hz band indicated by the curve b in FIG. It became similar to.

In the above embodiment, the D / A conversion circuit (10) has been described as being of the current output type, but it may be of the voltage output type, in which case a resistor is provided on the input side of the sample and hold circuit (11). Be sure to insert one container.

Further, the PLL circuits need not necessarily be combined in parallel as shown in FIG. 13 as long as they have different bands, and a narrow band PLL circuit is incorporated with the output of the wide band PLL circuit as an input. That is, a cascade connection may be used. At this time, the output of the frequency divider (6) of the PLL circuit (7) is supplied to one input side of the phase comparator (16) of the PLL circuit (19).

Further, in the above description, the case where the sampling frequency is 44.1 kHz has been described as an example, but the present invention is not limited to this, and other sampling frequencies such as 48 kHz and 32 kHz can be similarly applied.

〔The invention's effect〕

As described above, according to the present invention, a synchronizing signal is detected from a digital input signal, the synchronizing signal is phase-locked to obtain a clock signal of a predetermined frequency, the input signal is demodulated based on this clock signal, and the demodulated signal is obtained. Is D / A-converted, and the signal after the D / A conversion is sampled and held by a predetermined sampling timing signal. Therefore, a special digital signal such as a digital audio interface signal in which audio data is biphase-mark-modulated. Even an input signal can be easily D / A converted.

In addition, since a plurality of PLL circuits are used exclusively for decoding and sample and hold in consideration of the respective bands, even if the input signal contains jitter, it can be decoded and D / A converted. It is possible to prevent the occurrence of distortion in the sample and hold circuit at the time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing an example of a main part of the present invention.
FIG. 4 is a diagram for explaining the operation of FIG. 1, and FIGS.
FIG. 12 is a diagram for explaining the present invention, FIG. 13 is a block diagram showing another embodiment of the present invention, and FIG. 14 is a diagram for explaining the digital audio interface format. (2) is a sync signal detection circuit, (7) and (19) are PLL circuits, (8) is a demodulation signal, (9) is a serial / parallel (S / P) conversion circuit, and (10) is a digital / analog ( D / A) conversion circuit, (11) a sample and hold circuit, and (12) a D-type flip-flop circuit.

Claims (1)

[Claims] 1. A detection circuit for detecting a synchronization signal from an input signal including at least a synchronization signal and audio data modulated by a predetermined modulation method, and a wideband first circuit for phase-locking to the detected synchronization signal.
A PLL circuit, a narrow-band second PLL circuit that phase locks to the synchronization signal detected by the detection circuit, and a demodulation signal in response to the clock signal and the input signal from the first PLL circuit A demodulation circuit, D / A conversion means for converting the demodulation signal from the demodulation circuit from a digital signal to an analog signal, and an output of the D / A conversion means for the demodulation signal and the second signal.
A D / A converter comprising a sample and hold means for sampling and holding with a sampling timing signal formed from a clock signal from a PLL circuit.