JPS6217911B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for extracting a timing signal from a burst signal in a TDMA (time division multiple access) system.

In the TDMA system, M cylinder data signal sequences (M:
The so-called offset PSK (Phase
Shift Keying) method has been attracting attention recently. This offset PSK communication system has little envelope fluctuation in its modulated wave, and is not affected by its nonlinear characteristics even if it passes through a transmission line with a nonlinear response. Therefore, this communication method should be applied to systems such as satellite communication systems where using the amplifier on board the satellite (transponder) at the saturation level will make more effective use of the transmission power and will lead to a reduction in system costs. Effective. However, compared to conventional PSK modulation, offset modulation is added, there is less envelope fluctuation because it is transmitted at a saturation level, and the signal-to-noise ratio is not good in normal communication systems. A number of problems must be solved in realizing a modem device.

In the burst communication method, a transmission operation is performed only when transmitting information. The advantages of this type of burst communication method are that the required power can be reduced;
It is possible to communicate between multiple transmitting stations using the same satellite and the same frequency. For the above reasons, a burst offset PSK communication system is adopted in systems such as satellite communication, but in this communication system, it is necessary to reproduce the reference carrier wave and timing signal for each received burst. However, such reference signals such as a reference carrier wave and a timing signal are not reproduced simultaneously with the arrival of a burst, but are generally accompanied by a certain time delay. The time required to reproduce this reference signal is called acquisition time. During this acquisition time, no information can be transmitted because a reference signal has not been established. Therefore, at the leading edge of a burst, a preamble word (usually used for synchronization to promote the establishment of a reference signal) that does not contain any communication information and continues for a time corresponding to the acquisition time is used. , and the word for transmitting station identification are called prefix words, but here only the word for synchronization will be called prefix word.), followed by an information word. The method used is to continue. In such communication performed by bursts consisting of a prefix word and an information word, it is required to make the prefix word as short as possible in order to improve communication efficiency. That is, the performance required of the prefix is to reliably transmit information regarding the reference carrier wave and information regarding the timing signal within a short period of time. Furthermore, as additional performance, it is desirable to include information for detecting the boundary between the prefix part and the information word part of the burst on the receiving side.

From the standpoint of shortening the acquisition time for timing signal reproduction and reducing the phase jitter, it is desirable that the prefix be a deeply modulated wave, but from the standpoint of reproducing the reference carrier wave and shortening the acquisition time, it is desirable to use a deep modulation wave. contradicts. Also, the information word that follows after the prefix is offset.
In the case of a PSK modulated wave, the envelope fluctuation of the modulated wave is originally small, and in most cases the nonlinear transmission path is output at its saturation level by taking advantage of this characteristic, so the timing signal is generated by envelope detection. is difficult to extract.

An object of the present invention is to provide a circuit for regenerating a timing signal from an offset PSK modulated wave that solves these contradictory problems and difficulties.

For this reason, the present invention employs a method in which appropriate phase modulation is applied over the entire prefix word, and a timing signal and a carrier wave are simultaneously reproduced from this modulated wave. Further, as a reproduction method, phase detection such as delayed detection or frequency discrimination method such as FM detection is adopted.

According to the present invention, the carrier wave has a phase α and a phase β (α
and β are arbitrary phases, but β − α≠ο, π) A terminal for inputting a burst signal having a prefix word and an information word connected after the prefix, and this input means connected to a terminal for extracting a timing signal from a prefix portion; a reference timing signal generating means for changing an oscillation frequency in response to a control signal and outputting a reproduction timing signal; and an output of the timing signal extracting means and a reference timing. phase difference detection means for generating the control signal in response to the phase difference with the output of the signal generation means; gate means for selectively supplying the signal to the reference timing signal generation means; and gate signal detection for detecting the boundary between the prefix word and the information word of the burst signal to generate a gate signal and supplying the gate signal to the gate means. A timing signal regeneration circuit including means is obtained.

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Reference numbers 1 and 8 indicate input terminals. 2 is a timing signal extraction circuit, which is installed at the beginning of the received burst and uses a method such as FM detection, delay detection, or envelope detection, depending on the communication line used, and is installed at the beginning of the received burst to set the phase α to the carrier wave. Phase β (β−α
A timing signal is extracted from the prefix part that is phase-modulated so as to alternately take ≠ο, π). The timing signal component extracted by the extraction circuit 2 is supplied to the phase comparator circuit 4 after phase jitter components and amplitude jitter components are removed by a jitter removal circuit 3 (for example, composed of a bandpass filter and an amplitude limiter). Ru. The phase comparator 4 compares the phase of the output of the reference clock oscillation source 6 that has passed through the phase variable circuit 5 with the output of the jitter component removal circuit 2, detects a phase difference component, and supplies the detected phase difference component to the gate circuit 7. do. The gate circuit 7 is supplied with the signal detected by the gate signal detection circuit 8 , and when the gate signal is on, it appropriately amplifies the previous phase difference component and supplies it to the phase variable circuit 5 . As a result, a reference clock signal whose phase is brought closer to the received timing signal is output to the output terminal 9.
The signal is then supplied to other receiving circuits. The above operation continues while the gate signal supplied to the gate circuit 7 is on to form a feedback circuit, and the phase of the reference clock oscillation source 6 output from the terminal 9 is the timing of the received digital signal. It is controlled to be closer to the phase. However, while the gate signal is off, the gate circuit 7 acts to hold the phase variable circuit control voltage immediately before turning off.
Therefore, the stability of the timing frequency of the received signal is good, and the stability of the reference clock oscillation source 6 is also good. Let Δθ be the follow-up word difference for Δθ, and Δτ be the time interval that the gate circuit must maintain, then the phase error θ _s of the recovered clock signal is given by equation F (1) for one received burst.

θ _s = △θ + 2π・△・△τ (rad) (1) In a normal digital signal system, the allowable phase error θ _s of the reproduction timing signal when identifying and reproducing the demodulated waveform in the demodulation circuit on the receiving side is approximately 0.2
(rad) or less, so △
・If the characteristics of the phase control feedback circuit can be configured so that △τ can be established and the value of △θ can be made sufficiently small, the timing signal regeneration circuit according to the present invention can easily be adopted in a digital communication system. be understood.

FIG. 2 shows a block diagram of a specific embodiment of the timing signal extraction circuit 2 of the embodiment described in FIG. This embodiment shows the configuration of a circuit that extracts a timing signal from a prefix portion of a received burst signal using a delay detection method. Input terminal 1
The input received signal passes through the delay circuit 2 and is delayed by a predetermined time T/2 or T (T: symbol period = reciprocal of the timing frequency) before being supplied to the phase detection circuit 13. On the other hand, the received signal input from terminal 1 is partially branched to the phase detection circuit 1.
3 to form a delay detection circuit. Delay circuit 1 in the delay detection circuit shown in this embodiment
If the delay time of 2 is selected as T, or if the previously mentioned FM detection circuit is used for clock extraction, the detection output generated when receiving the prefix part will be _s /2, where _s is the timing signal frequency. It is sent out as follows. Therefore, in this embodiment, the case is shown in which the delay time of the delay circuit 12 is selected as T, and the output of the phase detection circuit 13 is inputted to the doubling circuit 14 to obtain the timing signal frequency _s , which is sent to the terminal 11. There is. Also, using an envelope detector as this timing extraction circuit is a simple and good method, but if the received signal is transmitted through a nonlinear circuit with a saturated output, the timing signal included in the envelope detection output This is not a good method because the frequency components become very small and the signal-to-noise ratio of the extracted signal becomes poor. This can be said to apply to cases where, for example, burst-like offset PSK modulation is employed in the information word portion, since the information is received after passing through a nonlinear transmission circuit.

FIG. 3 shows a block diagram of a specific embodiment of the gate circuit 7 of the embodiment described in FIG. That is, the phase comparison voltage inputted from the terminal 17 is suitably amplified by the amplifier 18, charges the capacitor _C1 through the switch _S1 , and then is supplied to the amplifier 19 having a high input impedance. This operation occurs when the gate signal supplied from terminal 15 that drives switch S ₁ is a voltage that turns switch S ₁ on, and when the voltage is such that it turns off switch S ₁ , it turns off. The potential charged in the capacitor C ₁ just before the current is maintained is maintained as it is. This is because the amplifier 19 has a high input impedance, so the previously charged potential is applied to the switch _S1 .
This is because it is retained without leaking while it is off. Therefore, in this gate circuit, when the gate signal supplied to the terminal 15 is a voltage that turns on the switch _S1 , the phase comparison voltage supplied to the terminal 17 is appropriately amplified and outputted from the terminal 16, and the phase is varied. A timing signal regeneration feedback circuit is formed by feeding back to circuit 5, and when the gate signal is a voltage in the direction of turning off switch _S1 , the output phase of the regenerated timing wave is maintained at the phase immediately before turning off switch _S1 . It acts like this.

FIG. 4 shows a block diagram of one embodiment of the gate signal detection circuit 8 among the embodiments described in FIG. In this embodiment, a timing signal extraction circuit using a delay detection circuit shown in FIG. 2 is used to extract a timing wave signal, and the timing frequency _s
It removes the phase jitter component of the timing wave signal extracted by passing it through the band wave generator 20 centered at the half frequency (= 1/2 _s) , and at the same time removes the phase jitter component of the timing wave signal which is added in the middle of the transmission path and increases until it is received. The signal with improved signal-to-noise ratio is detected by the detector 21 to generate a gate signal, which is output from the terminal 15.The received burst signal If the prefix placed at the beginning of is a signal that has been phase-modulated so that the carrier wave alternates between phase α and phase β, the delay detection circuit output has _s /2 ( _s : timing frequency) However, in the information word part following this prefix word, the output of the differential detection circuit becomes a random signal and does not have a specific frequency component.Therefore, a band wave with a center frequency of _s /2 is transmitted. After passing through the detector 20, the amount of signal passing through the prefix word part and the information word part is significantly different.For this reason, this output is power detected by the detector 21, and reception is determined by the magnitude of the detection level. A gate signal can be created that distinguishes whether a signal is a prefix word part or an information word part.This process will be explained in more detail later using FIG.

FIG. 5 is a block diagram showing another embodiment of the present invention. In Fig. 5, components 1, 2,
3, 4, 5, 6, 7 and 9 are the same as the components in FIG.

In this embodiment, a gate signal for driving the gate circuit 7 is supplied from the outside through a terminal 22. For example, in a communication system such as a satellite communication system, by receiving other pilot signals in advance, it is possible to know at what timing in each frame period a signal to be received will be received. In such a case, a gate signal can be created by performing a logical operation based on this timing information. The present embodiment was devised in consideration of such a case.

FIG. 6 is a block diagram showing still another embodiment of the present invention. Components 1, 2, 3, 4, 7,
8 and 9 are the same as the components shown in FIG. In this embodiment, most of the components are the same as in FIG. 1, but the variable phase circuit 5 and reference clock oscillation source 6 shown in FIG. 1 are replaced with a voltage-controlled reference clock oscillation source (Vcxo) 23. There is. This is because the output of the gate circuit 7 drives the variable phase circuit 5 and controls the output phase of the reference clock oscillation source 6, which constitutes a similar feedback circuit. This is easily understood since it has the same function as driving the oscillation source (Vcxo) 23.

7a to 7d are time charts showing the phase relationship between a prefix word and an information word, taking a burst-like offset PSK modulated wave as an example, in order to make the meaning of the present invention more concrete. Figure a shows the received waveform.

In addition, b is the phase change of this received waveform, c is the corresponding output of the gate signal detection circuit or the gate signal waveform appearing at the terminal 22, and c is the timing signal reproduction waveform appearing at the output terminal 10 of the phase comparator 4. Shown in d. Component 10 in Figure 7a
1 represents the prefix word part and the information word part which has been PSK modulated by 102 offset. Also, 10 of Figure 7b
3 represents the phase change of the prefix word part, and 104 represents the phase change of the information word part. FIG. 7c shows the waveform of the gate signal, in which the switch S1 shown in FIG. 3 is turned on only during the time interval shown at 105, and _{switch S1} is turned off at times other than those shown at 105. .
Further, FIG. 7d shows a timing signal regenerated waveform, of which 106 is the timing signal regenerated waveform whose time is maintained by the gate circuit 7 shown in FIG. The timing signal reproduction waveform of the process is shown.
That is, if we compare it with the gate signal in c of the same figure, the timing signal is regenerated while the gate signal is in the state 105 (on), and when it is no longer in the state 105 (off), the previous signal is regenerated. The holding motion process is understood.

FIG. 8 is a vector diagram showing the phase relationship shown by waveforms 103 and 104 in FIG. 7.
The phase of the prefix part is vectors 115 and 116
The phase in the information word portion is represented by vectors 111, 112, 113 and 114. As is clear from this vector diagram, vector 115 can be divided into vectors 117 and 118. Also, vector 116 can be divided into vectors 117 and 119. Therefore, the phase in the prefix part is continuous in time and represents a component in the same phase as vector 111, vector 117, and vector 118, which occurs alternately in time.
and 119. From a signal containing such continuous components, the continuous components, that is, the reference carrier wave, can be extracted directly using a phase synchronization circuit or a narrow band pass filter without using a phase modulation component removal circuit, so that the continuous components, that is, the reference carrier wave, can be extracted within a short acquisition time. The reference carrier wave can be regenerated. Further, as described above, the timing can be reproduced from the vectors 118 and 119 that occur alternately in the same short acquisition time.

As stated above, this invention is particularly effective when used to reproduce a timing signal from a burst-like offset PSK modulated signal, and thus was explained using this as an example, but information words can be used in any modulation format. It is clear that the timing signal regeneration circuit according to the present invention can be applied to any digitally modulated wave.

As explained above, according to the present invention, a timing signal with less phase jitter can be regenerated within a short acquisition time on the receiving side of burst digital communication, and the information word contained in the digital signal can be an offset modulated signal. It is particularly effective in certain cases and will greatly contribute to the development of satellite communication systems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing signal extraction circuit 2 of FIG.
3 is a block diagram of an embodiment of the gate circuit 7 of FIG. 1, FIG. 4 is a block diagram of an embodiment of the gate signal extraction circuit 8 of FIG. 1, and FIG.
FIG. 6 is a block diagram showing another embodiment of the invention, FIG. 6 is a block diagram showing still another embodiment of the invention, and FIG. 7 is a block diagram showing a burst offset PSK modulated wave to which the invention is applied. This is a time chart showing the phase relationship between the locator word and the information word, in which a shows the received waveform, b shows the phase change of the received waveform, and c shows the phase relationship of the received waveform.
is a gate signal waveform, d is a timing signal reproduction waveform diagram, and FIG. 8 is a vector diagram showing the phase relationship between the prefix word and the information word shown in FIG. 7. In the figure, 1... Received signal input terminal, 2... Timing signal extraction circuit, 3... Jitter component removal circuit, 4...
Phase comparator, 5... Phase variable circuit, 6... Reference clock oscillation source, 7... Gate circuit, 8... Gate signal detection circuit, 9... Reproduction timing signal output terminal, 22... External gate signal input terminal , 23...
This is a voltage controlled reference clock oscillator.

Claims (1)

[Claims] 1 A prefix word in which the carrier wave is phase modulated so that the phase α and phase β (α and β are arbitrary phases, however, β − α ≠ ο, π) and the information word that follows this prefix word. a terminal for inputting a burst signal, a means connected to the input terminal for extracting a timing signal from the prefix portion, and a reference timing signal generator for changing an oscillation frequency in response to a control signal and outputting a reproduction timing signal. means, phase difference detection means for generating the control signal in response to a phase difference between the output of the timing signal extraction means and the output of the reference timing signal generation means, and the phase difference detection means and the reference timing signal generation means. gate means connected between the means and the means for selectively supplying the control signal to the reference timing signal generating means in response to a gate signal; and detecting a boundary between the prefix word and the information word of the burst signal. and gate signal detection means for generating the gate signal and supplying the gate signal to the gate means.