JP3549958B2 - Symbol clock recovery method and apparatus - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a symbol clock reproducing method for reproducing a symbol clock, which is one component of a receiving apparatus, in an OFDM (Orthogonal Frequency Division Multiplexing) transmission system, and a symbol clock reproducing apparatus used therefor.
[0002]
[Prior art]
Conventionally, in a receiving apparatus that receives an OFDM signal, the symbol timing and the symbol clock required for demodulation are based on Ch. Dosch et al, "First public demonstrations of COFDM / MASCAM. A milestone for the future of radio broadcasting", EBU Review-Technical. 232, Dec. According to 1988, first, the transmitting side transmits a synchronization symbol such as a sweep signal at fixed time intervals (a plurality of symbol periods), and the receiving side transmits the same signal as the signal generated and transmitted on the transmitting side in the receiving device. Generate and correlate with the received signal to form a steep pulse signal. Since the formed pulse signal is generated every time a synchronization symbol is received, a symbol timing, an FFT (Fast Fourier Transform: fast Fourier transform) window, and a demodulation required for demodulation are required based on the pulse signal. The reproduction symbol clock is generated.
[0003]
[Problems to be solved by the invention]
However, according to the above prior art, it is assumed that a synchronization symbol is transmitted on the transmission side, but this synchronization symbol does not contribute to information transmission. Therefore, it is necessary to increase the interval between the synchronization symbols in order not to lower the transmission efficiency. However, on the other hand, if the interval between the synchronization symbols is large, it takes a long time to pull in a PLL (Phase Lock Loop) of the symbol clock, and the time accuracy of the generated symbol clock is deteriorated.
[0004]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a symbol clock recovery method capable of obtaining a symbol clock required for demodulating an OFDM signal on a receiving side from an information-bearing OFDM signal itself without requiring a synchronization symbol. In this case, it is possible to contribute to improvement of transmission efficiency, shortening of a PLL clock pull-in time of a symbol clock, improvement of follow-up of clock synchronization, and the like.
[0005]
[Means for Solving the Problems]
According to the present invention, as an inherent characteristic of an OFDM signal, in the case of an OFDM signal having a guard interval period, a signal having an effective symbol period length is integrated within one transmission symbol period (a period obtained by adding a guard interval period to an effective symbol period). A symbol clock regeneration method and apparatus which effectively utilizes the property of becoming zero and reproduces a symbol clock from an OFDM signal itself which is not particularly provided with a synchronization symbol described in the related art.
[0006]
That is, according to the symbol clock recovery method of the present invention, for a sample value obtained by sampling an OFDM signal having a guard interval period, the sample value is added over one effective symbol period; Extracting a symbol clock by passing through the step of performing a phase comparison, a step of performing a phase comparison between both signals of the reproduced symbol clock and the extracted symbol clock, and controlling an oscillation output frequency of the voltage controlled oscillator based on a result of the phase comparison. And extracting the reproduced symbol clock from the output side of the voltage-controlled oscillator.
[0007]
Further, in the symbol clock reproducing method of the present invention, a step for obtaining an absolute value of the result of the addition is interposed between the step of adding and the step of extracting the symbol clock by passing the signal through the band-pass filter. It is characterized by the following.
[0008]
The symbol clock reproducing apparatus according to the present invention further comprises: adding means for adding a sample value obtained by sampling an OFDM signal having a guard interval period over one effective symbol period; A band-pass filter for extracting a clock, a voltage-controlled oscillator for extracting a reproduced symbol lock, and a phase between both the reproduced symbol lock and the symbol lock extracted from the band-pass filter extracted by the voltage-controlled oscillator. Means for performing a comparison and controlling an oscillation output frequency of the voltage-controlled oscillator based on a result of the phase comparison.
[0009]
Further, in the symbol clock reproducing apparatus according to the present invention, an absolute value circuit for obtaining an absolute value of an output signal of the adding circuit is interposed between the adding means and the bandpass filter.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described in detail based on embodiments with reference to the accompanying drawings.
FIG. 1 is a diagram illustrating the signal waveform of an OFDM signal and the fact that the signal waveform is formed by combining a large number of modulated waves.
As shown in FIG. 1, an OFDM signal is a combination of a large number of digitally modulated waves consisting of k = 1, k = 2, ---, k = 20, ---. This is performed on a symbol basis. Each symbol is composed of an effective symbol period t _s and a guard interval period, a guard interval period has a a repeat of the rear portion of the signal waveform of the valid symbol period.
[0011]
Each carrier frequency _f k of the OFDM (k = 1, k = 2, ---, k = 20, ---) , in the baseband _f k = k / _{t s} (where, k is 1, - −−)
Is defined by Therefore, 1 become effective symbol period t _s zero is integrated signals within, also samples the OFDM signal period T = t s _{/ N} (where, N is the number of sample values) When sampled at its N The sum of the sample values is also zero.
[0012]
In the case of an OFDM signal having a guard interval period, as shown in FIG. 2A, the signal during the guard interval period is a cyclically repeated signal of the effective symbol period. integrating over the effective symbol period t _s length signals within the period Te in it becomes (FIG. 2 (b)) and still zero, integrating over two symbol periods successive (FIG. 2 (c)) and zero No.
[0013]
Thus, for a sample value obtained by sampling the OFDM signal at the sampling period T, the period during which the sum of N sample values becomes zero is equal to the length of the guard interval period. As a result, when successive addition of N sample values is successively repeated for an incoming OFDM signal, a signal having a waveform as shown in FIG. 3 is obtained, for example. Since the signal waveform contains a frequency component that matches the symbol timing frequency, the symbol clock frequency component is reduced by passing the signal obtained by the addition through a band-pass filter that passes this frequency component signal. Can be extracted.
[0014]
Next, a description will be given of a symbol clock reproducing method and apparatus according to the present invention configured based on the above principle.
FIG. 4 is a block diagram showing one embodiment of the symbol clock reproducing apparatus of the present invention.
In FIG. 4, the symbol clock reproducing apparatus of the present invention is roughly classified into two blocks from the viewpoint of signal processing. That is, a symbol clock extraction circuit 1 and a PLL circuit 2 are provided. In the former, OFDM signal that is input to the input terminal 3 (This signal is sampled at a period T) are sequentially repeatedly summed over one effective symbol period t _s first by the addition circuit 4, in FIG. 3 described above The signal has the waveform shown. This signal is sent to the absolute value circuit 5, and the signal on the negative side is turned back to the positive side, so that the signal has the waveform shown in FIG. The signal obtained by the absolute value circuit 5 is passed through a band-pass filter 6 for passing the symbol clock frequency component of the OFDM signal, and the symbol clock frequency component shown in FIG. Have been.
[0015]
In the above, the adding circuit 4 for adding the input OFDM signal over one effective symbol period t _s is configured, for example, as shown in FIG. Here, the FF denoted by reference numeral 11 represents a flip-flop or a one-clock register (both act as a one-clock delay element). The input data arriving at the input terminal 3 is shifted by the shift register 12 constituted by using these delay elements, and all the data of one effective symbol period are added by the adder 13. As described above, a result obtained by adding the input OFDM signal over one effective symbol period is obtained on the output side of the adder 13.
[0016]
Next, the PLL circuit 2 includes a voltage controlled oscillator 7 which oscillates at a frequency (clock frequency) near M times (M is 1, 2, 3, ---) the symbol clock frequency. The signal is sent to the frequency divider 8 and the frequency is divided by M to become a signal (reproduced symbol clock) equivalent to the symbol clock frequency. This signal and the symbol clock output from the symbol clock extracting circuit 1 are applied to each input terminal of the phase comparator 9, and the phases of the two signals are compared, and a signal (voltage) corresponding to a phase difference is output from the output terminal. Output from The output phase difference signal is applied to a control input terminal of the voltage controlled oscillator 7 via a loop filter 10 including a low-pass filter or the like for absorbing a sudden change.
[0017]
As described above, the output signal of the frequency divider 8 in the PLL circuit 2 is locked to the symbol clock of the incoming OFDM signal, and the output signal (reproduced clock) of the voltage controlled oscillator 7 is also the symbol clock of the incoming OFDM signal. And a signal maintaining a constant phase relationship, and a reproduced clock having a timing which is an accurate reference for operating the OFDM receiver can be obtained.
[0018]
In the embodiment of the symbol clock reproducing apparatus of the present invention described above with reference to FIGS. 4 and 6, not all the circuit elements included in the figures are necessary. For example, the absolute value circuit 5, the frequency divider 8, The loop filter 10 can be omitted depending on the level of circuit design.
[0019]
In particular, the frequency divider 8 can be omitted by selecting the oscillation frequency of the voltage controlled oscillator 7 as the symbol clock frequency of the incoming OFDM signal. However, by selecting the oscillation frequency of the voltage-controlled oscillator to be M times the symbol clock frequency, the output signal of the voltage-controlled oscillator can be used as a reproduction clock for OFDM demodulation. .
[0020]
【The invention's effect】
According to the present invention, when reproducing a clock necessary for demodulating an OFDM signal, a synchronization symbol is not required as in the related art, and the signal can be obtained from the OFDM signal carrying information. In addition, it is possible to shorten the PLL pull-in time when reproducing the symbol clock, expand the pull-in frequency range, and improve the follow-up of clock synchronization.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a signal waveform of an OFDM signal and that the signal waveform is formed by a combination of a large number of modulated waves.
FIG. 2 is a diagram showing the results of a case where an OFDM signal waveform having a guard interval period is integrated over one effective symbol period within one symbol period and over two symbol periods.
FIG. 3 is a diagram showing a waveform of a signal obtained when addition of consecutive N sample values is sequentially and continuously performed on an incoming OFDM signal.
FIG. 4 is a block diagram showing one embodiment of the symbol clock reproducing device of the present invention.
5 is a diagram showing signal waveforms at the output side of each of an absolute value circuit and a band-pass filter in the symbol clock recovery device shown in FIG. 4;
FIG. 6 is a diagram showing one embodiment of an adding circuit in the symbol clock reproducing device shown in FIG. 4;
[Explanation of symbols]
Reference Signs List 1 symbol clock extraction circuit 2 PLL circuit 3 input terminal 4 addition circuit 5 absolute value circuit 6 band pass filter 7 voltage controlled oscillator 8 frequency divider 9 phase comparator 10 loop filter 11 flip-flop or 1 clock register 12 shift register 13 addition vessel

Claims (4)

Adding a sample value for one effective symbol period to a sample value obtained by sampling an OFDM signal having a guard interval period;
Extracting a symbol clock by passing the result of the addition through a band-pass filter;
Performing a phase comparison between both the reproduced symbol clock and the extracted symbol clock signal;
Controlling the oscillation output frequency of the voltage-controlled oscillator based on the result of the phase comparison, and extracting the reproduced symbol clock from the output side of the voltage-controlled oscillator. Method. 2. The symbol clock reproducing method according to claim 1, further comprising a step for obtaining an absolute value of a result of the addition between the adding step and a step of extracting the symbol clock by passing through the band-pass filter. A symbol clock regeneration method. Adding means for adding a sample value obtained by sampling an OFDM signal having a guard interval period over one effective symbol period;
A band-pass filter for extracting a symbol clock from an output of the adding means;
A voltage-controlled oscillator for extracting a reproduction symbol lock;
A phase comparison is made between the two signals of the reproduced symbol lock extracted by the voltage controlled oscillator and the symbol lock extracted from the band pass filter, and the oscillation output frequency of the voltage controlled oscillator is determined based on the result of the phase comparison. Control means for controlling the symbol clock. 4. The symbol clock reproducing device according to claim 3, wherein an absolute value circuit for obtaining an absolute value of an output signal of the adding circuit is interposed between the adding means and the band-pass filter. Symbol clock regeneration device.

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