JP3518754B2 - Orthogonal frequency division multiplex signal receiving apparatus and orthogonal frequency division multiplex signal receiving method - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to an OFDM (Orthogonal Frequency Division Multiplexing Orthogonal Frequency).
cy Division Multiplexing)
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal receiving apparatus, and particularly to a receiving apparatus and OF for receiving an OFDM signal suitable for digital mobile communication.
The present invention relates to a method of receiving a DM signal .

[0002]

2. Description of the Related Art A conventional OFDM signal transmitting apparatus will be described with reference to FIG. First, the digital information data signal is supplied to the serial-parallel conversion circuit 70 via the input terminal,
An error correction code is added as needed. The output signal of the circuit 70 is supplied to the IFFT circuit 71, and the output signal thereof is supplied to the D / A converter 73 via the guard interval circuit 72 for reducing multipath distortion. Here, it is converted into an analog signal and the next LPF 7
4 allows only the components in the required frequency band to pass. The output signal of the real, imaginary part of analog value is supplied to the quadrature modulator 75, and the OFDM signal is output.

This OFDM signal is frequency-converted into a frequency band to be transmitted by a frequency converter 76 and supplied to the next transmitting section 77, and is transmitted via a linear amplifier and a transmitting antenna constituting the same. To be done. The output signal of the intermediate frequency generation circuit 78 and the signal passed through the 90 ° shift circuit 78A are supplied to the quadrature modulator 75, respectively. The output signal of this circuit 78 is supplied to the clock signal generation circuit 79. The output clock signal of the circuit 79 is supplied to the serial / parallel conversion circuit 70, the IFFT circuit 71, the guard interval circuit 72, and the D / A converter 73, respectively.

Next, a conventional OFDM signal receiving apparatus will be described with reference to FIG. The receiving section 80 amplifies the signal from the transmitting section 77 obtained by the receiving antenna constituting the receiving section 80 by a high frequency amplifier, and through a frequency converter 81 for converting a carrier frequency to an intermediate frequency, an intermediate frequency amplifier circuit. 82 and then to the quadrature demodulator 83. The output signal of the circuit 82 is supplied to the intermediate frequency generation circuit 89 via the carrier detection circuit 90. The output signal of the circuit 89 and the signal passed through the 90 ° shift circuit 89A are supplied to the quadrature demodulator 83, respectively, and the output signals of the real and imaginary reparts are decoded. The output signal of the quadrature demodulator 83 is supplied to the A / D converter 85 via the LPF 84 to be converted into a digital signal, and the quadrature demodulator 8 is also supplied.
The output signal of No. 3 is also supplied to the synchronization signal generation circuit 91.

The output of the A / D converter 85 is passed through the next guard interval circuit 86 to the FFT / QAM decoding circuit 8
7 is supplied. The FFT / QAM decoding circuit 87 is based on the supplied synchronization signal of the synchronization signal generation circuit 91,
Performs a complex Fourier operation and outputs the real and imaginary parts of the input signal for each frequency (real part, imaginary part)
, The level of the quantized digital signal transmitted by the carrier for transmitting digital information is determined, and the digital information is decoded. The output signal of the FFT / QAM decoding circuit 87 is output via the parallel-serial conversion circuit 88. Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device are completely the same, only the modulation component is obtained, and there is no problem, but the intermediate frequency generating circuit, the local oscillator of the frequency converter (not shown). If the frequency stability is not high, or if there is a phase error between both output signals, it will affect the subsequent demodulation operation and the probability of occurrence of symbol error will increase.

[0006]

In a receiving device which receives a transmitted OFDM signal, it is very difficult to completely reproduce the phases of all the received carriers without a time axis fluctuation component. In addition, since the guard interval circuit is set on the transmitting side in order to reduce the multipath distortion, when receiving a transmission signal under such conditions, the effective symbol period part and the guard interval part are However, there is a problem that it is more difficult to reproduce the phase of the transmission signal in the completely same state as the transmission side. The present invention has been accomplished in view of the above problems, setting the OFDM specific carrier as a pilot signal for carrier, thereby, OFDM signals received you allow maintain synchronization relationship on the receiving side at a constant Communication device and O
An object is to provide a method for receiving an FDM signal .

[0007]

The present invention includes the following 1) to
It comprises the means described in 4) . 1) orthogonal frequency division multiplexing with pilot signal,
Multilevel QAM transmitted with guard interval added
An orthogonal frequency division multiplex signal receiving apparatus for receiving a modulated digital information signal, comprising the guard interval
It is present as a discontinuous waveform in the head and is multiplied by 4
Exist as a single-frequency signal, and
At higher frequencies that are held in phase with each other in the Vol section
And the pie transmitted as a signal with a constant amplitude.
Pilot signal demodulation means for phase demodulating the lot signal,
The pattern obtained by demodulating with the pilot signal demodulating means.
A signal that generates a drive signal based on the phase information of the Ylot signal.
Signal generation means and drive generated by the signal generation means
Driven by a signal for
FFT means for converting into a digital information signal,
Configuring Te orthogonal frequency division multiplex signal receiving apparatus according to claim. 2) Orthogonal frequency division multiplexing with pilot signal,
Multilevel QAM transmitted with guard interval added
Quadrature frequency component that receives the modulated digital information signal
A division multiplexing signal receiving apparatus, wherein the guard interval is
It is present as a discontinuous waveform in the head and is multiplied by 4
Exist as a single-frequency signal, and
At higher frequencies that are held in phase with each other in the Vol section
And the pie transmitted as a signal with a constant amplitude.
Pyro to demodulate lot signal to obtain demodulated pilot signal
Input signal demodulation means and the pilot signal demodulation means.
The frequency of the demodulated pilot signal obtained by
And a signal generating means for generating a signal
Using the clock signal generated by the
FFT means for converting a tonal signal into the digital information signal
And an orthogonal frequency component characterized by comprising:
Split multiplex signal receiver. 3) Orthogonal frequency division multiplexing with pilot signal,
Multilevel QAM transmitted with guard interval added
Quadrature frequency component that receives the modulated digital information signal
A method of receiving a division multiplex signal, comprising:
It is made to exist as a discontinuous waveform on the head and multiplied by 4
Exist as a single-frequency signal, and
At higher frequencies that are held in phase with each other in the Vol section
And the pie transmitted as a signal with a constant amplitude.
A first step of the phase demodulation lot signal, the first
The position of the pilot signal obtained by demodulating in the step
A second step of generating a driving signal based on the phase information,
By the drive signal generated in the second step
The multi-valued QAM modulation signal is driven and FFT-converted before
A third step of obtaining a digital information signal,
Orthogonal frequency division multiplexing signal reception characterized by
Method. 4) Orthogonal frequency division multiplexing with pilot signal,
Multilevel QAM transmitted with guard interval added
Quadrature frequency component that receives the modulated digital information signal
A method of receiving a division multiplex signal, comprising:
It is made to exist as a discontinuous waveform on the head and multiplied by 4
Exist as a single-frequency signal, and
At higher frequencies that are held in phase with each other in the Vol section
And the pie transmitted as a signal with a constant amplitude.
First to demodulate the lot signal to obtain a demodulated pilot signal
And the demodulation pattern obtained in the first step.
Generate a clock signal by frequency converting the ilot signal
Generated by the second step and the second step
The multi-valued QAM modulated signal by using the clock signal
A third step for T-transforming to obtain the digital information signal
Orthogonal frequency division multi-feature
Double signal reception method.

[0008]

DETAILED DESCRIPTION OF THE INVENTION Orthogonal Frequency Division Multiplexed Signals of the Invention
Suitable for receivers and orthogonal frequency division multiplexed signal reception methods
For example the OFDM signal transmitting and receiving device that is, with reference to FIGS. 1 to 4 of the accompanying will be described below. Figure 1
It is an embodiment of an OFDM signal transmitting apparatus applied to the present invention, and digital data transmitted here is compressed audio, video signal and the like. The OFDM signal transmission device arranges a large number of carriers orthogonally and transmits independent digital information in each carrier. Since the carriers are orthogonal to each other, the spectrum of adjacent carriers is the frequency position of the carrier. It becomes zero. IFFT circuit technology is used to create this orthogonal carrier.
An OFDM signal can be generated by executing an inverse DFT (discrete Fourier transform) using N complex numbers during a time interval T that is a window section in the IFFT, and each point of the inverse DFT corresponds to a modulation signal output. The N is also called an IFFT or FFT cycle, and details are published by Corona (issue date: 1993).
May 20, 2014) "Television Society, edited by Sei Imai
Signal Processing Engineering ", pp. 74-75.

The basic specifications of the apparatus according to this embodiment shown in FIGS. 1 and 2 are as follows. (a) Central carrier frequency ... 100 MHz (b) Number of carriers for transmission ... 248 waves (c) Modulation method ... 256QAM OFDM (d) Number of carriers used ... 257 waves (e) Transmission bandwidth ... 100 kHz, Bandwidth used ... 99 k
Hz (f) Transfer rate ... 750 kbps (g) Guard interval ... 60.6 μsec As shown in FIG. 1, for example, a digital information signal, which is an audio or video signal whose information signal is compressed by an encoding system such as MPEG, It is supplied to the serial-parallel conversion circuit 2 via the input terminal 1, and an error correction code is added as necessary. In this circuit 2, the input signal is arranged and output as a 256QAM modulation signal. This 256QA
M-modulation defines 16 levels in the amplitude direction and 16 levels in the angle direction for each carrier to transmit information.
This is a method of specifying and transmitting 6 × 16 256 values.
In this embodiment, of the 257 wave carriers, 248 waves are used to transmit information, and the remaining 9 waves are used for calibration and for transmitting other auxiliary signals.

The serial-parallel conversion circuit 2 is configured to output 248 bytes of digital data in one symbol period, that is, 248 sets of parallel data of 4 bits each in one symbol period. The output signal of the serial-parallel conversion circuit 2 is IF
It is supplied to the FT and pilot signal generation circuit 3. This circuit 3 operates according to the clock signal output from the clock signal generation circuit 10, and operates on a 248-wave carrier with 2
56QAM modulation is performed and each output signal is output as a real and imaginary component. Further, the IFFT / pilot signal generation circuit 3 uses an IFFT circuit having a cycle N, and discrete frequency point information corresponding to N discrete frequency points (sample points) in each effective symbol period set by this IFFT circuit. Is output from the IFFT / pilot signal generation circuit 3. The Nyquist frequency is 1 of the sample clock frequency in the IFFT having the cycle N.
Corresponding to / 2, and the pilot signal is transmitted as information that the Nyquist frequency has, that is, Nyquist frequency information. Since the Nyquist frequency is 1/2 of the sample clock frequency, it is possible to generate a sampling position signal (sample clock signal) for operating the FFT circuit by decoding and multiplying the Nyquist frequency information by the receiving device. . This Nyquist frequency information is the IFFT, real part input terminal R of the IFFT of the pilot signal generation circuit 3.
It is obtained by applying a constant level signal to the N / 2th frequency terminal in the (imaginary part input terminal I).

The output signals of these IFFT and pilot signal generation circuits 3 are supplied to a guard interval setting circuit 4 having a next RAM (random access memory) 4A. A guard interval gi of a predetermined section for reducing distortion is set as shown in FIG. The guard interval setting circuit 4 operates according to the clock signal output from the clock signal generation circuit 10, and sets the last part in the window section (effective symbol period ts) obtained from the IFFT and pilot signal generation circuit 3 to the window section. Place it just before. In order to set the guard interval, the guard interval setting circuit 4 reads the signal from the IFFT / pilot signal generation circuit 3 fetched in the RAM (4A) of the guard interval setting circuit 4 at the end of the effective symbol period ( (this period is set equal to gi.), the process returns to the beginning of the effective symbol period, the data of the effective symbol period ts is read, and the signal of the symbol period ta is transmitted. The Nyquist frequency information (pilot signal) is
It is transmitted even within the guard interval, but before and after IFF
In order to maintain continuity with the T-window section signal, the transmitted pilot signal has an integral wavelength within the guard interval.

Although the case where the Nyquist frequency is used as the pilot signal has been described, the Nyquist frequency does not necessarily have to be the Nyquist frequency as long as it has a simple integer ratio with the sample clock signal. You may use the thing. When considering an IFFT having a period M, a pilot signal is arranged at a position of 1/2 of the Nyquist frequency, that is, at the M / 4th frequency, and the carriers transmitted by OFDM are M / th to M / th in the IFFT.
The signals output up to the 4th and from the 3rd M / 4 to the Mth are used. Thus, the cycle M = 2N
The IFFT output signal equivalent to that when the IFFT having the cycle N is used can be obtained by using the IFFT. Therefore, it is possible to transmit a continuous pilot signal including the guard interval, and to decode this pilot signal,
A sample clock signal can be obtained by multiplying by 4. If the FFT window section signal information can be decoded separately, the FFT operation of the OFDM signal can be performed by combining with the sample clock signal obtained in this embodiment, and the OFD
It is possible to decode the M signal.

Next, the symbol period set by the guard interval setting circuit 4 will be described with reference to FIG. First, the used bandwidth is 99 kHz and the IFFT cycle is N = 25.
When it is 6, the effective symbol frequency fs and the effective symbol period ts are as follows, respectively. fs = 99,000 / 256 = 387 Hz ts = 1 / fs = 2586 μsec Further, when the guard interval period gi, which is a section for multipath distortion removal, is determined to be three wavelengths of the pilot signal,
gi is set as follows. gi = (1 / 49,500) × 3 = 60.6 μsec The symbol period ta and the symbol frequency fa at this time are as follows. ta = ts + gi = 2586 + 60.6 = 2646.6
μsec fa = 1 / ta = 378 Hz

The output signals of these guard interval setting circuits 4 are supplied to the D / A converter 5, where they are converted into analog signals, and only the necessary frequency band components are passed through by the next LPF 6. Real analog value,
The imaginary output signal is supplied to the next quadrature modulator 7,
Further, the modulator 7 is supplied with the output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the signal through the 90 ° shift circuit 8, respectively, and outputs an OFDM signal. This OF
The DM signal is frequency-converted into a frequency band to be transmitted by the frequency converter 11 and supplied to the next transmission unit 12, and is transmitted via the linear amplifier and the transmission antenna which configure the DM unit. The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. In the clock signal generating circuit 10, the common clock signal supplied from the intermediate frequency generating circuit 9 is used as the clock signal for driving the IFFT / pilot signal generating circuit 3 and the clock signal for driving the guard interval setting circuit 4. It is generated based on. Incidentally, 248
Since a set of 4 + 4 bits of parallel data is transmitted by a carrier of 248 waves, the transmission rate of this device is 248 bytes per symbol period. Therefore, the transmission rate per second is approximately 750 Kbits.

Next, the phase relationship between the guard interval, the symbol period and the synchronizing signal (pilot signal) will be described below with reference to the drawings. Here, the description relating to FIG. 7, FIG. 9, and FIG. 10 is given as a reference example of the present embodiment. In FIG. 7, which is shown as a reference example, a case will be described in which a synchronization signal (pilot signal) having the same phase is generated in each symbol period and a synchronization signal having an integer wavelength exists in the guard interval. (This is a first example of generating a continuous synchronizing signal without inverting the polarity.) The IFFT shown in FIG. 7 is synonymous with the effective symbol period and the IFFT period, and is the same as the end portion (right part) of the IFFT period. One cycle is used as it is as a signal of the guard interval G in the front (left part) of the IFFT period. In this example, the synchronization signal (pilot signal) having the same phase is generated for each IFFT period, and since the synchronization signal (pilot signal) is an integral wave in the guard interval section, the pilot signal is generated over a plurality of symbol periods. It is continuously generated. The case of FIG. 3 already described is the same as the case of FIG.
Synchronization signal (pilot signal) also in the guard interval section
Since there are integer waves, the pilot signal is continuously generated over a plurality of symbol periods.

In FIG. 8 shown as a reference example, a case will be described in which synchronization signals (pilot signals) of the same phase are generated in every other symbol period, and there is a synchronization signal of an odd multiple of a half wavelength in the guard interval. . (This is a second example of generating a continuous sync signal without inverting the polarity.) IFFT is synonymous with an effective symbol period and an IFFT period, and is 1/2 cycle of the end portion (right part) of the IFFT period. Is directly used as the signal of the guard interval in the front part (left part) of the IFFT period. In this example, a sync signal (pilot signal) having an opposite polarity is generated every IFFT period, and a sync signal having an odd multiple of a half wavelength also exists in the guard interval section, so that a plurality of symbol sections (symbol periods) are included. The pilot signal is continuously generated.

In FIG. 9 according to the embodiment of the present invention, the case where the synchronizing signal exists in the guard interval G in an odd multiple of half the wavelength will be described. (This is a first example of generating a synchronization signal with inverted polarity.) In this case, the polarity of the pilot signal is inverted at the start point of the guard interval, and the phase of the pilot signal in each symbol period is in phase. . That is, the terminal voltage corresponding to the frequency for generating the synchronizing signal of the IFFT for generating the frequency division multiplexed signal is constant for each symbol, and the synchronizing signal of the same phase is always generated. Therefore, when the guard interval is an odd multiple of half the wavelength, the sync signal becomes a continuous signal when the polarity of the sync signal is inverted every other symbol period on the receiving device side. In this case, the synchronization signal can be detected by using the PLL circuit in the phase synchronization circuit as shown in FIG.

Referring to FIG. 10 shown as a reference example, a case will be described in which the synchronizing signal (pilot signal) exists in the guard interval at an even multiple of a half wavelength. (This is a second example of generating a sync signal with the polarity reversed.) As shown in FIG. 10, when the sync signal (pilot signal) present in the guard interval is an integer wave (even multiple of half wavelength) Even if there is a sync signal, as in the case of FIG. 9, if the sync signal is inverted and output every other symbol period, a sync output in which the polarity is inverted for each symbol is obtained. Also in this case, the PLL circuit as shown in FIG. 11 can be used to detect the synchronization signal.

FIG. 11 shows a phase synchronization circuit for detecting a synchronization signal which is inverted every other symbol period. This phase synchronization circuit includes a phase comparator PD2 (112), Amp
This is a configuration in which a signal switcher 116 composed of an exclusive OR is inserted in the VCO output of the PLL circuit composed of the (amplifier 113), the LPF (114) and the VCO circuit (115). Phase comparator PD1 (111)
Constitute a synchronous detection circuit which receives the VCO output of the phase locked loop as an input. The frequency division division signal including the synchronization signal applied to the input terminal 110 is input to both the phase synchronization circuit and the synchronization detection circuit PD1 (111). This phase lock circuit includes a phase comparator PD2 (112), an amplifier (1
13), a LPF (114), a VCO (115), and a signal switching device (116). According to the output of the PD1 (111) which is synchronously detected, the signal switch (1
Although the output of the VCO circuit 115 of the PLL is inverted in 16), the synchronization signal whose polarity is inverted for each symbol is detected by the synchronous detection circuit and the phase comparator PD2 (112) forming the PLL. The polarity is inverted to V
Since the CO output is supplied, the lock operation is continuously performed even for the sync signal whose polarity is inverted.

FIG. 12 shows output waveforms of the terminals B and A in FIG. The output A is a sync signal output waveform, and the output B is a symbol sync signal which is transmitted with its polarity inverted every symbol period (symbol period). FIG. 13 shows another circuit example for FIG. 11, in which the signal switch 136 is the phase comparator PD2.
It is inserted between (132) and the amplifier 133. At the same time that the synchronization signal is inverted, it is detected and the polarity of the error signal is inverted, and the operation mode is the same as in FIG. In either case, even if the synchronization signal is inverted every other symbol period (symbol period), it is detected and PL
Since the characteristics of the L loop are inverted, the VCO continues to operate without being inverted. Therefore, the synchronization signal can be decoded normally.

Next, an embodiment of the OFDM signal receiving apparatus of the present invention will be described with reference to FIGS. Each component of the receiving device is composed of a circuit that operates in reverse to the transmitting device. The receiving unit 20 amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting the receiving unit 20 by a high frequency amplifier and supplies the amplified signal to the frequency converter 21. This output signal is supplied to the intermediate frequency amplifier circuit 22, and is output from the intermediate frequency amplifier circuit 22 as a reception signal of a predetermined level. The output signal of the intermediate frequency amplification circuit 22 is the quadrature demodulator 2
3 and a carrier detection (carrier extraction) circuit 29, respectively. The carrier detection circuit 29 includes the phase comparator (multiplier) 41, the LPF 42, and the VCO circuit 4 illustrated in FIG.
The intermediate frequency oscillating circuit 31 which has a PLL circuit composed of the 3/4 frequency dividing circuit 45 and is supplied with this output signal is a circuit for extracting the center carrier with a small phase error.

In this embodiment, carriers for transmitting information are arranged adjacent to each other at a symbol frequency of 378 Hz to form an OFDM signal. Since the information carrier adjacent to the center carrier is also 378 Hz apart, the center carrier needs to transmit information without being affected by the adjacent information carrier, and a circuit with high selectivity is used. In this embodiment, the central carrier is extracted using the PLL circuit, but the carrier frequency interval between adjacent carriers is approximately 1
Quartz crystal oscillator (V
CXO) is used as the voltage controlled oscillator (VCO) 43,
Activate the circuit. The LPF used in the PLL circuit also has a cutoff frequency sufficiently low with respect to 378 Hz. The output signal of the intermediate frequency generation circuit 31 and the signal passed through the 90 ° shift circuit 30 are multipliers 40,
The output signals of the real and imaginary reparts (real number part, imaginary number part) are supplied to the quadrature demodulators 23 each having 41, and are decoded. The output signals of the real part and the imaginary part are LPF2
4, the signal of the required frequency band transmitted as the OFDM signal information is passed, the input analog signal is sampled, and the output signal is supplied to the A / D converter (sampling circuit) 25. Convert to digital signal.

In the sample synchronizing signal generating circuit 32 applied to the present invention, the sample clock signal before frequency multiplication is generated by the PLL circuit which is in phase synchronization with the pilot signal, and the analog output of the quadrature demodulator 23 is provided in this circuit. Signal is supplied. The PLL is phase-synchronized with the pilot signal transmitted as a continuous signal in each symbol section including the guard interval period, and a demodulated pilot signal is obtained. In the transmitter, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and frequency multiplication is performed according to the frequency ratio to obtain the sample clock signal. The guard interval processing circuit 26 determines the symbol period ta from the transmitted signal.
The effective symbol period signal of the period ts can be obtained at an arbitrary timing among them, and the effective symbol period signal of which the influence of the multipath distortion is less is obtained, and the output signal is supplied to the FFT and QAM decoding circuit 27.

The symbol synchronization signal generation circuit 33 for detecting the symbol period detects the symbol period. The next FFT, QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal,
Performs a complex Fourier operation and outputs the real and imaginary parts of the input signal for each frequency (real part, imaginary part)
Ask for the level of. The real part of each frequency obtained in this way, the imaginary part signal level, and the real part of each carrier to be transmitted, comparing the demodulation output of the reference carrier for transmitting the reference value of the imaginary part, The level of the quantized digital signal transmitted by the carrier for transmitting digital information is obtained, and the digital information is decoded. This circuit 2
The output signal of No. 7 is output via the parallel-serial conversion circuit 28.

Next, together with FIG. 4, the carrier detection circuit 29,
The sample synchronization (sample clock) signal generation circuit 32 will be described below. This circuit is intended to extract a pilot signal transmitted at a constant level and generate an accurate sample synchronization (sample clock) signal based on this. First, the VCO circuit 43 forming the carrier detection circuit 29 is oscillated at a frequency of 42.8 MHz which is four times the intermediate frequency of 10.7 MHz. VCO circuit 4
The output signal of 3 is supplied to the multipliers 40 and 41 via the 1/4 frequency dividing circuits 44 and 45, respectively. One multiplier 41
Is supplied to the LPF 42, components below the symbol frequency are extracted, and the output signal controls the VCO circuit 43. A loop formed by the multiplier 41, the LPF 42, the VCO circuit 43, and the frequency dividing circuit 45 constitutes a PLL circuit.

The intermediate frequency amplified signals are applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit to obtain the output signals of the real number part and the imaginary number part. The sample synchronization signal generation circuit 32 is supplied with the real part output signal from the quadrature demodulator 23 and detects the Nyquist frequency component transmitted as a pilot signal. Variable division ratio circuit (V
The output signal of the VCO circuit 43 is supplied to the CO circuit) 50, and the division ratio is set to 1/426 to 1/438. The multiplier 52 in the sample synchronization signal generating circuit 32 is supplied with the output signal from the quadrature demodulator 23 and the signal from the VCO circuit via the 1/2 frequency dividing circuit 51, and operates as a phase comparator. To do.

As the output signal of the multiplier 52, only the error signal related to frequency control is passed by the LPF circuit 53. The delay circuit 54 and the adder circuit 55 are circuits for attenuating adjacent carrier components and have a symbol frequency of 387.
It has the characteristic of having a dip in Hz. VCO circuit
In the PLL circuit including the (division ratio variable circuit) 50, the multiplier 52, and the LPF 53, the VCO output signal synchronized with the continuous pilot signal included in the real part output signal of the quadrature demodulator 23 of the carrier extraction unit Oscillated, 99 kHz
Is output as the sample clock output signal of. In the above-described embodiment, the case where the IFFT having the cycle of 256 is used to generate the carrier of 257 waves has been described, but as another embodiment, an example of using the IFFT having the cycle of 512 will be described below. In the embodiment using the IFFT with a period of 512, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio relationship with the sample clock signal is used.

That is, when considering the IFFT of the period M, the pilot signal is arranged at the position of 1/2 of the Nyquist frequency, that is, the M / 4th frequency, and the carrier transmitted by OFDM is the first carrier in the IFFT. The signals output up to the M / 4th and from the 3rd M / 4th to the Mth are used. In this way, IF with cycle M = 2N
Even if the FT is used, an output signal of the IFFT equivalent to that when the IFFT of the cycle N is used can be obtained. Therefore, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding this pilot signal and multiplying it by four.

In the sample synchronizing signal generating circuit used at this time, the frequency of the pilot signal is the same as that of the embodiment in which the cycle N is 256, but the FF shown in FIG.
The sample clock frequency for driving the T / QAM decoding circuit 27 is double that when the cycle N is 256. Accordingly, the doubled 198 kHz sample clock signal is output. Therefore, this sample sync signal generation circuit
The frequency division ratio of the frequency division ratio variable circuit 50 is half that of the above embodiment.
13 to 1/219, and the point that the frequency dividing ratio of the 1/2 frequency dividing circuit 51 is 1/4, and the other configurations are the same as those in FIG. 4, and the description thereof will be omitted. .

[0030]

The effect obtained from the pilot signal of the present invention
OFDM signal receiving apparatus and OF for decoding based on phase information
In the DM signal receiving method , the head is used for the guard interval .
Is a discontinuous waveform and is multiplied by 4 to receive a single frequency signal.
Exist in the adjacent valid symbol intervals.
The high-order frequency pilot signals that are held in phase
Phase demodulation, and drive signal based on the phase information obtained by demodulation
Upon generating a pilot signal actually transmitted
It is multiplied by 4 to obtain a single frequency spectrum and
Pie the receiving side the width is present as a constant signal
Jitter-free drive signal based on the phase information of the lot signal
Generation can, makes it easy to set the same time relationship of the FFT circuit operating at the IFFT circuit and the receiver operating at the transmission side, F in the same time relationship as was performed IFFT operation
The FT operation can be performed, and more accurate information can be received. In addition, the demodulation pilot signal of the present invention is
Decoding using a clock signal obtained by number conversion O
In the FDM signal receiving device and the OFDM signal receiving method,
In the guard interval, as a discontinuous waveform on the head,
And multiplied by 4 and exist as a signal of a single frequency, and adjacent
Higher order that is kept in phase with each other in the effective symbol section
Generate clock signal based on frequency pilot signal
In this case, the pilot signal actually transmitted is multiplied by 4
A single frequency spectrum is obtained and the amplitude is constant.
Since it exists as a signal, it is a pilot signal on the receiving side.
Generates a clock signal without jitter based on the phase information of
From now on, the IFFT circuit that operates on the transmission side and the operation on the reception side
It is easy to set the time relationship of the FFT circuit to the same.
The same time-related FFT operation as the IFFT operation.
And can receive more accurate information.
That Do not. Furthermore, the pilot signal transmitted as an information signal has a discontinuous waveform at the head of the guard interval.
Since sent so as to present as, for the drive
A signal can generate a drive signal based on its discontinuous waveform information before the time-division synchronization signal comes in, and can decode a frequency-division multiplexed signal in a short time even when switching channels, etc. Have the effect of.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an OFDM signal transmission apparatus applied to the present invention.

FIG. 2 is a block diagram of an embodiment of an OFDM signal receiving apparatus of the present invention.

FIG. 3 is a diagram showing a relationship between a symbol period and a guard interval of an OFDM signal according to an embodiment of the present invention.

FIG. 4 is a block diagram of a carrier extraction unit and a sample synchronization signal generation unit of an OFDM signal receiving apparatus according to an embodiment of the present invention.

FIG. 5 is a block diagram of a conventional OFDM signal transmitter.

FIG. 6 is a block diagram of a conventional OFDM signal receiving apparatus.

FIG. 7 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 8 is a diagram showing a relationship between a synchronization signal and a symbol period according to the present invention.

FIG. 9 is a diagram showing a relationship between a sync signal and a symbol period according to an embodiment of the present invention .

FIG. 10 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 11 is a diagram showing an example of a phase synchronization circuit.

FIG. 12 is an output waveform diagram of the phase locked loop circuit.

FIG. 13 is a diagram showing another example of the phase synchronization circuit.

[Explanation of symbols]

2 serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 Guard interval setting circuit 4A RAM (random access memory) 5 D / A converter 6,24,42,53,114,134 LPF 7 Quadrature modulator 8,30 90 ° shift circuit 9,31 Intermediate frequency generation circuit 10 Clock signal generation circuit 11,21 Frequency converter 12 Transmitter 20 Receiver 23 Quadrature demodulator 25 A / D converter (sampling circuit) 26 Guard interval processing circuit 27 FFT, QAM decoding circuit 28 Parallel-serial conversion circuit 29 Carrier detection circuit 32 sample sync signal generator 33 Symbol synchronization signal generation circuit 40, 41, 52 Multiplier (phase comparator) 43, 50, 115, 135 VCO circuit 44,45 1/4 divider circuit 51 1/2 divider circuit 111, 112, 131, 132 Phase comparator (PD) 116, 136 signal switch

Continuation of the front page (56) Reference JP-A-56-134862 (JP, A) JP-A-56-158545 (JP, A) JP-A-60-52147 (JP, A) JP-A-6-141020 (JP , A) JP-A-7-273741 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 11/00

Claims (4)

(57) [Claims] 1. Orthogonal frequency division multiplexing with pilot signals
Multi-valued transmitted with a guard interval added
An orthogonal frequency division multiplex signal receiving apparatus for receiving a QAM-modulated digital information signal, wherein the guard interval is a discontinuous waveform at the head.
Exists and exists as a single frequency signal after being multiplied by 4
Exist and are in phase with each other in adjacent effective symbol intervals
A high-frequency signal that is held and has a constant amplitude
Pi for phase demodulating the pilot signal transmitted as
The lot signal demodulation means and the pilot signal demodulation means
Based on the phase information of the pilot signal obtained by demodulating more
Signal generating means for generating a drive signal, and the signal generating means
Driven by the drive signal generated by the stage,
Converting a value QAM modulated signal into the digital information signal
An orthogonal frequency division multiplex signal reception apparatus comprising: an FFT unit . 2. Orthogonal frequency division multiplexing with pilot signals
Multi-valued transmitted with a guard interval added
Quadrature circuit for receiving QAM-modulated digital information signal
A wave number division multiplex signal receiver, As a discontinuous waveform on the head during the guard interval
Exists and exists as a single frequency signal after being multiplied by 4
Exist and are in phase with each other in adjacent effective symbol intervals
A high-frequency signal that is held and has a constant amplitude
The pilot signal transmitted as
Pilot signal demodulation means for obtaining a lot signal,
Demodulation pilot signal obtained by lot signal demodulation means
Generating means for frequency-converting clock to generate clock signal
And a clock signal generated by the signal generating means
Using the multilevel QAM modulated signal as the digital information signal.
FFT means for converting into a number, Orthogonal frequency division multiplex characterized by comprising
Dual signal receiver. 3. Orthogonal frequency division multiplexing with pilot signals
Multi-valued transmitted with a guard interval added
Quadrature circuit for receiving QAM-modulated digital information signal
A method of receiving a wave number division multiplex signal, wherein a waveform that is discontinuous at the head of the guard interval
Exist and exist as a single frequency signal after being multiplied by 4
And keep them in phase with each other in adjacent effective symbol intervals.
It is a high-order frequency signal that has a constant amplitude.
First phase demodulates the pilot signal transmitted by
Step, and the pilot obtained by demodulation in the first step
A second step for generating a driving signal based on the phase information of the signal.
And the drive signal generated in the second step
The multi-valued QAM modulation signal is driven and FFT-converted before
A third step of obtaining a digital information signal, and an orthogonal frequency division multiplex signal,
How to receive. 4. Orthogonal frequency division multiplexing with pilot signals
Multi-valued transmitted with a guard interval added
Quadrature circuit for receiving QAM-modulated digital information signal
A method of receiving a wave number division multiplexed signal, As a discontinuous waveform on the head during the guard interval
Exist and exist as a single frequency signal after being multiplied by 4
And keep them in phase with each other in adjacent effective symbol intervals.
It is a high-order frequency signal that has a constant amplitude.
The pilot signal transmitted by
A first step of obtaining a set signal, Demodulated pilot signal obtained by the first step
Frequency converted to clock signal The second step to generate
And Use the clock signal generated by the second step
If the multilevel QAM modulated signal is FFT-converted,
The third step of obtaining a digital information signal, Orthogonal frequency division multiplexed signal characterized by having
How to receive.