JP3055541B2 - Orthogonal frequency division multiplexed signal transmitting / receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to OFDM (Orthogonal Frequency Division Multiplexing).
cy Division Multiplexing)
The present invention relates to a signal transmitting / receiving apparatus, and particularly to an OFDM signal transmitting / receiving apparatus suitable for digital mobile communication.

[0002]

2. Description of the Related Art A conventional OFDM signal transmitting apparatus will be described with reference to FIG. First, a digital information data signal is supplied to a serial / parallel conversion circuit 70 via an input terminal.
An error correction code is added as needed. The output signal of this circuit 70 is supplied to an IFFT circuit 71, and the output signal is supplied to a D / A converter 73 via a guard interval circuit 72 for reducing multipath distortion. Here, the signal is converted into an analog signal, and the next LPF 7
4 allows only the components of the required frequency band to pass. Output signals of the analog real and imaginary parts are supplied to a quadrature modulator 75, and an OFDM signal is output.

[0003] The OFDM signal is frequency-converted by a frequency converter 76 into a frequency band to be transmitted, and is supplied to the next transmitting unit 77, which transmits the signal through a linear amplifier and a transmitting antenna. Is done. The output signal of the intermediate frequency generation circuit 78 and the signal passed through the 90 ° shift circuit 78A are supplied to the quadrature modulator 75, respectively. The output signal of the circuit 78 is supplied to a clock signal generation circuit 79. The output clock signal of the circuit 79 is supplied to the serial-parallel conversion circuit 70, the IFFT circuit 71, the guard interval circuit 72, and the D / A converter 73, respectively.

Next, a conventional OFDM signal receiving apparatus will be described with reference to FIG. The receiving section 80 amplifies the signal from the transmitting section 77 obtained by the receiving antenna constituting the same by a high frequency amplifier, and converts the carrier frequency to an intermediate frequency via a frequency converter 81 through an intermediate frequency amplifying circuit. 82, and further supplied to a quadrature demodulator 83. The output signal of the circuit 82 is supplied to an intermediate frequency generation circuit 89 via a carrier detection circuit 90. The output signal of the circuit 89 and the signal passed through the 90 ° shift circuit 89A are respectively supplied to the quadrature demodulator 83, and the output signals of the real and imaginary parts are decoded. The output signal of the quadrature demodulator 83 is supplied to an A / D converter 85 via an LPF 84, and is converted into a digital signal.
The output signal of No. 3 is also supplied to the synchronization signal generation circuit 91.

The output of the A / D converter 85 is sent to the FFT / QAM decoding circuit 8 through the next guard interval circuit 86.
7 is supplied. This FFT / QAM decoding circuit 87 is based on the supplied synchronization signal of the synchronization signal generation circuit 91,
Performs complex Fourier operation, real and imaginary part signals (real part, imaginary part) for each frequency of input signal
Is obtained, the level of the quantized digital signal transmitted by the digital information transmission carrier is obtained, and the digital information is decoded. The output signal of the FFT / QAM decoding circuit 87 is output via the parallel / serial conversion circuit 88. Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device completely match, only the modulation component can be obtained, and there is no problem. ), If the frequency stability is not high, or if there is a phase error between the two output signals, the subsequent demodulation operation will be affected and the probability of occurrence of a symbol error will increase.

[0006]

In the OFDM signal transmitting / receiving apparatus, it is necessary to completely reproduce the phases of all the carrier waves on the receiving side without having a time-axis fluctuation component.
It is very difficult, and a guard interval circuit is set on the transmitting side to reduce multipath distortion. Therefore, when a transmission signal under such conditions is received, the effective symbol period portion and the guard interval portion Thus, there is a problem that it is more difficult to reproduce the phase of the transmission signal completely in the same state as the transmission side. The present invention has been made by paying attention to the above points, and an OFDM signal transmitting and receiving apparatus which sets a specific carrier of OFDM as a carrier for a pilot signal and thereby can keep a synchronization relationship of a receiving side constant. The purpose is to provide.

[0007]

SUMMARY OF THE INVENTION An OFDM signal transmitting / receiving apparatus according to the present invention is provided with a digital information signal supplied to a multi-level QAM.
It has an IFFT and pilot signal generation circuit for generating a modulation signal, a guard interval setting circuit configured to transmit a part of the modulation signal repeatedly for a predetermined time, and a clock signal generation circuit for driving both circuits. The IFFT and pilot signal generation circuit generates a pilot signal of a higher-order frequency whose phase is kept constant in a plurality of symbol periods (hereinafter, a symbol period is also referred to as a symbol period or a symbol period). A signal exists for a period corresponding to an odd multiple of an integer wavelength or a half wavelength in a guard interval section set by the guard interval setting circuit, and the pilot signal is continuous over a plurality of continuous symbol sections. Make or change the polarity of the continuous signal to the starting point of the guard interval So as to form an embodiment in which inverted, it is to achieve the above object so as to set the pilot signal of each symbol interval. The receiving device demodulates the pilot signal using a phase synchronization circuit, and generates a clock signal for decoding the orthogonal frequency division multiplexed signal based on the demodulated pilot signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an OFDM signal transmitting / receiving apparatus according to the present invention will be described below with reference to FIGS. FIG. 1 shows an embodiment of an OFDM signal transmitting apparatus according to the present invention. Digital data transmitted here is compressed audio and video signals. OF
The DM signal transmitting apparatus arranges a large number of carriers orthogonally and transmits independent digital information on each carrier. Since the carriers are orthogonal, the spectrum of the adjacent carrier is determined by the frequency position of the carrier. Becomes zero. IFFT circuit technology is used to create this orthogonal carrier. If an inverse DFT (Discrete Fourier Transform) using N complex numbers is performed during a time interval T which is a window section in the IFFT, an OFDM signal can be generated, and an inverse DF
Each point of T corresponds to a modulation signal output. N is an IFF
It is also called T or FFT cycle, and details are described in pages 74 to 75 of "Television Society, edited by Seiji Imai, Signal Processing Engineering" published by Corona Co., Ltd. (issued on May 20, 1993). I have.

The basic specifications of the apparatus of the present invention shown in FIGS. 1 and 2 are as follows. (a) Center carrier frequency: 100 MHz (b) Number of transmission carriers: 248 waves (c) Modulation method: 256 QAM OFDM (d) Number of carriers used: 257 waves (e) Transmission bandwidth: 100 kHz, used bandwidth: 99 k
Hz (f) Transfer rate: 750 kbps (g) Guard interval: 60.6 μsec As shown in FIG. 1, for example, a digital information signal that is an audio or video signal in which an information signal is compressed by an encoding method such as MPEG is used. The signal is supplied to the serial / parallel conversion circuit 2 via the input terminal 1, and an error correction code is added as necessary. In this circuit 2, input signals are arranged as 256QAM modulation signals and output. This 256QA
M-modulation defines 16 levels in the amplitude direction and 16 levels in the angle direction for each carrier to transmit information.
In this method, 256 values of 6 × 16 are specified and transmitted.
In this embodiment, information is transmitted using 248 waves out of 257 carriers, and the remaining 9 waves are used for calibration and for transmitting other auxiliary signals.

The serial-to-parallel conversion circuit 2 is configured to output 248 bytes of digital data during one symbol period, that is, 248 sets of 4-bit parallel data during one symbol period. The output signal of the serial-parallel conversion circuit 2 is IF
FT and pilot signal generation circuit 3. The circuit 3 operates by the clock signal output from the clock signal generation circuit 10 and operates for two hundred and fifty-eight carriers.
56QAM modulation is performed, and each output signal is output as a real and imaginary component. The IFFT / pilot signal generation circuit 3 uses an IFFT circuit having a period of N. Discrete frequency point information corresponding to N discrete frequency points (sample points) in each effective symbol period set by this IFFT circuit Are output from the IFFT and pilot signal generation circuit 3. The Nyquist frequency is 1 of the sample clock frequency in the IFFT of the period N.
/ 2, and the pilot signal is transmitted as information of the Nyquist frequency, that is, Nyquist frequency information. Since the Nyquist frequency is の of the sample clock frequency, the receiving device can decode and multiply the Nyquist frequency information to generate a sampling position signal (sample clock signal) for operating the FFT circuit. . This Nyquist frequency information is input to the real part input terminal R of the IFFT and the IFFT of the pilot signal generation circuit 3.
It is obtained by applying a signal of a constant level to the terminal of the N / 2th frequency in the (imaginary part input terminal I).

The output signals of the IFFT / pilot signal generation circuit 3 are supplied to a guard interval setting circuit 4 having a next RAM (random access memory) 4A, and the guard interval setting circuit 4 causes a multipath signal on a transmission path to be transmitted. A guard interval gi of a predetermined section for reducing distortion is set as shown in FIG. The guard interval setting circuit 4 is operated by the clock signal output from the clock signal generation circuit 10 and changes the last part in the window section (effective symbol period ts) obtained from the IFFT and pilot signal generation circuit 3 to the window section. Place it just before. In order to set the guard interval, the guard interval setting circuit 4 reads out the signal from the IFFT / pilot signal generation circuit 3 which has been taken into the RAM (4A) of the guard interval setting circuit 4 and reads the last period of the effective symbol period ( This period is set equal to gi.), and returns to the beginning of the effective symbol period, reads out the data of the effective symbol period ts, and sends out the signal of the symbol period ta. The Nyquist frequency information (pilot signal)
It is transmitted even within the guard interval, but before and after IFF
In order to maintain continuity with the T window section signal, the transmitted pilot signal is made to have an integer wavelength within the guard interval.

Although the case where the Nyquist frequency is used as the pilot signal has been described, the Nyquist frequency is not necessarily required as long as it has a simple integer ratio relationship with the sample clock signal. A thing may be used. When considering an IFFT having a period M, a pilot signal is arranged at a position １ ／ of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier to be transmitted by OFDM is M / Mth from the first in the IFFT.
The signals output up to the fourth and from the 3M / 4th to the Mth are used. Thus, the period M = 2N
, An IFFT output signal equivalent to the case of using an IFFT with a period of N can be obtained. Therefore, a continuous pilot signal including the guard interval can be transmitted, and the pilot signal is decoded.
By multiplying by 4, a sample clock signal can be obtained. If the window section signal information of the FFT can be separately decoded, the FFT operation of the OFDM signal can be performed in combination with the sample clock signal obtained in this embodiment, and the OFD signal can be obtained.
The decoding of the M signal can be performed.

Next, the symbol period set by the guard interval setting circuit 4 will be described with reference to FIG. First, the used bandwidth is 99 kHz, and the cycle of the IFFT is N = 25.
When the number is 6, the effective symbol frequency fs and the effective symbol period ts are respectively as follows. fs = 99,000 / 256 = 387 Hz ts = 1 / fs = 2586 μsec In addition, when the guard interval period gi, which is a multipath distortion removal section, is determined for three pilot signal wavelengths,
gi is set as follows. gi = (1 / 49,500) × 3 = 60.6 μsec At this time, the symbol period ta and the symbol frequency fa are respectively as follows. ta = ts + gi = 2586 + 60.6 = 2646.6
μsec fa = 1 / ta = 378 Hz

The output signal of the guard interval setting circuit 4 is supplied to a D / A converter 5 where it is converted into an analog signal, and only components in a required frequency band are passed by the next LPF 6. Real analog value,
The imaginary output signal is supplied to the next quadrature modulator 7,
The modulator 7 is supplied with the output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the signal passed through the 90 ° shift circuit 8, respectively, and outputs an OFDM signal. This OF
The DM signal is frequency-converted by a frequency converter 11 into a frequency band to be transmitted, supplied to the next transmission unit 12, and transmitted via a linear amplifier and a transmission antenna constituting the same. The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. In the clock signal generation circuit 10, a clock signal for driving the IFFT and pilot signal generation circuit 3 and a clock signal for driving the guard interval setting circuit 4 are a common clock signal supplied from the intermediate frequency generation circuit 9. Generated based on 248
Since the set of 4 + 4 bits of parallel data is transmitted by 248 carriers, the transmission rate of the present apparatus is 248 bytes per symbol period. Therefore, the transmission rate per second is approximately 750 Kbits.

Next, the phase relationship between the guard interval, the symbol period, and the synchronization signal (pilot signal) will be described with reference to the drawings. In FIG. 7, a synchronization signal (pilot signal) having the same phase is generated in each symbol period.
A case where a synchronization signal of an integer wavelength exists in the guard interval will be described. (This is a first example of generating a continuous synchronization signal without reversing the polarity.) IFFT shown in FIG. 7 is synonymous with the effective symbol period and the IFFT period, and is the end portion (right portion) of the IFFT period
1 cycle is just before the IFFT period (left part)
Of the guard interval G. In this example,
Synchronous signal (pilot signal) in phase for every IFFT period
Are generated, and the synchronization signal (pilot signal) has an integer wave in the guard interval, so that the pilot signal is continuously generated over a plurality of symbol periods. The case of FIG. 3 described above is the same as the case of FIG. 7, and since the synchronization signal (pilot signal) has an integer wave also in the guard interval section, the pilot signal is continuously generated over a plurality of symbol periods. I have.

Referring to FIG. 8, a case will be described in which a synchronization signal (pilot signal) having the same phase is generated in every other symbol period and a synchronization signal having an odd multiple of a half wavelength exists in the guard interval G. (This is a second example of generating a continuous synchronization signal without inverting the polarity.) IFFT is synonymous with the effective symbol period and the IFFT period, and is a half cycle of the end portion (right portion) of the IFFT period. Is used as it is as a signal of the guard interval before (left) of the IFFT period. In this example, the IFFT
A synchronization signal (pilot signal) of opposite polarity is generated for each period, and a synchronization signal having an odd multiple of half a wavelength also exists in the guard interval, so that the pilot signal is continuous over a plurality of symbol periods (symbol periods). Has been generated.

Referring to FIG. 9, a case will be described in which a synchronization signal exists at an odd multiple of a half wavelength in a guard interval.
(This is a first example of generating a synchronization signal with inverted polarity.) In this case, the polarity of the pilot signal is inverted at the start point of the guard interval G, and the phase of the pilot signal for each symbol period is the same. is there. That is, the terminal voltage corresponding to the frequency at which the IFFT synchronization signal for generating the frequency division multiplex signal is generated is fixed for each symbol,
Synchronous signals of the same phase are always generated. Therefore, when the guard interval is an odd multiple of half a wavelength, the synchronization signal becomes a continuous signal if the polarity of the synchronization signal is inverted every other symbol period on the receiving device side. In this case, it is possible to detect a synchronization signal using a PLL circuit in a phase synchronization circuit as shown in FIG.

Referring to FIG. 10, a case will be described in which a synchronization signal (pilot signal) exists at an even multiple of a half wavelength in the guard interval. (This is a second example of generating a synchronization signal with inverted polarity.) As shown in FIG.
Even when the synchronization signal (pilot signal) present in the guard interval is an integer wave (an even multiple of half a wavelength), the synchronization signal is inverted and output every other symbol period as in the case of FIG. A synchronous output in which the polarity is inverted for each symbol is obtained. Also in this case, the PLL shown in FIG.
The synchronization signal can be detected using a circuit.

FIG. 11 shows a phase synchronization circuit for detecting a synchronization signal inverted every other symbol period. This phase synchronization circuit includes a phase comparator PD2 (112), an Amp
(Amplifier 113), LPF (114), and VCO circuit (115) are provided with a signal switch 116 composed of an exclusive OR at the VCO output of a PLL circuit. Phase comparator PD1 (111)
Constitutes a synchronous detection circuit having the VCO output of the phase locked loop as an input. The frequency division multiplexed signal including the synchronization signal applied to the input terminal 110 is input to both the phase synchronization circuit and the synchronization detection circuit PD1 (111). This phase locked loop circuit includes a phase comparator PD2 (112) and an amplifier (1
13), a PLL composed of an LPF (114), a VCO (115), and a signal switch (116). The signal switch (1) is switched according to the output of the PD1 (111) that has been synchronously detected.
Although the configuration is such that the output of the VCO circuit 115 of the PLL is inverted in 16), the synchronization signal whose polarity is inverted for each symbol is detected by the synchronization detection circuit and the phase comparator PD2 (112) constituting the PLL Has the polarity inverted V
Since the CO output is supplied, the lock operation is continuously performed even for the synchronization signal whose polarity is inverted.

FIG. 12 shows output waveforms at terminals B and A in FIG. Output A is a synchronization signal output waveform, and output B is a symbol synchronization signal transmitted with its polarity inverted for each symbol period (symbol period). FIG. 13 shows another embodiment of FIG. 11, in which the signal switch 136 includes a phase comparator PD2.
(132) and the amplifier 133. The synchronous signal is detected at the same time as the synchronous signal is inverted, and the polarity of the error signal is inverted. The operation is performed in the same manner as in FIG. In any case, even if the synchronization signal is inverted every other symbol period (symbol period), it is detected and the PL is detected.
To invert the characteristics of the L loop, the VCO continues to operate continuously without being inverted. Therefore, decoding of the synchronization signal can be performed normally.

Next, an embodiment of the receiving apparatus of the present invention will be described with reference to FIGS. Each component of the receiving device is configured by a circuit that operates in the opposite direction to the transmitting device. The receiving unit 20 amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting the receiving unit 20 with a high-frequency amplifier and supplies the amplified signal to the frequency converter 21. This output signal is supplied to the intermediate frequency amplification circuit 22 and the intermediate frequency amplification circuit 2
2 is output as a reception signal of a predetermined level. The output signal of the intermediate frequency amplification circuit 22 is supplied to a quadrature demodulator 23 and a carrier detection (carrier extraction) circuit 29, respectively.
The carrier detection circuit 29 includes a phase comparator (multiplier) 41, an LPF 42, a VCO circuit 43, and a 1/4 illustrated in FIG.
An intermediate frequency oscillating circuit 31 to which the output signal is supplied has a PLL circuit composed of a frequency dividing circuit 45 and is a circuit for extracting a center carrier with a small phase error.

In this embodiment, carriers for transmitting information are arranged adjacent to each other at every 378 Hz which is a symbol frequency, and constitute an OFDM signal. The information carrier adjacent to the center carrier is only 378 Hz apart, and the center carrier needs to transmit information without being affected by the adjacent information carrier, and a highly selective circuit is used. In this embodiment, the center carrier is extracted using a PLL circuit.
/ 2, a crystal oscillator that oscillates at about ± 200 Hz (V
CXO) as a voltage controlled oscillator (VCO) 43,
Activate the circuit. The LPF used in the PLL circuit has a cutoff frequency sufficiently lower than 378 Hz. The output signal of the intermediate frequency generation circuit 31 and the signal passed through the 90 ° shift circuit 30 are used as a multiplier 40,
The output signals of the real part and the imaginary part (real part, imaginary part) are supplied to the quadrature demodulator 23 having 41, respectively. The real part and imaginary part output signals are LPF2
4, the signal of the required frequency band transmitted as OFDM signal information is passed, the input analog signal is sampled, and the output signal is supplied to an A / D converter (sampling circuit) 25. Convert to digital signal.

In the sample synchronizing signal generating circuit 32, a sample clock signal before frequency multiplication is generated by a PLL circuit which is phase-synchronized with a pilot signal, and an analog output signal of the quadrature demodulator 23 is supplied to this circuit.
The PLL is phase-synchronized with the pilot signal transmitted as a continuous signal in each symbol section including the guard interval period, and a demodulated pilot signal is obtained. In the transmitting device, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and performs frequency multiplication according to the frequency ratio to obtain a sample clock signal. The guard interval processing circuit 26 obtains an effective symbol period signal of the period ts at an arbitrary timing within the symbol period ta from the transmitted signal, and, from the transmitted signal, extracts an effective symbol period signal of which the influence of multipath distortion is smaller. Then, an output signal is supplied to the FFT / QAM decoding circuit 27.

The symbol synchronization signal generating circuit 33 for detecting the symbol period detects the symbol period. The next FFT and QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal,
Performs complex Fourier operation, real and imaginary part signals (real part, imaginary part) for each frequency of input signal
Find the level of The real part, imaginary part signal level of each frequency obtained in this way is compared with the real part of each carrier to be transmitted, and the demodulated output of the reference carrier for transmitting the reference value of the imaginary part, The level of the quantized digital signal transmitted by the digital information transmission carrier is determined, and the digital information is decoded. This circuit 2
7 is output via the parallel / serial conversion circuit 28.

Next, referring to FIG.
The sample synchronization (sample clock) signal generation circuit 32 will be described below. The purpose of this circuit is to extract a pilot signal transmitted at a constant level and generate an accurate sample synchronization (sample clock) signal based on the extracted pilot signal. First, the VCO circuit 43 constituting the carrier detection circuit 29 is oscillated at a frequency of 42.8 MHz, which is four times the intermediate frequency 10.7 MHz. VCO circuit 4
The output signal of No. 3 is supplied to multipliers 40 and 41 via 1/4 frequency dividing circuits 44 and 45, respectively. One multiplier 41
The output signal is supplied to the LPF 42, and a component equal to or lower than the symbol frequency is extracted. The output signal controls the VCO circuit 43. A loop including the multiplier 41, the LPF 42, the VCO circuit 43, and the frequency divider 45 forms a PLL circuit.

The intermediate frequency-amplified signal is applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit, and output signals of a real part and an imaginary part are obtained. The sample synchronization signal generation circuit 32 is supplied with the real part output signal from the quadrature demodulator 23 and detects a Nyquist frequency component transmitted as a pilot signal. Dividing ratio variable circuit (V
The output signal of the VCO circuit 43 is supplied to the (CO circuit) 50, and the frequency division ratio is set to 1/426 to 1/438. The multiplier 52 in the sample synchronization signal generating circuit 32 is supplied with the output signal from the quadrature demodulator 23 and the signal of the VCO circuit through the 1/2 frequency dividing circuit 51, and operates as a phase comparator. Do.

The output signal of the multiplier 52 is passed by the LPF circuit 53 so that only the error signal relating to the frequency control passes. The delay circuit 54 and the addition circuit 55 are circuits for attenuating adjacent carrier components, and have a symbol frequency of 387.
The characteristic has a dip in Hz. VCO circuit
(Division ratio variable circuit) In the PLL circuit including the multiplier 50, the multiplier 52, and the LPF 53, the VCO output signal synchronized with the continuous pilot signal included in the real part output signal of the quadrature demodulator 23 of the carrier extraction unit is output. Oscillated, 99kHz
As a sample clock output signal. In the above embodiment, the case where an IFFT having a period of 256 is used to generate carriers of 257 waves has been described. However, as another embodiment, an example in which an IFFT having a period of 512 is used will be described below. In the embodiment using the IFFT having a period of 512, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio relationship with the sample clock signal is used.

That is, when considering an IFFT with a period M, a pilot signal is arranged at a position of 1/2 of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier transmitted by OFDM is more than the first in the IFFT. Signals output as the M / 4th and the 3M / 4th to the Mth are used. Thus, the IF of the period M = 2N
Even if the FT is used, an output signal of the IFFT equivalent to the case of using the IFFT having the period N can be obtained. Therefore, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding this pilot signal and quadrupling it.

In the sample synchronizing signal generating circuit used at this time, the frequency of the pilot signal is the same as that of the embodiment in which the period N is 256, but the FF shown in FIG.
The sample clock frequency for driving the T, QAM decoding circuit 27 is twice as long as the period N is 256. Accordingly, a double 198 kHz sample clock signal is output. Therefore, this sample synchronization signal generation circuit
The frequency division ratio of the frequency division ratio variable circuit 50 is １ ／
13 to 1/219, and the fact that the dividing ratio of the 1/2 divider circuit 51 is 1/4, and the other configuration is the same as that of FIG. 4 and the description thereof is omitted. .

According to the OFDM signal transmitting / receiving apparatus of the present invention,
The guard interval period is determined by the same sample clock as that used to drive the IFFT and pilot signal generation circuit. The pilot signal used for transmitting the sample clock information is set so that the guard interval period is also continuous. The frequency spectrum of the pilot signal to be used is single. Therefore, a pilot signal having no jitter can be decoded in the receiving apparatus, and an IFFT circuit operating in the transmitting apparatus and an FFT circuit operating in the receiving apparatus.
It is easy to set the same time relationship in the circuit,
The FFT operation can be performed in a form close to the signal that has been subjected to the FFT operation, and more accurate information transmission becomes possible.
Further, the phase synchronization system according to the present invention can normally decode the synchronization information with respect to the synchronization signal information transmitted continuously or inverted every symbol period (symbol period). This means that even when the time-division synchronization signal is decoded with phase noise in mobile reception or the like, it can be received while correcting it, so that the clock synchronization signal and the symbol position signal can be decoded well. Furthermore, since symbol synchronization information is inserted into a pilot signal transmitted as an information signal, the synchronization signal can be decoded before a time-division synchronization signal arrives. This has the effect of decoding a frequency division multiplexed signal.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of an OFDM signal transmitting apparatus according to the present invention.

FIG. 2 is a block diagram of an embodiment of an OFDM signal receiving apparatus according to the present invention.

FIG. 3 is a diagram showing a relationship between a symbol period and a guard interval in the embodiment of the transmitting and receiving apparatus of the present invention.

FIG. 4 is a block diagram of a carrier extraction unit and a sample synchronization signal generation unit of the embodiment of the OFDM signal receiving apparatus according to the present invention.

FIG. 5 is a block diagram of a conventional OFDM signal transmission device.

FIG. 6 is a block diagram of a conventional OFDM signal receiving device.

FIG. 7 is a diagram illustrating a relationship between a synchronization signal and a symbol period.

FIG. 8 is a diagram illustrating a relationship between a synchronization signal and a symbol period.

FIG. 9 is a diagram illustrating a relationship between a synchronization signal and a symbol period.

FIG. 10 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 11 is a diagram illustrating an example of a phase synchronization circuit.

FIG. 12 is an output waveform diagram of a phase locked loop.

FIG. 13 is a diagram showing another example of the phase synchronization circuit.

[Explanation of symbols]

 Reference Signs List 2 serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 guard interval setting circuit 4A RAM (random access memory) 5 D / A demodulator 6, 24, 42, 53, 114, 134 LPF 7 quadrature modulator 8, 30 90 ° shift circuit 9, 31 Intermediate frequency generation circuit 10 Clock signal generation circuit 11, 21 Frequency converter 12 Transmitter 20 Receiver 23 Quadrature demodulator 25 A / D converter (sampling circuit) 26 Guard interval processing circuit 27 FFT, QAM decoding circuit 28 Parallel-serial conversion circuit 29 Carrier detection circuit 32 Sample synchronization signal generation circuit 33 Symbol synchronization signal generation circuit 40, 41, 52 Multipliers (phase comparators) 43, 50, 115, 135 VCO circuits 44, 45 1 / 4 frequency dividing circuit 51 1/2 frequency dividing circuit 111, 112, 131 , 132 Phase comparator (PD) 116, 136 Signal switch

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-11-215196 (JP, A) Patent 2874729 (JP, B2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 11/00

Claims (4)

(57) [Claims] 1. An IFFT and pilot signal generation circuit to which a digital information signal is supplied to generate a quadrature frequency division multiplexed multilevel QAM modulation signal including a pilot signal, and the multilevel QAM modulation in a predetermined section of an effective symbol section A guard interval setting circuit for generating a symbol interval by adding a guard interval for repeatedly transmitting a signal to the effective symbol interval, wherein the pilot signal is an integral multiple of one cycle in each of the guard intervals, Alternatively, the guard interval is set so as to exist for a period corresponding to an odd multiple of a 、 cycle and form a continuous signal in the one symbol section, and a pilot signal is set in a plurality of consecutive symbol sections. However, an aspect in which the polarity of the continuous signal is inverted for each start point of the guard interval In Suyo, orthogonal frequency division multiplex signal transmitting apparatus characterized by setting the pilot signal of each symbol interval. 2. A guard interval in which a pilot signal including synchronization information exists for a period corresponding to an integral multiple of one cycle or an odd multiple of a half cycle, and one effective symbol section following the guard interval are defined as one symbol. A receiving apparatus for an orthogonal frequency division multiplex signal transmitted as a section, comprising: a frequency converter for converting an orthogonal frequency division multiplex signal to be received into an intermediate frequency; and an orthogonal frequency division multiplex signal output from the frequency converter. A guard interval processing circuit for obtaining a signal of the effective symbol section to be decoded from a signal of the symbol section, and an FF for decoding an output of the guard interval processing circuit
A T / QAM decoding circuit; and a synchronizing signal generating circuit for generating a clock signal. The synchronizing signal generating circuit includes an input signal of a phase comparator constituting a phase synchronizing circuit for demodulating the received pilot signal. Alternatively, the pilot signal is demodulated by inverting the polarity of the output signal for each symbol section, and based on the demodulated pilot signal, a clock signal for driving the guard interval processing circuit and the FFT,
An orthogonal frequency division multiplexed signal receiving apparatus for generating a clock signal for driving a QAM decoding circuit. 3. An IFFT and pilot signal generating circuit for receiving a digital information signal and generating a quadrature frequency division multiplexed multilevel QAM modulated signal including a pilot signal, and the multilevel QAM modulation in a predetermined section of an effective symbol section. A guard interval setting circuit for adding a guard interval for repeatedly transmitting a signal to the effective symbol interval to generate a symbol interval, wherein the guard interval includes one of the pilot signals.
The pilot signal is set for a period corresponding to an odd number multiple of / 2 cycle, and the phase of the pilot signal changes every effective symbol period.
Continuous in a plurality of symbol periods
Or the pilot signal is its guard-in
Neighboring symbol periods that are inverted at each start point of the tarball
The orthogonal frequency division multiplexing signal transmitting apparatus, wherein a pilot signal of each of the symbol sections is set so as to form a discontinuous mode. 4. A pilot signal including synchronization information is divided by 1 /
An orthogonal frequency division multiplexed signal receiving apparatus, wherein one guard interval existing for a period corresponding to an integral multiple of two periods and one effective symbol interval following the guard interval are transmitted as one symbol interval. A frequency converter for converting a division multiplexed signal to an intermediate frequency, a guard interval processing circuit for obtaining a signal of the effective symbol section to be decoded from a signal of the symbol section of the orthogonal frequency division multiplexed signal output from the frequency converter, FF for decoding the output of the guard interval processing circuit
A T / QAM decoding circuit; and a synchronizing signal generating circuit for generating a clock signal. The synchronizing signal generating circuit includes an input signal of a phase comparator constituting a phase synchronizing circuit for demodulating the received pilot signal. Alternatively, the polarity of the output signal, the pilot signal is demodulated so that it is inverted according to the phase difference between the demodulated pilot signal and the received pilot signal, based on the demodulated pilot signal, An orthogonal frequency division multiplexed signal receiving apparatus for generating a clock signal for driving a guard interval processing circuit and a clock signal for driving the FFT / QAM decoding circuit.