JP3531828B2 - Orthogonal frequency division multiplexing signal transmission / reception system and orthogonal frequency division multiplexing signal transmission / reception method - Google Patents

Description

Detailed Description of the Invention 【Technical field】

The present invention relates to an OFDM (Orthogonal Frequency Division Multiplexing Orthogonal Frequency Div).
OFD relating to transmission and reception of an ion multiplexing signal, particularly suitable for digital mobile communication
The present invention relates to an M signal transmission / reception system and an OFDM signal transmission / reception method.

[Background technology]

A conventional OFDM signal transmitting apparatus will be described with reference to FIG.

First, a digital information data signal is supplied to a serial / parallel conversion circuit 70 via an input terminal, and an error correction code is added if necessary.

The output signal of the circuit 70 is supplied to an IFFT circuit 71, and the output signal is passed through a guard interval circuit 72 for reducing multipath distortion to D
It is supplied to the / A converter 73.

Here, the analog signal is converted into the next LP.
Only the necessary frequency band component is passed by F74.

The output signal of the real, imaginary part of analog value is supplied to the quadrature modulator 75, and the OFDM signal is output.

This OFDM signal is frequency-converted into a frequency band to be transmitted by the frequency converter 76 and supplied to the next transmitting section 77, which is transmitted via the linear amplifier and the transmitting antenna constituting the same. To be done.

The output signal of the intermediate frequency generating circuit 78 and 90
The signal passed through the shift circuit 78A is supplied to the quadrature modulator 75, respectively.

The output signal of the circuit 78 is supplied to the clock signal generating circuit 79.

The output clock signal of the circuit 79 is supplied to the serial / parallel conversion circuit 70, the IFFT circuit 71, the guard interval circuit 72, and the D / A converter 73, respectively.

Next, a conventional OFDM signal receiving apparatus will be described with reference to FIG.

The receiving unit 80 amplifies the signal from the transmitting unit 77 obtained by the receiving antenna constituting the receiving unit 80 by a high frequency amplifier and converts the carrier frequency into an intermediate frequency through an intermediate frequency converter 81. The signal is supplied to the frequency amplification circuit 82 and further to the quadrature demodulator 83.

The output signal of the circuit 82 is the carrier detection circuit 9
It is supplied to the intermediate frequency generating circuit 89 via 0.

Output signal of circuit 89 and 90 ° shift circuit 8
The signals via 9A are supplied to the quadrature demodulator 83, respectively, and the output signals of the real and imaginary reparts are decoded.

The output signal of the quadrature demodulator 83 is the LPF 84.
Is supplied to the A / D converter 85 via the, and converted into a digital signal, and the output signal of the quadrature demodulator 83 is also supplied to the synchronization signal generation circuit 91.

The output of the A / D converter 85 is passed through the next guard interval circuit 86 to the FFT / QAM decoding circuit 8
7 is supplied.

The FFT and QAM decoding circuit 87 performs a complex Fourier operation on the basis of the supplied synchronizing signal of the synchronizing signal generating circuit 91, and outputs a real part and an imaginary part signal (real part, Imaginary part) level, and the level of the quantized digital signal transmitted by the carrier for digital information transmission,
Digital information is decoded.

The output signal of the FFT / QAM decoding circuit 87 is output via the parallel-serial conversion circuit 88.

Here, if the intermediate frequency of the transmitting device and the intermediate frequency of the receiving device are completely the same, only the modulation component is obtained, and there is no problem, but the intermediate frequency generating circuit and the local oscillator of the frequency converter ( If the frequency stability is not high (not shown) or if there is a phase error between both output signals, it affects the subsequent demodulation operation and increases the probability of symbol error occurrence.

DISCLOSURE OF THE INVENTION [Problems to be Solved by the Invention]

In the OFDM signal transmitter / receiver, it is very difficult to completely reproduce the phases of all the carriers on the receiving side without having a fluctuation component on the time axis. Furthermore, in order to reduce multipath distortion. In addition, since the guard interval circuit is set on the transmission side, when receiving a transmission signal under such conditions, the phase of the transmission signal is completely the same as that on the transmission side in the effective symbol period part and the guard interval part. There is a problem that it is more difficult to reproduce in a state.

The present invention has been made by paying attention to the above points, and an OFDM specific carrier is set as a pilot signal carrier, whereby the synchronization relationship on the receiving side can be held constant. An object is to provide a signal transmission / reception system and an OFDM signal transmission / reception method.

[Means for Solving the Problems]

The present invention comprises means described in the following item 1) or 2).

That is, 1) an IFFT and pilot signal generating circuit which is supplied with a digital information signal and generates a multilevel QAM modulated signal;
A guard interval setting circuit configured to repeatedly transmit a part of the modulated signal for a predetermined time, and a clock signal generation circuit for generating a clock signal for driving both circuits, and the IFFT and pilot signal generation The circuit keeps the phases at the start points of the plurality of effective symbol sections in opposite phases in the adjacent effective symbol sections, keeps the amplitude constant, and has a higher-order frequency having an integer frequency ratio relationship with the clock signal. A transmission device configured to allow a pilot signal to exist as a signal of only a real part in a guard interval section set by the guard interval setting circuit and continuously transmit it over a plurality of the symbol sections; Clock that has a frequency ratio of a predetermined integer to the pilot signal sent from the device Signal generating means for generating a signal, a signal generating means for generating a driving signal by counting the number of clocks of the clock signal generated by the signal generating means, and a driving signal generated by the signal generating means An orthogonal frequency division multiplex signal transmission / reception system comprising a receiving device configured to include the FFT means for converting the multilevel QAM modulated signal into the digital information signal. 2) Multi-valued QA including the pilot signal by IFFT of the supplied digital information signal based on a predetermined clock signal
M-modulated signal is generated, a part of the multi-level QAM modulated signal is repeated for a predetermined time to generate a guard interval signal,
The generated guard interval signal is converted into the multilevel QA.
A method of transmitting and receiving an orthogonal frequency division multiplex signal, which is transmitted before an M-modulated signal and receives the transmitted signal, wherein the phases at the start points of a plurality of effective symbol sections are adjacent to each other in an effective symbol section. A first step of generating a pilot signal of a high-order frequency which is held in a reverse phase and whose amplitude is held constant, and which has an integer frequency ratio relationship with the clock signal, and generated in the first step. A second step of continuously transmitting a pilot signal over a plurality of the symbol intervals by allowing the pilot signal to exist as a signal of only a real part in a preset guard interval interval, and the second step. A third step of generating a clock signal having a frequency ratio of a predetermined integer with the transmitted pilot signal;
In the fourth step of counting the number of clocks of the clock signal obtained in step 4 to generate a driving signal, and driving the multi-valued QAM modulated signal by the driving signal generated in the fourth step. A fifth step of performing FFT conversion to obtain the digital information signal, and a method of transmitting and receiving an orthogonal frequency division multiplexed signal, the method comprising:

【The invention's effect】

In the OFDM signal transmission / reception system and the OFDM signal transmission / reception method of the present invention, the high-order frequencies of the high-order frequencies which are present in the guard interval from the transmission side as signals of only the real part and which are held in opposite phases in adjacent effective symbol sections When a pilot signal is transmitted, the receiving side generates a clock signal based on the received pilot signal, and when the generated clock signal is counted to generate a driving signal, the pilot signal actually transmitted is the guard interval. Since it exists as a signal of only the real part including the section and has a constant amplitude, it is possible to generate a driving signal without jitter, and an IFFT circuit operating on the transmitting side and an FFT circuit operating on the receiving side. It becomes easy to set the same time relationship of the FFT operation and the FFT operation of the same time relationship as when the IFFT operation is performed. Can be carried out, it is possible to send and receive more accurate information.

Further, the pilot signal transmitted as the information signal is inserted with the symbol synchronization information so that the pilot signals are held in opposite phases at the start points of a plurality of adjacent effective symbol sections, and the pilot signal is transmitted. Based on the polarity information of the signal, it is possible to generate a driving signal before the time-division synchronization signal comes in, and it is possible to decode the frequency-division multiplexed signal in a short time even when switching channels. Have

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of an OFDM signal transmitting / receiving apparatus adapted to the OFDM signal transmitting / receiving system and the OFDM signal transmitting / receiving method of the present invention will be described below with reference to the accompanying FIGS. 1 to 4.

FIG. 1 shows an embodiment of an OFDM signal transmitting apparatus, and the digital data transmitted here is compressed audio, video signals and the like.

The OFDM signal transmitting apparatus arranges a large number of carriers orthogonally and transmits independent digital information in each carrier. Since the carriers are orthogonal to each other, the spectrum of the adjacent carriers is the same as that of the carrier. It becomes zero at the frequency position.

IFFT to make this orthogonal carrier
Circuit technology is used. An OFDM signal can be generated by performing an inverse DFT (discrete Fourier transform) with N complex numbers during a time interval T that is a window section in IFFT.
Each point of the inverse DFT corresponds to the modulation signal output. The N is
It is also called the IFFT or FFT cycle. For details, see 74th to 75th "Signal Processing Engineering" by Sei Imai, Television Society, published by Corona Publishing (published on May 20, 1993).
It is explained in the page etc.

The basic specifications of the apparatus according to this embodiment shown in FIGS. 1 and 2 are as follows. (a) Central carrier frequency ... 100 MHz (b) Number of carriers for transmission ... 248 waves (c) Modulation method ... 256QAM OFDM (d) Number of carriers used ... 257 waves (e) Transmission bandwidth ... 100 kHz, Bandwidth used ... 99 k
Hz (f) Transfer rate ... 750 kbps (g) Guard interval ... 60.6 μsec As shown in FIG. 1, for example, a digital information signal, which is an audio or video signal whose information signal is compressed by an encoding system such as MPEG, It is supplied to the serial-parallel conversion circuit 2 via the input terminal 1, and an error correction code is added as necessary.

In this circuit 2, the input signal is 256QAM.
It is arranged as a modulation signal and output.

This 256QAM modulation is a system in which 16 levels in the amplitude direction and 16 levels in the angle direction are defined for each carrier to which information is transmitted, and 16 × 16 256 values are specified and transmitted. .

In this embodiment, of the 257 wave carriers,
248 waves are used to transmit information, and the remaining 9
The waves are used for calibration and for transmitting other auxiliary signals.

The serial-parallel conversion circuit 2 is configured to output 248 bytes of digital data during one symbol period, that is, 248 sets of parallel data of 4 bits each during one symbol period.

The output signal of the serial-parallel conversion circuit 2 is IFF.
The T signal is supplied to the pilot signal generation circuit 3. This circuit 3 operates according to the clock signal output from the clock signal generation circuit 10 and operates for 25 carriers for 248 waves.
6QAM modulation is performed, and each output signal is output as a real and imaginary component.

The IFFT / pilot signal generation circuit 3 uses an IFFT circuit having a cycle N.
N in each effective symbol period set by the FFT circuit
Discrete frequency point information corresponding to the discrete frequency points (sample points) is output from the IFFT and pilot signal generation circuit 3.

The Nyquist frequency is the IFF of the period N.
Equivalent to half the sample clock frequency at T,
The pilot signal is transmitted as information possessed by the Nyquist frequency, that is, Nyquist frequency information. Since the Nyquist frequency is 1/2 of the sample clock frequency, the receiver decodes the Nyquist frequency information.
A sampling position signal (sample clock signal) for operating the FFT circuit can be generated by multiplication.

This Nyquist frequency information is the IFFT,
It is obtained by applying a signal of a constant level to the terminal of the N / 2nd frequency in the real part input terminal R (imaginary part input terminal I) of the IFFT of the pilot signal generation circuit 3.

The output signals of these IFFT and pilot signal generation circuits 3 are supplied to a guard interval setting circuit 4 having a next RAM (random access memory) 4A, and this guard interval setting circuit 4 causes multipath in the transmission path. A guard interval gi of a predetermined section for reducing distortion is set as shown in FIG.

The guard interval setting circuit 4 operates by the clock signal output from the clock signal generation circuit 10, and the last part in the window section (effective symbol period ts) obtained from the IFFT and pilot signal generation circuit 3 is
Place it just before the window section.

In order to set the guard interval,
The guard interval setting circuit 4 has R
When the signal from the IFFT / pilot signal generation circuit 3 fetched in AM (4A) is read out, the signal is read from the last period of the effective symbol period (this period is set equal to gi) and the effective symbol period is changed. Returning to the beginning, the data in the effective symbol period ts is read and the signal in the symbol period ta is transmitted.

Although the Nyquist frequency information (pilot signal) is transmitted within the guard interval, the pilot signal transmitted within the guard interval has an integral wavelength in order to maintain continuity with the preceding and following IFFT window interval signals. Let it exist.

Although the Nyquist frequency is used as the pilot signal, the Nyquist frequency does not have to be the Nyquist frequency as long as it has a simple integer ratio with the sample clock signal. You may use the thing.

When considering an IFFT having a period M, a pilot signal is arranged at a position of 1/2 of the Nyquist frequency, that is, at the M / 4th frequency, and the carrier to be transmitted by OFDM is from the 1st to the Mth in the IFFT. / Until the 4th
Also, the signals output from the 3rd M / 4th to the Mth are used.

As described above, even when the IFFT having the cycle M = 2N is used, the output signal of the IFFT equivalent to that when the IFFT having the cycle N is used can be obtained. Therefore, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding this pilot signal and multiplying it by four.

If the FFT window interval signal information can be decoded separately, the FFT operation of the OFDM signal can be performed by combining with the sample clock signal obtained in this embodiment, and the OFD
It is possible to decode the M signal.

Next, the symbol period set by the guard interval setting circuit 4 will be described with reference to FIG.

First, when the used bandwidth is 99 kHz and the IFFT cycle is N = 256, the effective symbol frequency fs
And the effective symbol period ts are as follows, respectively.

Fs = 99,000 / 256 = 387 Hz ts = 1 / fs = 2586 μsec Further, when the guard interval period gi, which is a multipath distortion elimination section, is determined to be three wavelengths of the pilot signal,
gi is set as follows.

Gi = (1 / 49,500) × 3 = 60.6 μsec The symbol period ta and the symbol frequency fa at this time are as follows.

Ta = ts + gi = 2586 + 60.6 = 2646.6
μsec fa = 1 / ta = 378 Hz The output signals of these guard interval setting circuits 4 are
It is supplied to the D / A converter 5, where it is converted into an analog signal, and only the necessary frequency band component is passed through by the next LPF 6.

The real, imaginary output signal of the analog value is supplied to the next quadrature modulator 7, and this modulator 7 is also supplied.
The output signal of the 10.7 MHz intermediate frequency generation circuit 9 and the signal passed through the 90 ° shift circuit 8 are respectively supplied to
The FDM signal is output.

This OFDM signal is frequency-converted into a frequency band to be transmitted by the frequency converter 11 and supplied to the next transmitting section 12, and is transmitted through the linear amplifier and the transmitting antenna which compose this. It

The output signal of the 10.7 MHz intermediate frequency generation circuit 9 is also supplied to the clock signal generation circuit 10. In the clock signal generation circuit 10, the I
A clock signal for driving the FFT / pilot signal generation circuit 3 and a clock signal for driving the guard interval setting circuit 4 are generated based on the common clock signal supplied from the intermediate frequency generation circuit 9.

Since 248 sets of 4 + 4 bit parallel data are transmitted by the carrier of 248 waves, the transmission rate of this device is 248 bytes per symbol period.
Therefore, the transmission rate per second is approximately 750 Kbits.

Next, the phase relationship between the guard interval, the symbol period and the synchronizing signal (pilot signal) will be described below with reference to the drawings.

In FIG. 7 shown as a reference example, a case will be described in which the synchronization signal (pilot signal) of the same phase is generated in each symbol period and the synchronization signal of the integer wavelength exists in the guard interval. (This is a first example of generating a continuous synchronizing signal without inverting the polarity.) The IFFT shown in FIG. 7 is synonymous with the effective symbol period and the IFFT period, and is the same as the end portion (right part) of the IFFT period. One cycle is used as it is as a signal of the guard interval G in the front (left part) of the IFFT period.

In this example, the synchronization signal (pilot signal) having the same phase is generated for each IFFT period, and since the synchronization signal (pilot signal) is an integer wave in the guard interval section, it extends over a plurality of symbol periods. The pilot signal is continuously generated.

The case of FIG. 3 already described is the same as the case of FIG. 7, and since the synchronization signal (pilot signal) is an integer wave in the guard interval section, the pilot signal is continuously generated over a plurality of symbol periods. Has been made.

In FIG. 8 according to the embodiment of the present invention, a case where a synchronizing signal (pilot signal) having the same phase is generated in every other symbol period, and a synchronizing signal of an odd multiple of a half wavelength exists in the guard interval. explain. (This is a second example of generating a continuous sync signal without inverting the polarity.) IFFT is synonymous with the effective symbol period and the IFFT period, and is the end portion (right part) of the IFFT period.
1/2 cycle is directly used as the signal of the guard interval in the front part (left part) of the IFFT period.

In this example, a reverse polarity synchronization signal (pilot signal) is generated for each IFFT period, and a guard interval section also has a synchronization signal of an odd multiple of a half wavelength. Therefore, a plurality of symbol sections (symbols) The pilot signal is continuously generated over a period of time).

In FIG. 9 shown as a reference example, a case where the synchronization signal exists in the guard interval G in an odd multiple of half the wavelength will be described. (This is a first example of generating a synchronization signal with inverted polarity.) In this case, the polarity of the pilot signal is inverted at the start point of the guard interval, and the phase of the pilot signal in each symbol period is in phase. .

That is, I for generating the frequency division multiplexed signal
The terminal voltage corresponding to the frequency for generating the FFT synchronizing signal is constant for each symbol, and the synchronizing signals of the same phase are always generated.

Therefore, when the guard interval is an odd multiple of a half wavelength, the polarity of the synchronization signal is inverted every other symbol period on the receiving device side, so that the synchronization signal becomes a continuous signal.

In this case, the synchronization signal can be detected by using the PLL circuit in the phase synchronization circuit as shown in FIG.

In FIG. 10 according to the embodiment of the present invention, the case where the synchronization signal (pilot signal) exists in the guard interval at an even multiple of half the wavelength will be described. (This is a second example of generating a sync signal with the polarity reversed.)
As shown in FIG. 9, even when the sync signal (pilot signal) existing in the guard interval is an integer wave (even multiple of half wavelength), the sync signal is placed every other symbol period as in the case of FIG. When inverted and output, a synchronous output whose polarity is inverted for each symbol is obtained.

Also in this case, the synchronization signal can be detected by using the PLL circuit as shown in FIG.

FIG. 11 shows a phase synchronization circuit for detecting a synchronization signal which is inverted every other symbol period.

This phase locked loop circuit comprises a phase comparator PD2.
(112), Amp (amplifier 113), LPF (11
4), the signal switch 116 configured by an exclusive OR is inserted in the VCO output of the PLL circuit configured by the VCO circuit (115).

The phase comparator PD1 (111) constitutes a synchronous detection circuit which receives the VCO output of the phase synchronization circuit as an input. The frequency division division signal including the synchronization signal applied to the input terminal 110 is the phase synchronization circuit and the synchronization detection circuit PD.
It is input to both 1 (111). This phase locked loop circuit includes a phase comparator PD2 (112), an amplifier (113), and an LP.
F (114), VCO (115), signal switch (11
It is composed of a PLL configured in 6).

The VCO circuit 11 of the PLL is driven by the signal switch (116) according to the output of the PD1 (111) which is synchronously detected.
5, the sync signal whose polarity is inverted for each symbol is detected by the sync detection circuit, and the phase comparator PD2 (112) constituting the PLL is formed.
Since the VCO output whose polarity is inverted is supplied to, the lock operation is continuously performed even for the synchronization signal whose polarity is inverted.

FIG. 12 shows output waveforms of the terminals B and A in FIG. The output A is a sync signal output waveform, and the output B is a symbol sync signal which is transmitted with its polarity inverted every symbol period (symbol period).

FIG. 13 shows another example of the circuit shown in FIG. 11. The signal switch 136 is inserted between the phase comparator PD2 (132) and the amplifier 133.

At the same time that the sync signal is inverted, it is detected and the polarity of the error signal is inverted, and the operation mode is the same as in FIG. In either case, even if the synchronization signal is inverted every other symbol period (symbol period), it is detected and the characteristics of the loop of the PLL are inverted.
CO continues continuous operation without being inverted. Therefore, the synchronization signal can be decoded normally.

Next, an embodiment of an OFDM signal receiving apparatus for receiving the signal transmitted by this transmitting apparatus will be described with reference to FIG.
4 and FIG.

Each component of the receiving device is composed of a circuit that operates in the opposite manner to the transmitting device. The receiving unit 20 amplifies the signal from the transmitting unit 12 obtained by the receiving antenna constituting the receiving unit 20 by a high frequency amplifier, and a frequency converter 21
Supply to.

This output signal is supplied to the intermediate frequency amplifier circuit 22 and is output from the intermediate frequency amplifier circuit 22 as a reception signal of a predetermined level.

The output signal of the intermediate frequency amplification circuit 22 is supplied to the quadrature demodulator 23 and the carrier detection (carrier extraction) circuit 29, respectively.

The carrier detection circuit 29 includes the phase comparator (multiplier) 41, the LPF 42, and the VCO circuit 4 illustrated in FIG.
The intermediate frequency oscillating circuit 31 which has a PLL circuit composed of the 3/4 frequency dividing circuit 45 and is supplied with this output signal is a circuit for extracting the center carrier with a small phase error.

In this embodiment, carriers for transmitting information are arranged adjacent to each other at a symbol frequency of 378 Hz to form an OFDM signal. Since the information carrier adjacent to the center carrier is also 378 Hz apart, the center carrier needs to transmit information without being affected by the adjacent information carrier, and a circuit with high selectivity is used.

In this embodiment, the central carrier is extracted by using the PLL circuit, but a crystal controlled oscillator (VCXO) oscillating at about ± 200 Hz, which is approximately 1/2 of the interval between adjacent carrier frequencies, is used as a voltage controlled oscillator ( VCO) 43 to operate the circuit. L used in the PLL circuit
The PF also has a cutoff frequency sufficiently low with respect to 378 Hz.

The output signal of the intermediate frequency generating circuit 31 and the signal passed through the 90 ° shift circuit 30 are multipliers 40 and 4.
1 is supplied to the quadrature demodulator 23 having the
The output signal of the imaginary part (real part, imaginary part) is decoded.

The output signals of the real and imaginary parts are LPF2
4, the signal of the required frequency band transmitted as the OFDM signal information is passed, the input analog signal is sampled, and the output signal is supplied to the A / D converter (sampling circuit) 25. Convert to digital signal.

In the sample synchronizing signal generation circuit 32, the sample clock signal before frequency multiplication is generated by the PLL circuit which is in phase with the pilot signal, and the analog output signal of the quadrature demodulator 23 is supplied to this circuit.
The PLL is phase-synchronized with the pilot signal transmitted as a continuous signal in each symbol section including the guard interval period, and a demodulated pilot signal is obtained.

In the transmitter, the pilot signal is set to a predetermined integer ratio with respect to the sample clock frequency, and frequency multiplication is performed according to the frequency ratio.
Obtain the sample clock signal.

The guard interval processing circuit 26 can obtain the effective symbol period signal of the period ts at an arbitrary timing within the symbol period ta from the transmitted signal, and the effective symbol period signal having less influence of the multipath distortion among them can be obtained. The period signal is obtained and the output signal is supplied to the FFT and QAM decoding circuit 27.

The symbol synchronization signal generating circuit 33 for detecting the symbol period detects the symbol period.

The next FFT and QAM decoding circuit 27 is supplied with the obtained clock synchronization signal and symbol synchronization signal, performs a complex Fourier operation, and outputs a real part and an imaginary part signal ( Seeking the level of real part, imaginary part).

The thus obtained real and imaginary part signal levels for each frequency and the demodulated output of the reference carrier for transmitting the reference values of the real and imaginary parts of each carrier to be transmitted are shown. By comparison, the level of the quantized digital signal transmitted by the carrier for transmitting digital information is obtained, and the digital information is decoded.

The output signal of the circuit 27 is output through the parallel-serial conversion circuit 28.

Next, together with FIG. 4, the carrier detection circuit 29,
The sample synchronization (sample clock) signal generation circuit 32 will be described below.

The purpose of this circuit is to extract a pilot signal transmitted at a constant level and generate an accurate sample synchronization (sample clock) signal based on the extracted pilot signal.

First, V which constitutes the carrier detection circuit 29.
The CO circuit 43 is oscillated at a frequency of 42.8 MHz which is four times the intermediate frequency of 10.7 MHz. VCO circuit 43
The output signals of 1 to 4 are supplied to the multipliers 40 and 41 via the 1/4 frequency dividing circuits 44 and 45, respectively.

The output signal from one multiplier 41 is the LPF.
42, the components below the symbol frequency are extracted, and the output signal controls the VCO circuit 43.

Multiplier 41, LPF 42, VCO circuit 4
3. The loop formed by the frequency dividing circuit 45 constitutes a PLL circuit.

The intermediate frequency amplified signals are applied to the input terminals of the multipliers 40 and 41, and orthogonal decoding is performed by this circuit to obtain real and imaginary part output signals.

The sample synchronization signal generation circuit 32 is supplied with the real part output signal from the quadrature demodulator 23 and detects the Nyquist frequency component transmitted as the pilot signal.

The frequency division ratio variable circuit (VCO circuit) 50 has
The output signal of the VCO circuit 43 is supplied, and the division ratio is 1/4.
It is configured to be set from 26 to 1/438.
The multiplier 52 in the sample sync signal generation circuit 32 is
The output signal from the quadrature demodulator 23 and the signal from the VCO circuit via the 1/2 frequency divider circuit 51 are supplied to operate as a phase comparator.

As the output signal of the multiplier 52, only the error signal related to frequency control is passed by the LPF circuit 53. The delay circuit 54 and the adder circuit 55 are circuits for attenuating adjacent carrier components and have a symbol frequency of 387.
It has the characteristic of having a dip in Hz.

The PLL circuit composed of the VCO circuit (variable division ratio circuit) 50, the multiplier 52, and the LPF 53 is synchronized with the continuous pilot signal included in the real part output signal of the quadrature demodulator 23 of the carrier extraction unit. The VCO output signal is oscillated and output as a 99 kHz sample clock output signal.

In the above-mentioned embodiment, the case where the IFFT having the cycle of 256 is used to generate the carrier of 257 waves is described. However, as an embodiment applied to the present invention, an example of using the IFFT having the cycle of 512 will be described below. As described in.

In the embodiment using the IFFT having a period of 512, the Nyquist frequency is not used as the pilot frequency, but a high-order frequency having a simple integer ratio relationship with the sample clock signal is used.

That is, when considering the IFFT of the period M, the pilot signal is arranged at the position of 1/2 of the Nyquist frequency, that is, the M / 4th frequency, and the carrier transmitted by the OFDM is the first carrier in the IFFT. The signals output up to the M / 4th and from the 3rd M / 4th to the Mth are used.

As described above, even if the IFFT of the cycle M = 2N is used, the output signal of the IFFT equivalent to that when the IFFT of the cycle N is used can be obtained. Therefore, a continuous pilot signal including the guard interval can be transmitted, and a sample clock signal can be obtained by decoding this pilot signal and multiplying it by four.

In the sample synchronizing signal generating circuit used at this time, the frequency of the pilot signal is the same as that of the embodiment in which the cycle N is 256, but the FF shown in FIG.
The sample clock frequency for driving the T / QAM decoding circuit 27 is double that when the cycle N is 256. Accordingly, the doubled 198 kHz sample clock signal is output.

Therefore, in this sample synchronizing signal generation circuit, the frequency division ratio of the frequency division ratio variable circuit 50 is 1 in comparison with the above embodiment.
/ 213 to 1/219 and that the frequency dividing ratio of the 1/2 frequency dividing circuit 51 is 1/4, and the other configurations are the same as those in FIG. 4, and the description thereof is omitted. To do.

[Brief description of drawings]

[0107]

FIG. 1 is a block diagram of an embodiment of an OFDM signal transmitting apparatus according to the present invention.

FIG. 2 is a block diagram of an embodiment of an OFDM signal receiving apparatus according to the present invention.

FIG. 3 is a diagram showing a relationship between a symbol period and a guard interval of an OFDM signal according to an embodiment of the present invention.

FIG. 4 is a block diagram of a carrier extraction unit and a sample synchronization signal generation unit of an OFDM signal receiving apparatus according to an embodiment of the present invention.

FIG. 5 is a block diagram of a conventional OFDM signal transmitter.

FIG. 6 is a block diagram of a conventional OFDM signal receiving apparatus.

FIG. 7 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 8 is a diagram showing a relationship between a sync signal and a symbol period according to an embodiment of the present invention.

FIG. 9 is a diagram showing a relationship between a synchronization signal and a symbol period.

FIG. 10 is a diagram showing a relationship between a sync signal and a symbol period according to an embodiment of the present invention.

FIG. 11 is a diagram showing an example of a phase synchronization circuit.

FIG. 12 is an output waveform diagram of the phase locked loop circuit.

FIG. 13 is a diagram showing another example of the phase synchronization circuit.

[Explanation of symbols]

[0108] 2 serial-parallel conversion circuit 3 IFFT, pilot signal generation circuit 4 Guard interval setting circuit 4A RAM (random access memory) 5 D / A converter 6,24,42,53,114,134 LPF 7 Quadrature modulator 8,30 90 ° shift circuit 9,31 Intermediate frequency generation circuit 10 Clock signal generation circuit 11,21 Frequency converter 12 Transmitter 20 Receiver 23 Quadrature demodulator 25 A / D converter (sampling circuit) 26 Guard interval processing circuit 27 FFT, QAM decoding circuit 28 Parallel-serial conversion circuit 29 Carrier detection circuit 32 sample sync signal generator 33 Symbol synchronization signal generation circuit 40, 41, 52 Multiplier (phase comparator) 43, 50, 115, 135 VCO circuit 44,45 1/4 divider circuit 51 1/2 divider circuit 111, 112, 131, 132 Phase comparator (PD) 116, 136 signal switch

─────────────────────────────────────────────────── --Continued from the front page (56) Reference JP-A-56-134862 (JP, A) JP-A-56-158545 (JP, A) JP-A-60-52147 (JP, A) JP-A-6- 141020 (JP, A) JP-A-7-273741 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04J 11/00

Claims (2)

(57) [Claims] 1. A multilevel QA supplied with a digital information signal.
An IFFT for generating an M modulation signal, a pilot signal generation circuit, a guard interval setting circuit configured to repeatedly transmit a part of the modulation signal for a predetermined time,
A clock signal generation circuit for generating a clock signal for driving both circuits, and the IFFT and pilot signal generation circuits hold the phases at the start points of a plurality of effective symbol sections in opposite phases in adjacent effective symbol sections. A pilot signal having a higher frequency, which has a constant amplitude and is held at a constant frequency ratio with the clock signal, is present as a signal having only a real part in the guard interval section set by the guard interval setting circuit. In this way, a transmitter configured to continuously transmit over a plurality of the symbol intervals, and a signal generating unit for generating a clock signal having a frequency ratio of a predetermined integer to the pilot signal transmitted from the transmitter. And counting the number of clocks of the clock signal generated by the signal generating means And a signal generating means for generating a driving signal, and an FFT means driven by the driving signal generated by the signal generating means to convert the multi-level QAM modulated signal into the digital information signal. Orthogonal frequency division multiplexed signal transmission / reception system comprising the above receiving device. 2. A multi-valued QAM modulated signal including a pilot signal is IFFTed on the supplied digital information signal based on a predetermined clock signal, and a part of the multi-valued QAM modulated signal is repeated for a predetermined time to guard. A method for transmitting and receiving an orthogonal frequency division multiplex signal for generating an interval signal, transmitting the generated guard interval signal in front of the multi-level QAM modulated signal, and receiving the transmitted signal, comprising: Of the high-order frequency pilot signal having a phase ratio at the start point of the effective symbol section which is opposite to each other in the adjacent effective symbol section and whose amplitude is kept constant and which has an integer frequency ratio relationship with the clock signal. The first step of generating and the pilot signal generated in the first step are combined with a predetermined guard interface which is set in advance. A second step of continuously transmitting the signal over the plurality of symbol sections so that it exists as a signal having only a real part in the pulse section, and a frequency ratio of a predetermined integer to the pilot signal transmitted in the second step. Third for generating related clock signals
And a fourth step of counting the number of clocks of the clock signal obtained in the third step to generate a drive signal, and being driven by the drive signal generated in the fourth step, A fifth step of obtaining the digital information signal by performing FFT conversion on the multilevel QAM modulated signal, and a method for transmitting and receiving an orthogonal frequency division multiplexed signal, comprising: