JPH0222584B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a method of transmitting a prefix word at the beginning and an information word following it in a burst signal in TDMA (time division multiple access system) suitable for satellite communication systems. The present invention relates to a gate signal extraction circuit that is installed inside a receiving device that receives digitally modulated waves and supplies a gate signal to a demodulation circuit or a timing signal regeneration circuit.

[Conventional technology]

One of the communication methods suitable for communication systems such as satellite communication systems is the burst communication method. In the burst communication method, a transmission operation is performed only when transmitting information. This type of burst communication method is
It has the advantage of reducing power requirements and allowing communication between multiple transmitting and receiving stations using the same satellite and the same frequency band. In a burst communication method using such a satellite (transponder), an offset PSK modulation method is used. This is because this offset PSK modulated wave has little envelope fluctuation.
Even if a transmission path has a nonlinear response, it is less affected by its nonlinear characteristics, and in satellite communication systems, using the satellite's onboard amplifier at the saturation level makes more effective use of transmission power and reduces system costs. It is from.

[Problem that the invention seeks to solve]

However, compared to conventional PSK modulation, because an offset modulation circuit is added, and because the signal is transmitted at saturation level, there is less envelope fluctuation, and because the signal-to-noise ratio is not good in normal communication systems, burst-like offset Several problems still need to be solved in order to implement a PSK modem (Burst Mode Offset PSK Modem) in a practical line.

In burst digital modulation communication systems, information is represented in the form of relative phase changes of carrier waves. Demodulation of such a digital signal is performed by comparing the phase of the digital modulation signal with the phase of a reference carrier wave. Therefore, when demodulating a digitally modulated signal, it is necessary to reproduce the reference carrier wave from the received signal on the receiving side. At the same time, a timing signal is also required to reproduce the digital information sent from the demodulated output.
This must also be recovered from the received signal.
However, such reference signals such as a reference carrier wave and a timing signal are not reproduced instantaneously with the arrival of a burst, but are generally accompanied by a certain time delay. The time required to reproduce this reference signal is called acquisition time. During this acquisition time, no reference signal has been established, so information cannot be transmitted. Therefore, the leading edge of the burst does not contain any communication information that lasts for a time corresponding to the acquisition, and instead contains only a preamble word (a preamble word, a synchronization word to encourage the establishment of a reference signal). , and the word for transmitting station identification is also called a prefix word, but here only the word for synchronization is called a prefix word.), followed by an information word. The following method is used.

In such communication performed by bursts consisting of a prefix word and an information word, it is required to make the prefix word as short as possible in order to improve communication efficiency. That is, the performance required of the prefix is to reliably transmit information regarding the reference carrier wave and information regarding the timing signal within a short period of time. Furthermore, as an additional required performance, it is desirable to include information for detecting the boundary between the prefix part and the information word part of the burst on the receiving side. Although it is advantageous for the prefix to be unmodulated from the standpoint of shortening the acquisition time of reference carrier wave regeneration and reducing its phase jitter, it is not possible to extract the timing signal from the unmodulated signal.

One of the methods usually taken is to
In one part, the signal is unmodulated and the reference carrier is established exclusively, and in the other part, 0, π,
This method applies deep modulation such as 0, π, etc. to promote the establishment of a timing signal. Since this method requires allowance for the acquisition time of both the reference carrier wave and the timing signal, it is not an effective method especially when there is a demand for shortening the prefix. Another method is to apply appropriate phase modulation (PSK) over the entire prefix word and, in parallel with extracting a timing signal from this, establish a reference carrier wave from the PSK signal.

When the information word following the prefix word is an offset PSK modulated wave, the envelope fluctuation of the modulated wave is originally small, and in most cases, taking advantage of this characteristic, the nonlinear transmission path is output at its saturation level. Therefore, it is difficult to extract the timing signal using envelope detection, and an extraction method using a phase detection method such as delayed detection or a frequency discrimination method such as FM detection is adopted.

However, even if such a method is adopted, the timing signal extracted from the information word portion has a poor signal-to-noise ratio and is often unsatisfactory as a timing signal used for phase demodulation of the information word portion. Therefore, since the satellite communication system can receive the pilot signal in advance and establish frame synchronization, it is possible to send out the gate signal in accordance with the timing of receiving the burst digital modulation signal to be received. Therefore, by receiving this gate signal so that it acts only when the prefix part of the burst signal is received, the timing signal is extracted and reproduced from the prefix part, and the timing signal is extracted from the prefix part and reproduced. A timing signal reproducing circuit has been devised that uses a previous gate signal to hold the phase of the reproduced timing signal when receiving a portion.

Even with this circuit, the pilot signal is received and regenerated through the demodulation circuit, so the demodulation circuit cannot be established in the very initial state, and if the pilot signal is not received and regenerated, the timing signal regeneration circuit cannot be established. It was hot. Furthermore, the fact that the gate signal must be supplied from the pilot signal regeneration circuit has the disadvantage of complicating the satellite communication system.

It is an object of the present invention to overcome these drawbacks and to provide a device that can reproduce a carrier wave signal and a timing signal from a burst-shaped offset PSK modulated wave including a prefix word and an information word within a short acquisition time. do.

[Means for solving problems]

This invention uses the structure of the prefix as a carrier wave with a phase α and a phase β (α and β are arbitrary phases, but β−α≠0,
To provide a gate signal extraction circuit which uses a phase modulated wave that alternately takes π) and can reproduce a timing signal without receiving a gate signal from the outside.

By using the output of the gate signal extraction circuit according to the present invention, it is possible to eliminate polarity fluctuations in the demodulation code of the demodulation circuit, and to construct an absolute phase detection demodulation circuit. This greatly contributes to improving demodulation code error rate characteristics.

〔Example〕

The drawings will be explained in detail below.

FIG. 1 is a block diagram of a clock signal regeneration circuit according to an embodiment of the present invention. 1 is a timing signal extraction circuit. The timing signal component extracted in step 1 is supplied to a phase comparator circuit 3 after having phase jitter and amplitude jitter removed by a jitter component removal circuit 2 . The output of the reference clock oscillation source 6 is given to one input of the phase comparison circuit 3 via the phase variable circuit 5, and the other input is given the output of the reference clock oscillation source 6 via the phase variable circuit 5.
The output of the jitter component removal circuit 2 is given.
The phase comparison circuit 3 compares the phases of these two signals, detects a phase difference component, and supplies this to the gate circuit 4. In the gate circuit 4, the signal detected by the gate signal detection circuit 7 according to the present invention is supplied from the terminal 9, and when the gate signal is on, the phase difference component is appropriately amplified and supplied to the phase variable circuit 5 from the terminal 13. do. As a result, the phase of the reference clock signal is brought closer to the received timing signal, and this signal is supplied from terminal 10 to other receiving circuits.

Since this circuit forms a feedback circuit, it continues while the gate signal supplied to terminal 9 is on, and the phase of the reference clock oscillation source output from terminal 10 is determined by the timing of the received digital signal. It is controlled so that it always approaches the phase of the signal.

Here, while the gate signal supplied from the terminal 9 is off, the gate circuit 4 acts to hold the phase variable circuit control voltage immediately before turning off.
Therefore, if the stability of the timing frequency of the received signal is good, and the frequency stability of the reference clock oscillation source 6 is also good, and the value of the frequency difference between the two, including frequency fluctuation, is small, the receiving side demodulator The reproduction timing signal phase error allowed when the circuit identifies and reproduces the demodulated waveform can be designed to be sufficiently small to follow the timing signal phase of the input wave.

FIG. 2 shows a gate signal detection circuit 7 according to the present invention.
FIG. 2 is a block diagram showing one embodiment of the invention. The received signal input from the terminal 8 passes through the delay circuit 14 and is delayed by a fixed time (1/2) T or T (T is the symbol period, that is, the reciprocal of the timing frequency), and then passes through the phase detection circuit. 15. A received signal inputted from one terminal 8 is partially branched and supplied to the other terminal of the phase detection circuit 15, forming a delay detection circuit.

In this delay detection circuit, if the delay time of the delay circuit 14 is selected as T, the detection output generated when receiving the prefix part will be (1/2) when the timing frequency is _s .
_s , the phase jitter component of the extracted timing wave signal is removed by passing it through the band waver 16 whose center frequency is (1/2) _s , and at the same time, the phase jitter component of the extracted timing wave signal is removed. This improves the signal-to-noise ratio by removing the increased thermal noise added during reception.

If you choose the delay time of delay time 14 to be (1/2)T, then
Since the detection output generated when receiving the prefix part is _s , the bandpass filter 16 with center frequency _s is used.
use. However, in this case, the efficiency of the phase detector deteriorates. Therefore, it is desirable to select the delay time of the delay circuit 14 to be n·T (n is a positive integer).
The signal whose signal-to-noise ratio has been improved in this way is subjected to envelope detection by the wave detector 17 to generate a gate signal. The generated gate signal is appropriately amplified and waveform-shaped by a limiter circuit for limiting the amplitude, etc., and then outputted to the terminal 9.

FIG. 6 shows a waveform time chart when the delay time of the delay circuit 14 is set to T in FIG. 2.

The input signal phase is modulated alternately with α and β, and is delayed by T in the delay circuit 14.
5, the signal a before delay (FIG. 6a) and the input signal b after delay (FIG. 6b) are input. Considering the component of the difference between the phase α and the phase β in the output of the phase detection circuit 15, α-β and β-α appear alternately. That is, if α=0 and β=90°, -90° and +90° appear alternately. This is a signal with a period of 1/(2T),
That is, it can be seen that a timing signal c (Fig. 6c) having a frequency of (1/2) _s can be output.

Furthermore, when the timing signal c (FIG. 6c) passes through a bandpass filter 16 with a center frequency of 1/2 _s for noise removal, it becomes a waveform as shown in FIG. 6d. The output signal from the bandpass filter 16 is input to the wave detector 17, and is outputted as a waveform as shown in FIG. 6e, that is, as a gate signal. In reality, this waveform has slightly rising and falling edges compared to the ideal gate signal waveform shown in Figure 6, that is, a waveform that is undisturbed by ignoring the passing time of the bandpass filter. It becomes distorted.

In the explanation of Fig. 6, α=0 and β=90°, but the same effect can be obtained by setting α=90° and β=0, and also when α and β have other phase relationships. Although the phase detection output sin(α-β) and sin(β-α) change, the timing signal with a period of (1/2) _s is still output.

Next, in Fig. 2, the delay time of the delay circuit 14 is T/2.
The case is shown in FIG.

In this case, the phase difference is α-β every T/2,
0, β-α, 0 appear repeatedly, α=0, β=
When it is 90°, every T/2 becomes -90°, 0°, 90°, 0°. Therefore, it can be seen that the phase difference output becomes a timing signal with a period of 1/T= _s , as shown in FIG. 7c. In this case, the amplitude is 1/2 compared to the case shown in FIG. In the case of Fig. 7, when α and β have other phases, the phase detection output is cos(α−β),
Although cos(β−α) changes, the frequency of _s remains the same.

If the prefix placed at the beginning of the received burst signal is a signal that is phase-modulated so that the carrier wave alternately has a phase α and a phase β,
As mentioned earlier, a frequency signal of (1/2) _s is sent to the output of the delay detection circuit, but in the information word that follows this prefix, the output of the delay detection circuit is a random signal. Therefore, it does not have a specific frequency component. Therefore, after passing through the bandpass filter 16 whose center frequency is (1/2) _s , the amounts of signals passing through the prefix word part and the information word part are significantly different. Therefore, this output is envelope-detected by the detector 17, and a gate signal can be created to distinguish whether the received signal is a prefix word part or an information word part based on the magnitude of the detection level. .

FIG. 3 is a block diagram showing another embodiment of the gate signal detection circuit 7 according to the present invention. The received signal input from the terminal 8 is sent to the frequency discrimination circuit 18.
The regular phase fluctuation of the prefix part placed at the beginning of the received burst signal is detected in the form of frequency fluctuation, and the frequency signal of (1/2) _s is output from the frequency discrimination circuit 18. Sent out. This output is shaped into a gate signal waveform by a band wave generator 16 and a wave detector 17 having a center frequency of (1/2) _s , as in the embodiment shown in FIG.

In order to make the meaning of the present invention more concrete, FIG. 4 is a diagram showing an example of the phase relationship between a prefix word and an information word, taking a burst-like offset PSK modulated wave as an example. FIG. 4a shows the envelope waveform of the received burst-like signal, which burst is formed from a prefix word portion 19 and an information word portion 20. In the figure, T indicates the symbol period. This is equal to the reciprocal of the timing frequency. This received signal is subjected to four-phase phase offset modulation with a symbol period T and an offset of (1/2)T.

An example of the phase change is shown in waveforms 21 and 22 in FIG. 4b. In the prefix word portion 21, the phase alternately takes α and β, and in the information word portion 22, the phase takes any value among 0, π/2, π, and 3π/2. However, since there is an offset of T/2, the phase change is limited to 0, ±π/2 for every T/2.

Correspondingly, the gate signal appearing at terminal 9 in FIG. 1, ie, the output of gate signal extraction circuit 7 according to the invention, is shown at 23 and 23' in FIG. 4c. FIG. 4d shows the output waveform of the timing signal reproducing circuit that also appears at the terminal 10 of FIG. 1. Fourth
Figure c shows the waveform of the gate signal, of which 2
The gate circuit 4 shown in FIG. 1 is turned on for the time interval shown at 23', turned off for the time interval shown at 23', and maintains the voltage appearing at the output terminal 13 of the gate circuit 4 immediately before turning off. do the action. Further, FIG. 4d shows timing signal reproduction waveforms, of which 24 are timing signal reproduction waveforms held by the gate circuit of FIG.
4' shows a timing signal reproduction waveform in the process of pulling in the phase of the received timing signal. That is, when compared with the gate signal in Figure 4c, the timing signal is regenerated while the gate signal is 23, and in the state 23', the operation process that holds the previously regenerated signal is be understood.

FIG. 5 is a vector diagram showing the phase relationship between waveforms 21 and 22 in FIG. 4. The phase change in the prefix word part is expressed as a variation in vectors 29 and 30, and the phase change in the information word part is represented by vector 2.
It is represented by vector changes of 5, 26, 27, and 28. As is clear from this vector diagram, vector 29 can be divided into vectors 31 and 32. Also, vector 30 is vector 31,
It can be divided into 33 parts. Therefore, the phase in the prefix part is continuous in time, and vector 3 represents a component with the same phase as vector 25.
1 and the sum of vectors 32 and 33 that occur alternately in time.

From a signal containing such continuous components, the continuous components, that is, the reference carrier wave, can be directly extracted using a phase synchronization circuit or a narrow band pass filter without using a phase modulation component removal circuit, resulting in a short acquisition time. The reference carrier wave can be recovered within a short period of time. Furthermore, as mentioned earlier, by using the delay detection circuit and the frequency discrimination circuit, the timing frequency ( _s /2) component can be extracted from the vectors 32 and 33 that occur alternately in time, so the timing signal can be played within a short acquisition time. Furthermore, it is clear from FIG. 4a that the interval of vector change is (1/2)T when the information word portion is received. Also, since vector changes do not necessarily occur alternately, the future timing frequency ( _s /
2) It is easy to understand that the number of components is reduced. It can be seen that the gate signal can be extracted by detecting the signal after passing it through a bandpass filter with the output center frequency _s /2 of the delay detection circuit or the frequency discrimination circuit.

In addition, this gate signal output is supplied to the carrier wave regeneration circuit inside the demodulation circuit, and a specific one is specified among n (n is a positive integer) recovered carrier wave phases of the carrier wave regeneration circuit when receiving the prefix part. It becomes possible to do so. This eliminates the need to use a code conversion circuit for relieving pull-in phase fluctuations. As a result, loss of signal power due to insertion of the code conversion circuit can be improved, and economy can be achieved. This is because there is no information transmission when the prefix part is received, and even if the carrier recovery circuit is fixed only when the prefix part is received using a specific gate signal, there will be no loss of information transmission. is also understood.

In addition, when the above-mentioned carrier wave regeneration circuit is a carrier wave regeneration circuit for n-phase PSK modulated digital waves,
It is known that n carrier recovery phases can be introduced.

The gate signal extraction circuit according to the present invention is particularly effective when used to extract a gate signal from a burst-shaped offset PSK modulation signal.
Although this case has been described as an example, the circuit of the present invention can be implemented in any modulation format for the information word as long as it is a digitally modulated wave.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to create a gate signal so that carrier wave regeneration and timing signal regeneration can be performed within a short acquisition time on the reception side of burst digital communication. This is particularly effective when the information word contained in the data is an offset modulated signal, and it greatly contributes to the development of satellite communication systems and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a clock signal regeneration circuit using an embodiment of the present invention. FIG. 2 is a block diagram of an embodiment of a gate signal extraction circuit according to the present invention. FIG. 3 is a block diagram showing another embodiment of the invention. FIG. 4 is a diagram showing the phase relationship between a prefix word and an information word, taking as an example a burst-shaped offset PSK modulated wave applied to the present invention. a shows the received envelope waveform, b shows the phase change of the received waveform, c shows the gate signal waveform, and d shows the timing signal reproduction waveform. FIG. 5 is a vector diagram showing the phase relationship between the prefix word and the information word shown in FIG. 4. FIG. 6 is a waveform time chart illustrating the operation when the delay time of the delay circuit of the embodiment shown in FIG. 2 is T. FIG. 7 is a waveform time chart illustrating the operation when the delay time of the delay circuit of the embodiment shown in FIG. 2 is set to T/2. 1... Timing signal extraction circuit, 2... Jitter component removal circuit, 3... Phase comparison circuit, 4... Gate circuit,
5... Phase variable circuit, 6... Reference clock oscillation source, 7
...Gate signal extraction circuit, 8...Received signal input terminal,
9...Gate signal input terminal, 10...Reproduction timing signal output terminal, 14...Delay circuit, 15...Phase detection circuit, 16...Band wave detector, 17...Detector, 18...
Frequency discriminator.

Claims (1)

[Scope of Claims] 1. Provided in a time division multiple access receiving device in which digital communication signals are sent out in bursts, and arranged as a prefix at the beginning of the burst signals, phase α and phase β (α , β are arbitrary phases, however, β-α≠0, π). In a circuit that extracts a gate signal to be supplied to a demodulation circuit or a timing signal regeneration circuit from a received signal, A delay circuit 14 to which an input signal is applied; a phase detection circuit 15 which receives the output signal of this delay circuit and an input signal as two inputs; a band pass filter 16 through which the output signal of this phase detection circuit passes; 1. A gate signal extraction circuit using a time division multiple access method, comprising: an envelope detector 17 which receives the output of a wave detector as an input. 2. When the timing frequency of the input signal is _s , the delay time of the delay circuit is 1/ _s , and the passband of the bandpass waveform is (1/2) _s . Gate signal extraction circuit using division multiple access method. 3 When the timing frequency of the input signal is _s , the delay time of the delay circuit is (1/2)・(1/ _s ),
2. The time division multiple access gate signal extraction circuit according to claim 1, wherein the band pass waveformer has a passband of _s . 4 A digital communication signal is provided in a time division multiple access receiving device that sends out digital communication signals in burst form, and is placed as a prefix at the beginning of the burst signal to indicate phase α and phase β (α and β are arbitrary phases). , where β-α≠0, π), the frequency at which the input signal is given in a circuit that extracts a gate signal to be supplied to a demodulation circuit or a timing signal regeneration circuit from a received signal from a signal that is phase-modulated so as to take alternately A time division multiplexer comprising: a discriminator circuit 18; a bandpass waveform generator 16 through which the output signal of the frequency discrimination circuit passes; and an envelope detector 17 whose input is the output of the bandpass waveform generator. Connection type gate signal extraction circuit.