JPH0779269A - Delay detection circuit - Google Patents

Abstract

PURPOSE:To facilitate the LSI adaptation enabling the constitution of a circuit with only a digital circuit by using the clock from the same oscillator for a first frequency conversion circuit and a digital instantaneous phase detection circuit. CONSTITUTION:A 1/n frequency divider 103 frequency divides a clock signal to n and obtains the clock signal of a frequency f2/n as the output. The clock signal of f2/n and a modulation wave signal of f1 are inputted into an EX-OR circuit 104 and the modulation wave signal of f3=f1-f2/n is obtained as the output. A 1/m frequency divider 108 frequency divides the clock signal to m and obtains the clock signal of f2/m. Api/2 phase converter 109 obtains the clock signal where the clock signal of f2/m is shifted by 90 deg. phase. Therefore, the modulation wave signal of f3=f1-f2/n and the clock signal of f2/m are inputted in an EX-OR circuit 106, and the modulation signal of f3=f1-f2/n and the clock signal of f2/m shifted by 90 deg. phase are inputted in an EX-OR circuit 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential detection circuit used in a demodulation circuit of a digital communication device, and more particularly to a differential detection circuit suitable for integrating a .pi. / 4 shift QPSK demodulation circuit used in a digital cordless telephone into an LSI. It is a thing.

[0002]

2. Description of the Related Art A conventional differential detection circuit is a π / 4 shift QPSK differential detection circuit for digital cordless telephones.
4-shift QPSK differential detection circuit ". In the disclosed differential detection circuit, an instantaneous phase circuit is composed of an exclusive OR circuit (hereinafter referred to as EX-OR circuit), a D-type flip-flop circuit, an analog reduction reactor, an analog / digital converter and a logic circuit. It was The phase detection characteristics of the combination of the EX-OR circuit and the analog reduction reactor wave are 0 to π rising to the right and π to 2π falling to the right. Therefore, the polarities are switched by the output of the D-type flip-flop circuit to form a straight line. The phase can be detected.

[0003]

However, the analog reduction reactor and the analog / digital converter are extremely difficult to be integrated into an LSI, and it has been desired to realize a differential detection circuit having a circuit configuration that can be easily integrated into an LSI.

[0004]

Therefore, in the present invention, the first frequency is based on the first and second clock signals of the same frequency, which are generated based on the reference clock signal and are out of phase with each other by π / 2. A second frequency conversion circuit that outputs first and second modulated wave information signals in which the frequency of the modulated wave signal converted by the frequency conversion circuit is dropped to a base band (base band), and the first and second modulation circuits First and second moving average filter circuits that receive the wave information signals and output average values of the information of these signals, and the modulation wave signal is modulated from the outputs of these first and second moving average filter circuits. An instantaneous phase detection circuit of a delay detection circuit was constructed with a logic circuit that outputs information digitally.

[0005]

The first frequency conversion circuit converts the modulated wave signal into a frequency band suitable for operating the instantaneous phase detection circuit. The second frequency conversion circuit converts the modulated wave signal into a signal having information of the modulated wave phase component by two clock signals which are shifted by 90 °. The first and second moving average filter circuits digitally output the average value of the phase component of the modulated wave in a constant time and the information on the phase shift direction. Then, the logic circuit combines the digital information of the phase components of the modulated waves generated by the first and second moving average filter circuits.

[0006]

1 is a circuit diagram of a differential detection circuit according to a first embodiment of the present invention, which will be described below with reference to the drawings.
An example will be described. Input terminal 101 has frequency f1
A modulated wave signal (for example, 10.8 MHz) is input.
The oscillator 102 has a frequency f2 (eg, 19.2M) that is sufficiently higher than the frequency f1 and is N times the data clock (eg, 384 kHz) (where N is a positive integer; eg, 50).
A clock signal having a frequency of Hz). This oscillator 1
The output of 02 is passed through a 1 / n frequency divider 103 (where n is a positive integer; for example, 2), and a first EX-OR circuit 104 is provided.
Connected to one input. First EX-OR circuit 10
The other input of 4 is connected to the input terminal 101.
The output of the first EX-OR circuit 104 is connected to the input of the instantaneous phase detection circuit 105. Instantaneous phase detection circuit 105
Are the second and third EX-OR circuits 106, 107,
1 / m frequency divider 108 (where m is a positive integer; for example, 1
6), π / 2 phase shifter 109, first and second moving average filter circuits 110 and 111, and first logic circuit 11
2 and. The first EX is connected to one input of each of the second and third EX-OR circuits 106 and 107.
-The output of the OR104 circuit is connected. 1 / m frequency divider 1
The input of 08 is connected to the output of oscillator 102. The other input of the second EX-OR circuit 106 is connected to the output of the 1 / m frequency divider 108. The output of the 1 / m frequency divider 108 is also connected to the input of the π / 2 phase shifter 109. Third
The other input of the EX-OR circuit 107 is connected to the output of the π / 2 phase shifter 109.

The output of the second EX-OR circuit 106 is the input of the first moving average filter circuit 110 whose control terminal is connected to the output of the oscillator 102, and the output of the third EX-OR circuit 107 is its output. The control terminal is connected to the input of the second moving average filter circuit 110, which is connected to the output of the oscillator 102. Here, the circuit configurations of the first and second moving average filter circuits are the same, and the circuit diagram thereof is shown as FIG. The moving average filter circuit used in the first embodiment has 2 ^P stages (where P is a positive integer), as shown in FIG.
Shift register 405, second logic circuit 406 and up / down counter 407. The input 401 of the moving average filter circuit is connected to the input of the first stage A of the shift register 405. Shift register 405
The clock input of is the control input 40 of the moving average filter circuit.
4 to the oscillator 102. The output of the first stage A and the output of the second ^P stage of the shift register 405 are the second
Of the logic circuit 406. The clock input of the second logic circuit 406 is connected to the control input 404 of the moving average filter circuit. The output of the second logic circuit 406 is connected to the input of the up / down counter 407, and the output of the up / down counter 407 becomes the output 408 of the moving average filter circuit.

Now, returning to FIG. 1, the instantaneous phase detection circuit 10
Continuing with the explanation in 5. The outputs of the first and second moving average filter circuits 110 and 111 are the same as those of the first logic circuit 112.
Connected to each of the two inputs. Then, the output of the first logic circuit 112 becomes the output of the instantaneous phase detection circuit 105. The output of the instantaneous phase detection circuit 105 is connected to the input of the second delay circuit 113 and the input of the phase difference calculation circuit 114. The clock input of the second delay circuit 113 is connected to the oscillator 112. Phase difference calculation circuit 114
Is connected to the input of the clock recovery circuit 116 and is also connected to the input of the data recovery circuit 115. The clock input of the clock recovery circuit 116 is connected to the oscillator 112, and the clock input of the data recovery circuit 115 is connected to the output of the clock recovery circuit 116. The output of the data recovery circuit 115 and the output of the clock recovery circuit 116 are respectively connected to the reproduction data output terminal 117 and the reproduction clock output terminal 118 of the differential detection circuit of the first embodiment.

Next, the operation of the differential detection circuit of the first embodiment will be described. Since the 1 / n frequency divider 103 divides the frequency of the clock signal by n, the clock signal having the frequency f2 / n is output from the output. First EX-OR circuit 10
Since the clock signal of frequency f2 / n and the modulated wave signal of frequency f1 are input to 4, the frequency f3 is output from the output.
The modulated wave signal of = f1-f2 / n is output. In this way, the 1 / n frequency divider 103 and the first EX-OR circuit 1
04 functions as a mixer for converting the frequency of the modulated wave signal. Since the 1 / m frequency divider 108 divides the clock signal by m, the clock signal having the frequency f2 / m is output from its output. The π / 2 phase shifter 109 has a frequency f2 /
A clock signal in which the phase of the clock signal which is m is shifted by 90 ° (by π / 2) is output. Therefore, the second EX-OR circuit 106 receives the modulated wave signal having the frequency f3 = f1-f2 / n and the clock signal having the frequency f2 / m, and the third EX-OR circuit 107 receives the frequency f.
3 = f1-f2 / n modulated wave signal and frequency f2 / m
And a clock signal whose phase is shifted by 90 ° is input. These second and third EX-OR circuits 106,
The frequency of the output modulated wave signal of 107 is f4 = f1−f2 /
It becomes n-f2 / m.

Here, the frequencies f1 and f2 and the frequency division numbers n and m
Has the following relationship. f2 / m = f1-f2 / n (1) Substituting the above equation into f4 results in f4 = 0, and the signals output from the second and third EX-OR circuits 106 and 107 are modulated wave signals. It becomes a baseband modulated wave information signal in which the modulated wave frequency of is dropped to the baseband.
This baseband modulated wave information signal is input to the shift register 40 via the input 401 of the moving average filter circuit shown in FIG.
5 to the input of the first stage A. Shift register 4
At 05, the baseband modulated wave information signal is sampled as data in accordance with the sampling clock signal input to the clock input and read into the first stage A. The shift register 405 shifts the data read for each sampling clock signal is advanced one cycle to the right, the data read in the first stage A is shifted to the 2 ^P stage B by 2 ^P over one sampling clock To be done. The first logic circuit 406 operates as shown in Table 1.
That is, the first logic circuit 406 is the shift register 405.
The data read in the first stage A of the data read in the 2 ^P stage B, the up-count signal in synchronization with the sampling clock, the operation of not outputted even down-count signals and any signal carried. The up / down counter 407 counts up by 1 when the signal from the first logic circuit 406 is an up count signal, and counts down by 1 when it is a down count signal.

[0011]

[Table 1] The output of the up / down counter 407, that is, the output of the moving average filter is generated from the signal obtained by exclusive ORing the clock signal and the modulated wave signal whose phases are shifted from each other by 90 °, and therefore these are modulated waves. Is a signal that digitally represents the average value of the phase difference component of and the information on the deviation direction of the phase difference. The first logic circuit 112 combines the average value of the phase difference components for a certain period of time and the digital information in the direction of deviation of the phase difference, and outputs it as modulated digital information of one modulated wave. First
The output of the logic circuit 112 is input to the second delay circuit 113 and the phase difference calculation circuit 114. Second delay circuit 1
At 13, the output of the first logic circuit 112 is delayed by the symbol rate (1/2 times the data rate in this embodiment) based on the reference clock signal generated by the oscillator 112, and then the phase difference calculation circuit 114 is delayed. input. In the phase difference calculation circuit 114, differential detection is performed by taking the difference between the output of the first logic circuit 112 and the output of the second delay circuit 113. The output of the phase difference calculation circuit 114, which is the delay detection output, is input to the data recovery circuit 115 and the clock recovery circuit 116. The clock reproduction circuit 116 reproduces the data clock signal from the differential detection output based on the reference clock signal generated by the oscillator 112. The regenerated data clock signal is output from the regenerated clock output terminal 118 and also to the data regenerating circuit 115. The data reproduction circuit 115 reproduces data based on the delayed detection output and the reproduction clock output signal generated by the clock reproduction circuit 116, and outputs the data from the data reproduction output terminal 117.

As described in detail above, according to the differential detection output circuit of the first embodiment, the modulation frequency input using the first frequency conversion circuit is reduced to a frequency band in which the digital instantaneous phase can be detected. Further, by using the clock from the same oscillator for the first frequency conversion circuit and the digital instantaneous phase detection circuit, the differential detection output circuit is configured without using the analog circuit even when the modulated wave input frequency is relatively high. be able to. Further, since the delay detection output circuit can be constructed only by digital circuits without using the analog reduction reactor and analog / digital converter, which have been conventionally required, it is extremely suitable for LSI implementation. In the first embodiment, the second delay circuit 113 and the clock recovery circuit 116 are operated by the reference clock signal of the frequency f2 generated by the oscillator 102. As an example, consider the case where the frequency (data rate) of the data clock is 384 kHz and the frequency f1 of the modulated wave signal input is 10.8 MHz. Since the frequency f2 of the signal input to the instantaneous phase detection circuit 105 is preferably about 1.2 MHz, considering these, f2 = N (= 50) × 384k
When Hz = 19.2 MHz, m = 16, and n = 2, the formula (1), that is, f2 / m = f1-f2 / n can be satisfied.
However, the input modulated wave frequency f1 = 10.7 MH
In the case of z, in order to satisfy the equation (1) with m = 16 and n = 2, the frequency f2 of the signal input to the instantaneous phase detection circuit 105 becomes 19.0222 MHz, and the data rate (3
It is not an integral multiple of (84 kHz). If f2 does not become an integral multiple of the data rate, the reference clock signal cannot be used because the delay in the second delay circuit 113 is the symbol rate (1/2 the data rate), and the clock recovery circuit 116 is used.
It is also difficult to extract the clock at, and the processing after the instantaneous phase detection circuit becomes difficult.

FIG. 3 shows a differential detection output circuit of the second embodiment which can solve this problem. In addition,
In FIG. 3, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. Considering a modulated wave input signal of 10.7 MHz, as described above, the frequency f2 ′ of the first clock signal output from the first oscillator 202 corresponding to the oscillator 102 of the first embodiment becomes 1902222 MHz, and the data It is not an integral multiple of the clock (384 kHz).
Therefore, in the second embodiment, a second oscillator 219 is provided and outputs a second clock signal having a frequency of f5 = 19.2 MHz (N = 50), for example. The output of the first oscillator 202 is connected only to the 1 / n frequency divider 103 and the 1 / m frequency divider 108. On the other hand, the output of the second oscillator 219 is the second delay circuit 113 and the clock recovery circuit 116.
Connected to. Further, in the differential detection output circuit of the second embodiment, the sampling circuit 220 is provided between the output of the instantaneous phase detection circuit 105 and the second delay circuit 113 and the phase difference calculation circuit 114. The sampling circuit 220 is controlled by the output of the 1 / k frequency dividing circuit 221 that frequency-divides the second clock signal output from the second oscillator 219 by k.

Next, the operation of the differential detection output circuit of the second embodiment will be described. The operation up to the output of the instantaneous phase detection circuit 105 is the same as the operation of the differential detection output circuit of the first embodiment, so the description thereof is omitted and the operation of the sampling circuit 220 will be mainly described. The output of the instantaneous phase detection circuit 105 is generated based on the first clock signal of the frequency f2 ′, but the processing thereafter is operated based on the second clock signal of the frequency f3 and becomes asynchronous. .
Therefore, the sampling circuit 220 is operated by a signal obtained by dividing the second clock signal by the 1 / k frequency dividing circuit 221. The sampling circuit 220 samples the output of the instantaneous phase detection circuit 105 at a timing that is asynchronous with the first clock signal and synchronized with the second clock signal. The subsequent operation is similar to that of the first embodiment, and therefore its explanation is omitted. Here, the output of the instantaneous phase detection circuit 105 has the high frequency component removed by the moving average circuit, and the data existing frequency band is very small with respect to the output sampling rate. Therefore, even if the sampling circuit 220 performs asynchronous sampling, there is almost no deterioration in data quality due to the aliasing phenomenon.

As described above, according to the differential detection output circuit of the second embodiment of the present invention, in addition to the effect of the first embodiment,
Even if the frequency of the input modulated wave signal is not an integral multiple of the data rate, the data clock signal and the data output can be easily reproduced. The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, although the moving average filter circuit shown in FIG. 2 is used in the above-described embodiment, another moving average filter circuit as shown in FIG. 7 can be used instead. FIG. 7 is a circuit diagram showing another moving average filter circuit, which is obtained by adding logic circuits 409 and 410 to the moving average filter circuit shown in FIG. The logic circuit 409 is the up / down counter 4
The first signal is output when all the values of 07 are 1, and the second signal is output when all the values of the up-down counter 407 are 0. In the logic circuit 410, when the logic circuit 409 outputs the first signal, the output of the up-count signal of the logic circuit 406 to the up-down counter 407 is stopped, and the logic circuit 409 outputs the second signal. At this time, the output of the down count signal of the logic circuit 406 to the up / down counter 407 is stopped. With this configuration, the moving average filter circuit is prevented from outputting an incorrect value due to noise or the like.

[0016]

As described above in detail, according to the present invention, the modulation frequency input using the first frequency conversion circuit is reduced to a frequency band in which the digital instantaneous phase can be detected,
Further, by using the clock from the same oscillator for the first frequency conversion circuit and the digital instantaneous phase detection circuit, the differential detection output circuit is configured without using the analog circuit even when the modulated wave input frequency is relatively high. be able to. Further, since the delay detection output circuit can be constructed only by digital circuits without using the analog reduction reactor and analog / digital converter, which have been conventionally required, it is extremely suitable for LSI implementation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential detection output circuit according to a first embodiment.

FIG. 2 is a circuit diagram of a moving average filter circuit according to a first embodiment.

FIG. 3 is a circuit diagram of a differential detection output circuit according to a second embodiment.

FIG. 4 is a circuit diagram of another moving average filter circuit.

[Explanation of symbols]

 101 Modulated Wave Input Terminal 102 Oscillator 103 1 / n Frequency Divider 104 First EX-OR Circuit 105 Instantaneous Phase Detection Circuit 106 Second EX-OR Circuit 107 Third EX-OR Circuit 108 1 / m Frequency Divider 109 π / 2 phase shifter 112 first logic circuit 110, 111 moving average filter circuit 113 second delay circuit 114 phase difference calculation circuit 115 data recovery circuit 116 clock recovery circuit 117 recovered data output terminal 118 recovered clock output terminal

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Seizo Nakamura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Kenzo Urabe 2-3-13 Toranomon, Minato-ku, Tokyo No. Kokusai Electric Co., Ltd.

Claims (8)

[Claims] 1. A modulated wave input terminal to which a modulated wave signal is input, a reference clock input terminal to which a reference clock signal is input, the modulated wave signal and a reference clock signal are input, and a reference clock signal is input based on the reference clock signal. A first frequency conversion circuit for converting the frequency of the modulated wave signal, and an instantaneous phase detection circuit for receiving the modulated wave signal with the converted frequency and digitally outputting the modulation information of the modulated wave signal, First and second modulation in which the frequency of the modulated wave signal is dropped to a baseband based on first and second clock signals of the same frequency, which are generated based on the clock signal and are out of phase with each other by π / 2 A second frequency conversion circuit that outputs a wave information signal, and a first frequency conversion circuit that receives the first and second modulated wave information signals and outputs an average value of information of these signals. And an instantaneous phase detection circuit having a second moving average filter circuit and a logic circuit for digitally outputting the modulation information of the modulated wave signal from the outputs of the first and second moving average filter circuits, and the instantaneous phase Phase difference calculation for calculating the phase difference of the modulation wave signal from the digital signal of the modulation information of the modulation wave signal output from the detection circuit and the delay signal obtained by delaying the digital signal for a predetermined time based on the frequency of the data clock signal And a differential detection circuit having a circuit. 2. The differential detection circuit according to claim 1, further comprising a clock regeneration circuit for regenerating a data clock signal from the output of the phase difference calculation circuit based on the frequency of the data clock signal, and an output of the phase difference calculation circuit for regeneration. And a data recovery circuit for recovering data from the data clock signal. 3. The first frequency conversion circuit comprises a 1 / n frequency divider circuit (where n is a positive integer) whose input is connected to the reference clock input terminal, and a first input which is the modulated wave. The differential detection circuit according to claim 1, further comprising an exclusive OR circuit connected to an input terminal and having a second input connected to an output of the 1 / n frequency dividing circuit. 4. A 1 / m frequency dividing circuit (where m is a positive integer) whose input is connected to the reference clock input terminal, and a first input which is the first frequency converter circuit. A first exclusive OR circuit connected to the output of the frequency conversion circuit and having a second input connected to the output of the 1 / m frequency dividing circuit; and an input connected to the output of the 1 / m frequency dividing circuit The above 1 / m
A π / 2 phase circuit that shifts the phase of the output signal of the frequency divider circuit by π / 2, a first input connected to the output of the first frequency conversion circuit, and a second input of the π / 2 phase circuit. The differential detection circuit according to claim 1, further comprising a second exclusive OR circuit connected to the output. 5. Each of the first and second moving average filter circuits inputs an input signal in synchronization with the reference clock signal, and inputs the first stage data and the final stage data. When the output shift register and the data of the first stage and the data of the final stage of this shift register have different values, an up-count signal or a down-count signal is output. 2. The differential detection circuit according to claim 1, further comprising a logic circuit that does not output the signal of 1. and an up-down counter that performs a counting operation based on the up-count signal or the down-count signal. 6. The differential detection circuit according to claim 1, wherein the phase difference calculation circuit and the clock recovery circuit are controlled based on the reference clock signal. 7. The second reference clock signal having a frequency of k times or 1 / k times (where k is a positive integer) of the data signal, which is different from the reference clock signal, in the phase difference calculation circuit and the clock recovery circuit. The differential detection circuit according to claim 1, which is controlled based on 8. The differential detection circuit according to claim 7, wherein the output signal of the instantaneous phase detection circuit is output via a sampling circuit which operates based on the second reference clock signal.