JP2000049882A - Clock synchronization circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a zero-cross detection system without the need of the double speed operation of an A/D converter. SOLUTION: Data for successive two symbols for which analog base band signals 101 are sampled by the sampling clock 102 of a modulation speed in an A/D converter 10 are held by shift registers 21 and 22, the data for the two symbols are added by an adder 23, the most significant bit is outputted and thus, the polarity of the data of the intermediate point of a sampling interval in the case of linearly interpolating the values of the two symbols is obtained. Then, by exclusive OR circuits 24 and 25 and a masking circuit 28, the phase information of the sampling clock 102 is extracted from the relation of the polarity of the data of the intermediate point and the polarity of the data of an original sampling point and outputted through an LPF 30 to a VCO 40 as an APC voltage 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization circuit for a demodulator used in a digital microwave communication system, and more particularly to a clock synchronization circuit for a multilevel quadrature amplitude modulation system.

[0002]

2. Description of the Related Art Wired and wireless communication systems use a quadrature amplitude modulation system as a modulation system. In recent years, digitalization of a demodulation device in a communication system using the quadrature amplitude modulation scheme has been promoted. In such a demodulation device, a clock is reproduced based on information extracted from the received signal, and the demodulation process is performed after the received signal is sampled and converted into a digital signal using the clock. Therefore, a demodulation device of the digitized quadrature amplitude modulation system requires a clock synchronization circuit for reproducing a clock synchronized with a clock on the transmission side.

As such a clock synchronization circuit, a zero-cross detection method is generally used.
No. 7229. A conventional zero-crossing detection method uses data obtained by sampling an analog baseband signal input to an A / D converter at twice the modulation speed, and the baseband signal is a median value of the amplitude of 0.
The error information of the sampling clock phase is extracted from the phase crossing the phase, and the PLL (Phase
Locked Loop). In the following, regarding the operation principle of the conventional zero-cross detection method, the modulation method is QPSK (Quadrature Phase).
Shift Keying (orthogonal PSK) will be described as an example.

FIG. 7 is a block diagram of a clock phase detection circuit of a conventional zero-cross detection system. Here, the symbol period is Ts, and the modulation frequency is fs (1 / Ts).

This conventional clock synchronization circuit includes an A / D converter 110, a clock phase detector 120, a loop filter (hereinafter abbreviated as LPF) 130, and a voltage controlled oscillator (hereinafter abbreviated as VCO) 140. It is composed of

The clock phase detector 120 includes flip-flop circuits (hereinafter abbreviated as F / F) 51 to 53.
, A frequency divider 60, and a condition determination circuit 70. The LPF 130 receives the output of the condition determination circuit 70 as an input, and suppresses the noise component of the input to output the APC (Au
tomatic Phase Control) Voltage 1
03 is generated and output. VCO140 is APC
It is controlled by the voltage 103 and generates and outputs a sampling clock 202 whose frequency is twice the modulation frequency fs. The A / D converter 110 converts the analog baseband signal 101 into a digital signal of a plurality of bits by sampling the analog baseband signal 101 with a sampling clock 202.

The frequency divider 60 divides the frequency of the sampling clock 202 having a frequency of 2 fs by １ ／ and generates and outputs a normal phase clock having a frequency fs and a negative phase clock having a frequency fs. The F / F 51 outputs the MSB (Mos) of the multi-bit digital signal output from the A / D converter 110.
t Significant Bit: Most significant bit)
Are used as data inputs, and the in-phase clock from the frequency divider 60 is used as a clock input. F / F52 is F / F
The output of 51 is used as a data input and the positive-phase clock from the frequency divider 60 is used as a clock input. F / F53
Operates with the MSB of the digital signal of a plurality of bits output from the A / D converter 110 as a data input and the inverted phase clock from the frequency divider 60 as a clock input.

As shown in FIG. 8, the condition determining circuit 70 includes an F / F 91, exclusive OR circuits 92 and 93,
And a mask circuit 128. Mask circuit 1
28 includes an AND circuit 94 and an F / F 95.

The F / F 91 operates using an output from the F / F 53 as a data input and a positive-phase clock from the frequency divider 60 as a clock input.

The exclusive OR circuit 92 performs an exclusive OR operation between the output of the F / F 91 and the output of the F / F 52, and outputs the operation result. Exclusive OR circuit 9
Numeral 3 performs an exclusive OR operation between the output of the F / F 52 and the inverted output of the F / F 51, and outputs the operation result.

The AND circuit 94 has an exclusive OR circuit 93.
And the logical product between the output of the frequency divider 60 and the positive-phase clock from the frequency divider 60, and outputs the result of the operation. F / F95
Operate with the output of the exclusive OR circuit 92 as the data input and the output of the AND circuit 94 as the clock input.

Next, the operation of the conventional clock synchronization circuit will be described.

A sampling clock 20 having a frequency of 2 fs
2 is frequency-divided by the frequency divider 60 into two clocks of the normal phase and the negative phase of the frequency fs. An F / F 51 that operates with the normal phase clock and an F / F 53 that operates with the negative phase clock
, Data sampled at intervals of Ts / 2 are input, and three consecutive sampling values at intervals of Ts / 2 are held in three F / Fs 51 to 53. The temporal relationship of the data held here is F / F5 in chronological order.
The numbers are 2, 53 and 51.

FIG. 9 is a diagram showing the relationship between the eye pattern of the analog baseband signal 101 input to the A / D converter 110 and the phase of the sampling clock 202. Here, it is assumed that the eye opening, which is the optimum sampling phase, is a phase 0, a phase slightly advanced therefrom is + Δp, and a phase slightly delayed is −Δp.

It is assumed that the F / Fs 51 and 52 correspond to the data of the eye opening, and the F / F 53 corresponds to the middle point of the eye opening. If it is limited to the case where the polarities of the F / Fs 51 and 52 are reversed, the analog baseband signal 101 input to the A / D converter 110 has a central value in the amplitude direction at some point during the interval Ts. Is crossing 0. The phase of the sampling clock 202 is +
In the case of Δp, if the polarity of the F / F 51 is at a high level (hereinafter abbreviated as H), the polarity of the F / F 53 also becomes H, and the F / F
If the polarity of 51 is at a low level (hereinafter abbreviated as L), F
The polarity of / F53 also becomes L. That is, F / Fs 51 and 53
Have the same polarity.

The phase of the sampling clock 202 is -Δ
At the time of p, when the polarity of the F / F 51 is H, the polarity of the F / F 53 becomes L, and when the polarity of the F / F 51 is L, the F / F
The polarity of 53 becomes H. That is, the polarities of the F / Fs 51 and 53 are reversed. When the phase is L, L and H of the F / F 53
Is 50%, the polarities of the F / Fs 51 and 53 match with a probability of 50%.

In summary, the F / Fs 51 and 52 sampled with the normal phase clock when the polarities are opposite are shown.
The match / mismatch of the polarities of the F / F 53 sampled with the clock 51 and the antiphase clock becomes the phase information of the sampling clock 202. If the phase of the sampling clock 202 is controlled based on the phase information, the normal phase clock obtained by the frequency divider 60 is controlled so as to have the optimum sampling phase.

The condition determination circuit 70 is a circuit for detecting the above conditions and outputting phase information. Here, as the phase information, the relationship between the polarities of the F / F 52 and the F / F 53 can be used, but in this case, the polarity of the phase information is inverted.

The data of the frequency fs, which is the output of the demodulator, is the double-speed data, which is the output of the A / D converter 110, since the positive-phase clock output from the frequency divider 60 always corresponds to the eye opening. It is obtained by thinning out the sampled data with a positive-phase clock of frequency fs.

The above is the operating principle of the zero-cross detection method. Here, the operation in the state where the C / N of the QPSK is good has been described. However, this clock synchronization method is a multi-valued signal even when the analog baseband signal input to the A / D converter includes a noise component. QAM (Quadratu
In the case of re-Amplified Modulation, it can be used similarly.

However, in the zero-cross detection method, Ts
Conventionally, the A / D converter was operated at double speed in order to obtain phase information from the sampling values at the interval of / 2.

In the zero-cross detection method, data after carrier wave synchronization is used as a clock phase information source. Therefore, when the zero-cross detection method is applied to a quasi-synchronous detection method in which carrier synchronization is performed by digital signal processing, an infinite signal for carrier wave synchronization is used. Phase shifter (hereinafter referred to as EPS (Endless P)
abbreviated as H. shifter). ), All the circuits that pass before data synchronized with the carrier can be obtained also require double speed operation.

As described above, the clock synchronization system of the zero-cross detection system requires an expensive device that can operate at high speed, and consumes a large amount of power. For this reason, it has been difficult to reduce the cost, apply to a device with a high modulation speed, and reduce the power consumption.

[0024]

In the above-mentioned conventional clock synchronous circuit, when the zero-crossing detection method is used, A
There is a problem that the double speed operation of the / D converter is required.

An object of the present invention is to provide a clock synchronous circuit capable of performing a zero-cross detection method without requiring a double speed operation of an A / D converter.

[0026]

In order to achieve the above object, a clock synchronization circuit according to the present invention provides an A / D converter for sampling an analog baseband signal with a sampling clock having the same cycle as a symbol cycle and converting the analog baseband signal into a digital signal.
A first D / A converter for holding data for one symbol of the digital signal converted by the A / D converter;
, A second shift register holding one symbol data output from the first shift register, and adding the output of the first cyst register and the output of the second shift register. Calculating an exclusive OR of the adder outputting the most significant bit of the operation result, the signal output from the adder, and the most significant bit of the first shift register; A first exclusive-OR circuit outputting a result, an exclusive-OR operation of the most significant bit of the first shift register and the most significant bit of the second shift register, and calculating the result of the computation. The output of the second exclusive-OR circuit and the output of the first exclusive-OR circuit are used as data inputs, and the data input is output in accordance with the logic of the output of the second exclusive-OR circuit. Or the previous state A clock phase detector comprising a mask circuit for determining whether to hold the signal, and a loop filter which receives an output from the clock phase detector as an input, and generates and outputs an APC voltage by suppressing its noise component. And a voltage-controlled oscillator that outputs the sampling clock whose oscillation frequency is controlled by the APC voltage to the A / D converter.

Further, another clock synchronization circuit according to the present invention comprises:
An AND circuit that performs an AND operation on the sampling clock output from the voltage controlled oscillator and an output of the second exclusive OR circuit, and outputs the operation result; The exclusive-OR circuit has a data input, an output of the AND circuit has a clock input, and a flip-flop circuit that outputs the clock phase information.

According to the present invention, two consecutive symbols of data obtained by sampling an analog baseband signal with a sampling clock having a modulation rate by an A / D converter are converted into first and second symbols.
The data of two symbols are added by an adder and the most significant bit is output, thereby obtaining the polarity of the data at the middle point of the sampling interval when the value of two symbols is linearly interpolated. The phase information of the sampling clock is extracted from the relationship between the polarity of the data at the intermediate point and the polarity of the data at the original sampling point. Therefore, the zero-cross detection method can be performed without requiring the double speed operation of the A / D converter.

[0029]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram of a demodulator using QPSK, and FIG. 2 is a block diagram showing a configuration of a clock synchronization circuit according to a first embodiment of the present invention.

The demodulator of FIG. 1 includes analog multipliers 11 and 3
1, a low-pass filter (hereinafter abbreviated as LPF) 12,
32, A / D converters 10, 33, VCOs 40, 54
, A phase shifter 50, and a control unit 56.

Since the demodulator shown in FIG. 1 is for demodulating a quadrature-modulated received signal, an in-phase component (hereinafter referred to as I
Abbreviated as (In-phase) component. ) And quadrature components (hereinafter abbreviated as Q (Quadrature: quadrature) components).

The VCO 54 generates a local oscillator whose frequency is controlled by the control unit 56. The phase shifter 50 shifts the phase of the local oscillator from the VCO 54 by π / 2 and outputs it.

The analog multiplier 11 multiplies the local oscillator from the VCO 54 by the received signal. The LPF 12 passes only the low-frequency component of the output of the multiplier 11 and outputs the analog baseband signal 101.

The analog multiplier 31 performs multiplication between the received signal and the local oscillator shifted in phase by the phase shifter 50. The LPF 32 passes only the low-frequency component of the output of the multiplier 31 and outputs the same as an analog baseband signal.

The VCO 40 is controlled by an APC voltage 103 output from the control unit 56, and generates and outputs a sampling clock 102 having a frequency fs.

The A / D converter 10 samples the analog baseband signal 101 by the sampling clock 102 and outputs it as a Q component digital signal. The A / D converter 33 samples the analog baseband signal 101 output from the LPF 32 by using the sampling clock 102 and outputs it as an I-component digital signal.

The control unit 56 controls the digital signal of the Q component output from the A / D converter 10 or the A / D converter 33
The phase information is extracted from the I-component digital signal output from the VCO 40, and the frequency of the sampling clock 102 generated by the VCO 40 is controlled. The control unit 56 also controls the frequency of the local oscillator generated by the VCO 54, but has no direct relation to the operation of the present embodiment, and a description thereof will be omitted.

The LPF 12 allows only the low-frequency component of the output of the multiplier 11 to pass, and
01 is output.

As shown in FIG. 2, the clock synchronization circuit according to the present embodiment includes an A / D converter 10, a clock phase detector 20, a VCO 40, and a loop filter (LPF) 30.
It is composed of Here, the clock phase detector 2
0 and the LPF 30 are provided in the control unit 56.

In this embodiment, a clock synchronous circuit that controls the VCO 40 using the analog baseband signal 101 of the Q component will be described.
A clock synchronization circuit that controls the VCO 40 using the analog baseband signal of the I component output from the F32 can be similarly configured.

The clock phase detector 20 has an F / F 21,
22, an adder 23, and exclusive OR circuits 24, 25
And a mask circuit 28. The mask circuit 28 includes an AND circuit 26 and an F / F 27.

The F / F 21 operates with the sampling clock 102 having the frequency fs, and outputs a plurality of bits of the A / D converter 10 after delaying it by one symbol.
The F / F 22 has a sampling clock 10 having a frequency fs.
2, the F / F 21 outputs a plurality of bits after delaying by one symbol. Here, F / F2
Reference numerals 1 and 22 are actually provided with a plurality of F / Fs in parallel, and operate as shift registers.

The adder 23 adds the plurality of bits of the output of the F / F 21 and the plurality of bits of the output of the F / F 22 and outputs the MSB of the addition result. Exclusive OR circuit 24
Calculates the exclusive OR of the output of the adder 23 and the MSB of the output of the F / F 21 and outputs the calculation result.
The exclusive OR circuit 25 calculates the MSB of the output of the F / F 21.
And the exclusive OR of the output of the F / F 22 and the MSB, and outputs the operation result.

The AND circuit 26 is connected to the sampling clock 102 output from the VCO 40 and the exclusive OR circuit 2.
The logical product of the outputs of Nos. 5 and 5 is calculated and the calculation result is output. The F / F 27 receives the output of the exclusive OR circuit 24 as a data input, receives the output of the AND circuit 26 as a clock input, and outputs clock phase information.

The LPF 30 receives the output of the F / F 27 as input, generates an APC voltage 103 by suppressing its noise component, and outputs the generated APC voltage 103 to the VCO 40. Here, LPF3
0 can be constituted by either an analog circuit or a digital circuit. However, when the circuit is constituted by a digital circuit, its output is converted into an analog signal by a D / A converter and then the VCO 4
Supply 0.

A specific configuration example of the LPF 30 will be described with reference to FIG. FIG. 3A shows a case where the LPF 30 is realized by an analog lag-lead filter, and FIG. 3B shows a case where the LPF 30 is configured using a digital circuit.

The lag lead filter shown in FIG. 3A includes resistors 61 and 63 and a capacitor 62.

The digital circuit used in FIG. 3B includes digital multipliers 64 and 65, digital adders 66 and 68, and an F / F 67.

Here, α and β shown in FIG.
30 are parameters that determine the characteristics of the T.30. In both cases, noise components within the band are suppressed and output. Since the VCO 40 that generates the sampling clock 102 is an analog circuit, as shown in FIG.
When the PF 30 is constituted by a digital circuit, a D / A converter 69 for D / A converting the output of the digital circuit is provided.

Next, the operation of the clock synchronous circuit of the present embodiment will be described in detail with reference to the drawings.

The F / Fs 21 and 22 hold two symbols of data at Ts intervals (Ts = 1 / fs) sampled by the sampling clock 102 having the frequency fs. By adding the values of the two symbols by the adder 23 and outputting the MSB, the polarity of data obtained by linearly interpolating the two symbols can be obtained. Although the addition result itself is twice as large as the interpolated value, only the polarity is required here.
Does not need to be multiplied by a factor of two.

The exclusive OR circuit 25 makes a condition judgment for detecting the clock phase, and the F / F 21,
A waveform whose output at 22 has the opposite polarity is selected. Then, the exclusive OR circuit 24 determines whether the polarity of the interpolated value obtained by the adder 23 matches the polarity of the F / F 21 and the output of the exclusive OR circuit 24 becomes clock phase information.

The AND circuit 26 and the F / F 27 constitute a mask circuit 28, and the output of the exclusive OR circuit 25 is H
, The output of the exclusive OR circuit 24 is output as an APC value, and when the output of the exclusive OR circuit 25 is L, F
/ F27 holds the previous output value. AND circuit 26 and F
/ F27 is an example for realizing the above functions, and can be realized by other circuit configurations.

In the conventional clock synchronization circuit, clock synchronization can be established by the zero-cross detection method by performing double-speed sampling with the A / D converter. In the clock synchronization circuit of the present embodiment, the A / D converter 10 can establish clock synchronization similarly to the conventional clock synchronization circuit, even though the A / D converter 10 performs only sampling at the same speed as the modulation speed. The reason is that the modulation method is QP
The case of SK will be described below as an example.

In the zero-cross detection method, a condition that the two sampling data at the Ts interval have different polarities is necessary. Therefore, only the signal transition shown by the solid line in FIG. Looking at this waveform, FIG.
Outside the two optimal sampling phases indicated by arrows in (a) are curves, but the inside can be regarded as almost straight. Therefore, when the vicinity of the optimum sampling phase is sampled by the clock of fs, the data obtained by linearly interpolating the two sampled values is very close to the value sampled at the original intermediate point by the double speed clock. Therefore,
As shown in FIG. 4B, the phase characteristic output from the clock phase detector 20 is almost the same as the case where the double-speed sampled value is used.

The waveform shown in FIG. 4A is a schematic one, and other transitions exist in the actual eye pattern. However, since these appear above and below the waveform shown in FIG. In this case, there is no significant difference even if only the waveform shown in FIG. At a phase apart from the optimal sampling phase, the waveform between the two phases becomes a curve, and the difference between the interpolated value and the original intermediate value increases, but the intermediate value is no longer away from 0, so the probability of erroneous polarity is low. Can be used as clock phase information in the synchronization pull-in process. Once synchronization is established, sampling is performed only in the vicinity of the optimum phase, so that an error in phase information when the sampling phase difference is large does not matter.

When sampling is performed at the optimum phase,
The polarity of the sampling value is almost fixed even when C / N is poor. Since the interpolated value is near 0, the mark rate is 50%. Here, the mark rate is a rate at which the polarity is positive. At this time, the phase information output from the clock phase detector 20 has a mark ratio of 50%.
As shown in FIG. 4B, the average value is 0.

When sampling is performed at a phase slightly advanced from the optimum phase, the polarity of the sampled value is almost fixed even when C / N is poor. Then, the interpolated value is also apart from 0, and the polarity is almost fixed. At this time, the phase information output from the clock phase detector 20 has a negative average value as shown in FIG. 4B because the mark ratio is 50% or less.

When sampling is performed at a phase slightly later than the optimum phase, the polarity of the sampled value is almost fixed even when C / N is poor. Then, the interpolation value also deviates from 0, and the polarity is almost fixed. At this time, the phase information output from the clock phase detector 20 has a mark ratio of 50% or more, and therefore has a positive average value as shown in FIG. 4B.

As described above, even when sampling at the same speed as the modulation speed without using double-speed sampling and using an interpolated value as in the clock synchronous circuit of the present embodiment is shown in FIG. Phase vs. AP
The characteristic of the C value is obtained, and if the VCO 40 is controlled by the APC value, clock synchronization can be established.

(Second Embodiment) Next, a demodulation device according to a second embodiment of the present invention will be described.

FIG. 5 is a block diagram showing the configuration of the demodulation device according to the second embodiment of the present invention. The demodulator of the present embodiment is a quasi-synchronous detection type demodulator in which a local oscillator is asynchronous.

The demodulator of this embodiment is different from the demodulator of the first embodiment shown in FIG. 1 in that an EPS 57 is provided between the A / D converters 10 and 33 and the control unit 56. is there. In the present embodiment, the VCO 54 is not controlled by the control unit 56.

As in this embodiment, after A / D conversion, EP
Even if a zero-crossing detection type clock synchronization circuit is applied to a quasi-synchronous detection type demodulator that performs carrier wave synchronization in S, the data required for clock synchronization only needs to be data having the same speed as the modulation speed. Can be the modulation speed. Therefore, when a circuit is formed by CMOS, power consumption can be reduced by half, and a device having the same speed can cope with a higher modulation speed.

(Third Embodiment) Next, a demodulation device according to a third embodiment of the present invention will be described. FIG. 6 is a block diagram showing the configuration of the demodulation device according to the third embodiment of the present invention.

The demodulator of this embodiment is different from the demodulator of the second embodiment in FIG. 5 in that a roll-off filter (R) is provided between the A / D converters 10, 33 and the EPS 57, respectively.
OF) 34, 44 and a thinning circuit (DECIM) 35,
45 are provided.

Since the roll-off filters 34 and 44 are constituted by digital signal processing circuits, the roll-off filters 34 and 44 of the present embodiment perform A / D conversion with a clock four times or more. The clock synchronization circuit as described in the first embodiment can be applied by thinning out the subsequent data into data at intervals of Ts by the thinning circuits 35 and 45.

In the first to third embodiments, the QPS
Although the description has been made using the case where the K modulation scheme is used, the present invention is not limited to this, and the present invention can be similarly applied to a case where a multi-level QAM modulation scheme is used.

[0070]

As described above, according to the present invention, the A / D
A clock synchronization circuit of a zero-cross detection system can be configured without performing conversion at double speed. Therefore, there is no need to use an expensive A / D converter or EPS that operates at high speed, and the cost and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a demodulation device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock synchronization circuit used in the demodulation device of FIG.

3 is a circuit diagram when the LPF 30 in FIG. 2 is configured by an analog circuit (FIG. 3A) and a block diagram when the LPF 30 is configured by a digital circuit (FIG. 3B).

FIGS. 4A and 4B are diagrams for explaining an optimum sampling phase (FIG. 4A) and diagrams showing phase characteristics output from the clock phase detector 20 (FIG. 4B).

FIG. 5 is a block diagram illustrating a configuration of a demodulation device according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a demodulation device according to a third embodiment of the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional clock synchronization circuit.

8 is a circuit diagram of a condition determination circuit 70 in FIG.

FIG. 9 is a diagram illustrating a relationship between an eye pattern of an analog baseband signal 101 and a phase of a sampling clock 202;

[Explanation of symbols]

 Reference Signs List 10 A / D converter 11 Analog multiplier 12 Low-pass filter (LPF) 20 Clock phase detector 21, 22 Flip-flop circuit 23 Adder 24, 25 Exclusive OR circuit 26 Logical product circuit 27 Flip-flop circuit 28 Mask circuit 30 Loop filter (LPF) 31 Analog multiplier 32 Low-pass filter (LPF) 33 A / D converter 34 Roll-off filter (ROF) 35 Decimation circuit (DECIM) 40 Voltage-controlled oscillator 44 Roll-off filter (ROF) 45 Decimation circuit (DECIM) 50) phase shifter 51-53 flip-flop circuit 54 voltage controlled oscillator 56 control unit (CONT) 57 infinite phase shifter (EPS) 59 voltage controlled oscillator 60 frequency divider 61 resistor 62 capacitor 63 resistor 64, 65 digital multiplier 66Digital adder 67 Flip-flop circuit 68 Digital adder 69 D / A converter 70 Condition judgment circuit 91 Flip-flop circuit 92, 93 Exclusive OR circuit 94 Logical product circuit 95 Flip-flop circuit 101 Analog baseband signal 102 Sampling clock 103 APC voltage 110 A / D converter 120 Clock phase detector 128 Mask circuit 130 Loop filter (LPF) 140 Voltage controlled oscillator 202 Sampling clock

Claims (6)

[Claims] An A / D converter for sampling an analog baseband signal with a sampling clock having the same cycle as a symbol cycle and converting the analog baseband signal into a digital signal;
One of the digital signals converted by the / D converter
A first shift register for holding data for one symbol, a second shift register for holding data for one symbol output from the first shift register, an output of the first cyst register, An adder that adds the output of the second shift register and outputs the most significant bit of the operation result; a signal output from the adder;
A first exclusive OR circuit for calculating an exclusive OR with the most significant bit of the first shift register and outputting the result of the calculation; A second exclusive-OR circuit for calculating the exclusive-OR of the most significant bit of the second shift register and outputting the result of the calculation; and outputting the output of the first exclusive-OR circuit to the data. A clock phase detector comprising, as an input, a mask circuit for determining whether to output the data input or keep the previous state in accordance with the logic of the output of the second exclusive OR circuit; A loop filter that receives and outputs an output from a filter and generates and outputs an APC voltage by suppressing a noise component thereof; and a sampling clock whose oscillation frequency is controlled by the APC voltage. The clock synchronization circuit having a voltage controlled oscillator that outputs the serial A / D converter. 2. The AND circuit according to claim 2, wherein the mask circuit calculates a logical product of a sampling clock output from the voltage controlled oscillator and an output of the second exclusive OR circuit, and outputs the calculated result. A circuit; and an output of the first exclusive OR circuit as a data input;
2. The clock synchronization circuit according to claim 1, further comprising: a flip-flop circuit that receives an output of the AND circuit as a clock input and outputs the clock phase information. 3. The clock synchronization circuit according to claim 1, wherein said loop filter is a lag-lead filter. 4. The clock synchronization circuit according to claim 1, wherein said loop filter comprises a digital circuit and a D / A converter. 5. The clock synchronization circuit according to claim 1, further comprising an infinite phase shifter between said A / D converter and said clock phase detector. 6. The clock synchronization circuit according to claim 5, further comprising a roll-off filter and a thinning circuit between the infinite phase shifter and the clock phase detector.