TW202301827A - Method and system for clock and data recovery - Google Patents

Abstract

The present invention provides a method and system for clock and data recovery, which provides at least one data information signal and at least one sampling signal. Generates a sampling clock based on default data in the data information signal and the sampling signal. Then, a plurality of recovery processes are executed in sequence, and each recovery process includes the following steps: sampling the data information signal by using the sampling clock, to obtain a response data; and according to the recovery data, restoring a recovery clock as the next sampling clock for the next recovery process. Finally, based on all the recovery data, a serial data is restored. Therefore, under a stable and simple structure, the present invention sequentially restores the entire serial data like a domino and restores all corresponding clocks at the same time.

Description

Method and system for clock and data recovery

The present invention relates to a clock and data recovery technology, in particular to a method and system for clock and data recovery.

For some receivers that strictly require low power consumption and low heat generation or devices without batteries, such as biomedical implantable chips, environmental monitoring systems and Internet of Things, etc., these devices need a demodulator to receive data, however The demodulator accounts for a large proportion of the power consumption of the entire system, so reducing the power consumption of the demodulator has become an important topic for improving system power consumption performance. The demodulator uses two modulation methods: non-return-to-zero (NRZ) and phase-shift keying (PSK).

Traditional serial links mostly use NRZ signals for data transmission, plus 8B/10B coding methods to maintain the DC balance of modulation signals. However, the NRZ clock data restoration circuit needs to use high-power phase-locked loops (PLL) to restore the clock first, and then use the restored clock to sample the modulated signal to restore data. The high-frequency oscillation in the phase-locked loop Passive components such as the inductance of the circuit breaker, the resistors and capacitors in the loop filter not only have a large area, but also consume a lot of power. In addition, the use of 8B/10B encoding will reduce the effective data transmission rate by 20%. PSK modulation signals use different carrier clocks to represent data, such as binary PSK (BPSK) and quadrature PSK (QPSK). Since PSK itself has the characteristic of DC balance, the transmission data does not need to be encoded by 8B/10B first, and the effective data transmission rate can reach 100%.

BPSK uses 180-degree phase difference and orthogonal signals to represent the data of 0 and 1. 0 and 1 are respectively at the positive and negative ends of the X-axis of the coordinate diagram. Figure 1A and Figure 2A show the symbols on the constellation diagram of BPSK and QPSK signals and the waveform corresponding to each symbol. Each clock cycle is called a symbol, and BPSK includes two symbols of 0 and 1, as shown in Figure 1B. QPSK includes four symbols representing 00, 01, 11, and 10 in four quadrants. QPSK can double the data transmission rate with the same bandwidth as BPSK. The Costas loop is the most concise traditional QPSK demodulator architecture. This architecture includes two parallel phase-locked loops, which are the I branch and the Q branch. As shown in Figure 2B, the two branches have a 90-degree phase difference. The common The implementation scheme is to first generate twice the carrier frequency by the oscillator, and then generate two signals of the same frequency with a phase difference of 90 degrees through the digital quadrature signal generator, which has the following disadvantages: (1) High power consumption, because the oscillator operating frequency It is twice the carrier frequency, which not only increases the difficulty of circuit design, but also is not suitable for low-power applications because of the large power consumption; (2) Due to the stability of the phase-locked loop, the data transmission rate will be limited by the phase-locked loop Stability; (3) The circuit complexity is high, because the phase-locked loop is a relatively complex feedback system; and (4) Large area, low frequency of biomedical application, large loop filter takes up a lot of area.

U.S. Patent Publication No. 20170317871 proposes an improved OQPSK demodulator architecture, which uses a delay line to delay the OQPSK signal, then multiplies the original signal and filters components higher than the carrier frequency to obtain data, and then uses the restored data and the original The OQPSK signal is used to recover the clock pulse, and the oscillator and loop filter are omitted in the overall structure, which can reduce power consumption and chip area. But this improved OQPSK demodulator has the following disadvantages: (1) The data transmission rate is low. This OQPSK encoding does not include all the data conversion paths in the constellation diagram, for example, the data in the second and fourth quadrants cannot be converted, resulting in a decrease in the effective data rate. (2) Since the data in the second and fourth quadrants cannot be converted, in order to ensure the normal operation of the demodulator, an additional encoding/decoding circuit must be used to convert the data in the second and fourth quadrants into data in other quadrants through calculation, so it is necessary Pay for the area and power consumption of the extra encoding circuit.

Therefore, the present invention proposes a method and system for clock and data recovery to effectively solve the above-mentioned problems. The specific structure and its implementation will be described in detail below:

The main purpose of the present invention is to provide a method and system for clock and data recovery, which utilizes phase-shift keying (PSK) technology, can restore a piece of data according to the principle of preset clock, and then use the recovered data to restore the sampling time The next segment of the pulse, and use the sampling edge in the next sampling clock segment to sample the signal again to restore the next data. Repeat this step to restore all the data and the corresponding clock in sequence.

Another object of the present invention is to provide a method and system for clock and data recovery, which uses a delay-locked loop to provide various PSK delay signals, including BPSK, QPSK, 8PSK, etc., because the delay-locked loop is a first-order feedback system, and Compared with the complex phase-locked loop, the delay-locked loop is not only quite stable, but also has a simple structure and low power consumption.

Another object of the present invention is to provide a method and system for clock and data recovery. The decision-making circuit is composed of a D-type flip-flop and a phase rotator, and the phase rotator is a multiplexer, so the structure is simple. Both analog circuits and digital circuits can be implemented.

Another object of the present invention is to provide a method and system for clock and data recovery. Its overall structure only includes delay-locked loops and decision-making circuits, and does not require low-frequency filters and other huge passive components, such as capacitors, inductors, and oscillators. , phase-locked loop, etc., so the overall area is small, the manufacturing cost is low, and it can be operated under low supply voltage.

In order to achieve the above object, the present invention provides a method for clock and data recovery, including the following steps: providing at least one first type of delayed signal as a data information signal and at least one second type of delayed signal as a clock information signal; The clock information signal and a default data generate a segment of the sampling clock; execute multiple recovery processes in sequence, and each recovery process includes the following steps: use a sampling edge of the segment of the sampling clock to sample the data information signal , to obtain a reply data; and according to the reply data and the clock information signal, restore a segment under the sampling clock for use in the next reply process; and combine all the reply data to restore a series of data.

According to an embodiment of the present invention, after the sampling edge of the sampling clock samples the data information signal, at least one sub-data is respectively output, and the sub-data constitutes the reply data.

According to the embodiment of the present invention, the sub-data is 0 or 1, and the reply data composed of the sub-data is binary data.

According to the embodiment of the present invention, one rising edge of the sampling clock is used as the sampling edge to sample the data information signal, and after obtaining the reply data, the reply data is used to restore the rising edge of the next section of the sampling clock to repeat The data information signal is sampled to obtain the next reply data.

According to an embodiment of the present invention, the serial data includes a synchronous signal, and the default clock is obtained from the synchronous signal.

The present invention further provides a clock and data recovery system, comprising: a delay-locked loop generating at least one first-type delayed signal as a data information signal and at least one second-type delayed signal as a clock information signal; and a The decision-making circuit is electrically connected to the delay-locked loop, wherein the decision-making circuit generates a segment of the sampling clock according to a preset data and timing information signal, executes a plurality of reply processes in order to obtain all the reply data, and restores a series of data, wherein each recovery process includes the following steps: using a sampling edge of a segment of the sampling clock, sampling the data information signal to obtain a recovery data; and restoring the sampling clock according to the recovery data and the clock information signal The sampled edge of the next fragment for use in the next recovery process.

According to the embodiment of the present invention, the decision-making circuit further includes at least one D-type flip-flop, which respectively receives the data information signal, uses the sampling edge of the sampling clock to sample the data information signal, and outputs at least one sub-data respectively, and the sub-data consists of Reply to the information.

According to the embodiment of the present invention, the decision circuit further includes a phase rotator, the clock information signal generated by the delay-locked loop is used as the input signal of the phase rotator, and the reply data output by the D-type flip-flop is used as the phase The selection signal of the rotator is processed by the phase rotator to synthesize and output the next segment of the sampling clock, and at the same time provide the sampling edge of the next segment of the sampling clock to the D-type flip-flop for sampling.

According to an embodiment of the present invention, the phase rotator is a multiplexer.

According to an embodiment of the present invention, the delay locked loop and the decision circuit are applied to a quarter phase-shift keying (QPSK) modulated signal.

The present invention provides a method and system for recovering clock and data. Using phase-shift keying (PSK) technology, a piece of data can be restored according to the principle of preset clock, and then the restored data can be used to restore the sampling time. The next segment of the pulse, and use a sampling edge of the sampling clock segment to sample the signal again to restore the next piece of data. Repeat this step to restore all the data and the corresponding clock in sequence. The invention does not need complex circuits and huge passive components, not only has stable data transmission, but also has the advantages of low power consumption, small area, and low cost.

Please refer to Fig. 3 and Fig. 4 at the same time, wherein Fig. 3 is a flow chart of the method for clock and data recovery, and Fig. 4 is a circuit block diagram using BPSK as an example in the system of clock and data recovery of the present invention. . The clock and data recovery system 20 of the present invention includes a delay locked loop 22 and a decision circuit 24 . A delay locked loop (DLL) 22 is used to generate at least one delayed signal of the first type as a data information signal and at least one delayed signal of the second type as a clock information signal and provide them to the decision circuit 24 . Taking the BPSK shown in Figure 3 as an example, there is one data information signal BPSK(t) and one clock information signal; if taking the QPSK shown in Figure 5 as an example, the two data information signals are respectively the first and the second Two delay signals, the two clock information signals are the third and fourth delay signals respectively, and so on, this mode can be extended to 8PSK, 16PSK...etc. The second, third, and fourth delay signals are delay signals of the first delay signal, and the delay time is designed by the user. Since the delay-locked loop 22 is a first-order feedback system, the signal output is quite stable. The decision-making circuit 24 is responsible for realizing the flow of the method in Fig. 3, which is described in detail as follows.

The system 20 of timing and data recovery receives a series of data, which is included in a packet. First, in step S10, at least one first-type delayed signal and at least one second-type delayed signal are generated by a delay-locked loop (delay locked loop, DLL) 22 and output to the decision circuit 24, including the first-type delayed signal as data information signal, and the second type of delayed signal is used as clock information signal. The following steps S12 - S20 are the calculation process in the decision circuit 24 . In step S12, the decision-making circuit 24 generates a segment of the sampling clock according to the clock information signal and a preset data. Assuming that the sampling clock is divided into multiple segments, one segment is usually one cycle, and only the sampling clock can be restored at a time. a fragment. In step S14, use a sampling edge of the sampling clock segment to sample the data information signal to obtain a reply data. Furthermore, each packet has a synchronization pattern at the beginning, allowing the receiving end to lock the carrier frequency and phase, so the data of this synchronization signal is known, and this synchronization pattern can be used in the present invention to obtain Preset clock to sample and restore data. Usually this sync signal is a series of zeros. Next, as described in step S16 , the recovery data obtained after sampling is used to restore a clock, and this clock is the next segment of the sampling clock, which will be used for sampling in the next recovery process. Then repeat steps S14~S16, use a sampling edge of the last sampling clock segment to sample the data information signal, and then restore the next segment of the sampling clock after obtaining the recovered data, and use the newly restored sampling clock segment Used for the next sampling of the data information signal. In step S18, it is judged whether all the data have been restored, if not, then return to step S14 to continue the reply process until step S18 judges that all data have been restored, and finally in step S20 the complete serial data and the corresponding clock are obtained, The corresponding clock is formed by restoring each segment of the sampling clock one by one.

The decision circuit 24 further includes at least one D-type flip-flop, such as the D-type flip-flop 242 in the BPSK embodiment of FIG. The data information signal is sampled, and the reply data can be output. In addition, the decision circuit 24 further includes a phase rotator 244, which is a multiplexer. The input signal of the phase rotator 244 is provided by the delay locked loop 22 as a third delayed signal or a fourth delayed signal input, and the third and fourth delayed signals are both delayed signals of the first delayed signal. In addition, the reply data output by the D-type flip-flop 242 is also provided to the phase rotator 244 as a selection signal of the phase rotator 244 . After multiplex processing by the phase rotator 244, a segment of the sampling clock can be synthesized, which will be fed back to the D-type flip-flop 242 at the same time as the output, for the D-type flip-flop 242 to sample and obtain the next group Reply to the information.

For example, after the D-type flip-flop 242 obtains the preset data according to the synchronization signal, the phase rotator 244 generates the first sampling clock segment according to the preset data and the clock information signal. Then the D-type flip-flop 242 uses the sampling edge of the first sampling clock segment to sample the data information signal to obtain the first reply data. Next, the phase rotator 244 uses the first reply data and the clock information signal to restore the second sampling clock segment. Next, the D-type flip-flop 242 uses the sampling edge of the second sampling clock segment to sample the data information signal to obtain the second reply data. The phase rotator 244 uses the second recovered data to restore the segment of the third sampling clock. The D-type flip-flop 242 then uses the sampling edge of the third sampling clock segment to sample to obtain the third reply data... and so on, the entire series of data can be restored sequentially like pushing dominoes, and restored at the same time corresponding to all clocks.

Taking Fig. 5 as an example again, it is a circuit block diagram of the present invention taking QPSK as an example. The decision circuit 14 further includes a first D-type flip-flop 142 and a second D-type flip-flop 144, which respectively receive the first delay signal and the second delay signal provided by the delay-locked loop 12, and use the preset clock pulse to The first delayed signal and the second delayed signal are sampled, and two sub-data in the reply data can be respectively output, such as I data and Q data as shown in the figure, and the I data and Q data can form a group reply data. Taking the QPSK modulator as an example, the I data is 0 or 1, and the Q data is 0 or 1. The I data and the Q data form two-digit binary data, including four symbols such as 00, 01, 11, and 10.

If it is a BPSK modulator, there is only one D-type flip-flop, and one sub-data is output. If it is an 8PSK modulator, there are three D-type flip-flops, which output three sub-data to form three-digit binary data as reply data. By analogy, the reply data composed of all sub-data is binary data.

In addition, the decision circuit 14 further includes a phase rotator 146, which is a multiplexer. The input signal of the phase rotator 146 is the clock information signal provided by the delay locked loop 12, including a third delayed signal or a fourth delayed signal, and the third and fourth delayed signals are both delayed signals of the first delayed signal. In addition, the I data and Q data output by the first and second D-type flip-flops 142 and 144 are also provided to the phase rotator 146 as selection signals for the phase rotator 146 . After being multiplexed by the phase rotator 146, a segment of the sampling clock can be synthesized and fed back to the first and second D-type flip-flops 142 and 144 at the same time as the output for the first and second D-type flip-flops. Type flip-flops 142, 144 for sampling to obtain the next set of reply data.

For example, the first D-type flip-flop 142 and the second D-type flip-flop 144 obtain preset data according to the synchronization signal, and provide the phase rotator 146 with data. The phase rotator 146 generates the first sampling clock segment according to the preset data and the clock information signal provided by the delay locked loop 12 . Then the first D-type flip-flop 142 and the second D-type flip-flop 144 use a sampling edge of the first sampling clock segment to sample the data information signal to obtain the first reply data. Then, the phase rotator 146 uses the first reply data and the clock information signal to restore the second sampling clock segment. Next, the first D-type flip-flop 142 and the second D-type flip-flop 144 use the sampling edge of the second sampling clock segment to sample the data information signal to obtain the second reply data. The phase rotator 146 uses the second recovered data to restore the segment of the third sampling clock. The first D-type flip-flop 142 and the second D-type flip-flop 144 then use the sampling edge of the third sampling clock segment to sample to obtain the third reply data... and so on, it can be like pushing dominoes The entire serial data is restored sequentially, and all corresponding clocks are restored at the same time.

In addition to being applicable to the BPSK architecture in FIG. 4 and the QPSK architecture in FIG. 5 , the present invention can also be applied to an 8PSK architecture based on the same principle, and even to a 16PSK architecture by analogy.

In the present invention, the delay time of the delay signal can be defined by the user. It should be noted that the data can be sampled only at the rising edge or falling edge of the clock, which is called the sampling edge in the present invention. In the embodiment of the present invention, the rising edge is used to sample the data, as shown in FIG. 5, the upward arrow is the rising edge of the clock. Assuming that a QPSK modulator is used and the synchronization signal of the known data is 00, the definition of its clock is shown in Figure 2A and Figure 2B. 00 is sin waveform, 01 is cos waveform, 11 is -sin waveform, 10 is -cos waveform. Since the sin waveform is falling, it cannot be sampled. Therefore, in order to move the falling edge to the specified position to become a rising edge, the first data needs to delay the clock signal by 7T/8 and reverse it, so that a sampling clock can be generated at the 3T/8 position in the first cycle rising edge. Please refer to Figure 7, which shows that when the data is 00, the clock needs to be delayed by 7T/8 and reversed. Under this premise, the corresponding data 01 needs to be delayed by 5T/8, 11 needs to be delayed by 7T/8, and 10 needs to be delayed by 5T/8 and reversed. According to the setting of the delay signals corresponding to these symbols, the delay-locked loop 12 has predefined how many clock pulses the outputted first delayed signal, the second delayed signal, the third delayed signal and the fourth delayed signal should be delayed respectively. For example, when the clock signal encountered is a sin waveform, it must be delayed by 7T/8 and reversed; when the clock signal encountered is a cos waveform, it must be delayed by 5T/8, and so on.

與

進行取樣，得到第一組回復資料(I、Q)。接著將第一組回復資料作為相位旋轉器146的選擇控制訊號，適當的切換第三延遲訊號

或第四延遲訊號

輸出，即可合成出取樣時脈的下一個片段，且此取樣時脈片段的上升緣位於下一個符號的3T/8處。重複上述的動作，用時脈上升緣對

與

取樣以得到第二組回復資料，再用第二組回復資料還原出取樣時脈的下一個片段的上升緣。以此類推，整個時脈與資料回復的過程就如同推骨牌，利用上一筆資料來還原當前的時脈，並用此時脈還原當前的資料，不斷重複此演算法的迴圈，即可將整個串列資料依序還原。 Therefore, after the delay-locked loop 12 is designed on the premise of the above-mentioned definition of delay time, the calculation flow of the decision-making circuit 14 is: when the first preset clock is delayed by 7T/8 and reversed, the rising edge is at 3T/8 position, at this time you can separately

and

Sampling is performed to obtain the first set of reply data (I, Q). Then use the first group of reply data as the selection control signal of the phase rotator 146, and appropriately switch the third delay signal

or the fourth delayed signal

output, the next segment of the sampling clock can be synthesized, and the rising edge of the sampling clock segment is located at 3T/8 of the next symbol. Repeat the above action, use the rising edge of the clock to

and

Sampling to obtain a second set of reply data, and then using the second set of reply data to restore the rising edge of the next segment of the sampling clock. By analogy, the entire clock and data recovery process is like pushing dominoes. Use the last data to restore the current clock, and use this pulse to restore the current data. Repeat the cycle of this algorithm continuously to restore the entire Serial data is restored sequentially.

與

取樣（圖中第五行

與第六行

的第一個黑點為取樣位置），就可分別得到I分支與Q分支的第一筆I資料和Q資料，第一筆I資料和Q資料組成第一回復資料。接著，依據第一回復資料選擇適當的延遲訊號，即可在第二個週期時間內的3T/8處又產生一個取樣時脈的上升緣。當同步訊號結束後，第一個取樣時脈的資料為01，此為cos訊號（如圖中第二行時脈QPSK(t)的虛線所圈出的波形），因此延遲5T/8後使時脈上升緣落在3T/8處，並進行取樣（圖中第五行

與第六行

的第四個黑點為取樣位置）。以此類推，重複上述動作，依據不同的回復資料，將其波形作適當的延遲，即可得到取樣時脈的下一片段。 FIG. 8 is a timing diagram of data transition under the QPSK framework using the system and method of the present invention. In a preferred embodiment, the synchronous signal is a series of continuous data 000000 as an example, after being modulated by QPSK, it becomes a small segment of carrier clock, as shown in the first row of QPSK(t). Since the first data is 00, it is necessary to delay the carrier clock by 7T/8 (as shown in the third row of clock QPSK (t-7T/8)), and reverse it (as shown in the fourth row of clock rclk ), which can generate a rising edge of the sampling clock at 3T/8 in the first data period (the sampling clock obtained by using the synchronous signal, such as the first rising edge of the fourth line clock rclk in the figure Rising edge at 3T/8 in the first data period). Then, use the rising edge of the sampling clock to respectively

and

Sampling (the fifth line in the figure

with the sixth row

The first black dot is the sampling position), the first I data and Q data of the I branch and the Q branch can be obtained respectively, and the first I data and Q data form the first reply data. Then, by selecting an appropriate delay signal according to the first reply data, another rising edge of the sampling clock can be generated at 3T/8 in the second cycle time. When the synchronization signal ends, the data of the first sampling clock is 01, which is a cos signal (the waveform circled by the dotted line of the clock QPSK(t) in the second row in the figure), so after a delay of 5T/8, use The rising edge of the clock falls at 3T/8 and is sampled (the fifth line in the figure

with the sixth line

The fourth black point is the sampling position). By analogy, the above actions are repeated, and the waveform is appropriately delayed according to different reply data, so as to obtain the next segment of the sampling clock.

In the embodiment of Figure 8, the symbol 00 is preset as a sin waveform, so the original packet needs to be phase-delayed after being modulated by QPSK, and converted into the clock QPSK (t-7T/8) of the third row, and then reversed To the clock rclk of the fourth row, the rising edge of the clock is obtained, which is the sampling clock required by the present invention. If the symbol 00 is defined as a -sin waveform, then the first line of QPSK(t) is the sampling clock. Therefore, the synchronization signal can be directly sampled as the default clock, or it needs to be delayed and reversed before it can be sampled as the default clock, depending on how the user defines the symbol.

FIG. 9 is a timing diagram of data transition under the BPSK architecture using the system and method of the present invention. In a preferred embodiment, the synchronization signal is a series of continuous data 000 as an example, which becomes a small segment of carrier clock pulse after BPSK modulation, as shown in the first row of BPSK(t). Since the first data is 0, it is necessary to delay the carrier clock by 3T/4 (as shown in the second row of clock BPSK(t-3T/4)), that is, 3T/4 in the first data period A rising edge of a sampling clock is generated at (this is a sampling clock obtained by using a synchronous signal, as shown in the figure, the first rising edge of the clock rclk in the third row rises at 3T/4 in the first data period edge). Then, use the rising edge of the sampling clock to sample BPSK(t) (the first black dot in the first row of BPSK(t) in the figure is the sampling position), and the first reply data can be obtained. Then, according to the first reply data, another rising edge of the sampling clock can be generated at 3T/4 of the second cycle time. When the synchronization signal ends, the data of the first sampling clock is 1 (the waveform circled by the dotted line of the clock BPSK(t) in the first row in the figure), which is a falling edge, so after a delay of 3T/4, it takes Reverse (the rising edge of the clock rclk selected by the dotted circle in the third line in the figure), and then sample (in the first line of BPSK(t) in the figure, the black dot in the cycle selected by the dotted line is the sampling position) . By analogy, the above actions are repeated, and the waveform is appropriately delayed according to different reply data, so as to obtain the next segment of the sampling clock.

To sum up, the clock and data recovery method and system provided by the present invention use the known clock to sample the data information signal, and after obtaining a reply data, use the reply data to restore a sampling clock fragments. Then use the sampling edge of the sampling clock segment to sample the data information signal to obtain the next reply data, and then restore the next segment of the sampling clock. Continuously repeating the steps of sampling to obtain recovered data and restoring to obtain sampling clock segments, the entire series of data can be sequentially restored like pushing dominoes, and the corresponding clock can be restored at the same time. The present invention has the following advantages: 1. Absolutely stable. Because the delay-locked loop is a first-order feedback system, it has the advantage of absolute stability compared with the phase-locked loop. 2. High data transfer rate. Because the circuit of the present invention is stable, the effective data rate can reach the theoretically fastest transmission speed of QPSK. 3. Low power consumption. Since the present invention does not require the use of power-hungry oscillators and phase-locked loops, power consumption can be significantly reduced. 4. The architecture is simple and easy to implement, no matter using digital or analog circuits. 5. Can operate at low supply voltage. If the system of the present invention is used in a wireless power transmission system, the lower the supply voltage required by the system, the easier it is to increase the transmission distance and improve the application range. If implemented in digital circuits, reducing the supply voltage can greatly reduce both dynamic power consumption and static power consumption. 6. Small area and low cost. Since the system of the present invention does not need to use low-frequency filters and bulky passive components, such as capacitors and inductors, the area can be reduced and the manufacturing cost can be reduced. 7. Excellent resistance to process, voltage and temperature variation (PVT variation). The delay line can use the delay-locked loop to control its delay time. When the delay-locked loop is locked, the delay time can resist PVT variation and improve circuit reliability.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Therefore, all equivalent changes or modifications based on the features and spirit described in the scope of the application of the present invention shall be included in the scope of the patent application of the present invention.

10: Clock and data recovery system 12: Delay locked loop 14: Decision circuit 142: The first D-type flip-flop 144: The second D-type flip-flop 146:Phase rotator 20: Clock and data recovery system 22: Delay locked loop 24: Decision circuit 242: D-type flip-flop 244:Phase rotator

Figure 1A is a constellation diagram of Binary PSK (BPSK). FIG. 1B is a schematic diagram of the waveform corresponding to I data and Q data of binary phase shift keying. FIG. 2A is a constellation diagram of Quad PSK (Quarter PSK, QPSK). FIG. 2B is a schematic diagram of the four-bit phase-shift keying waveform corresponding to I data and Q data. Fig. 3 is a flow chart of the method for clock and data recovery of the present invention. Fig. 4 is a circuit block diagram of the clock and data recovery system of the present invention, taking BPSK as an example. Fig. 5 is a circuit block diagram of the clock and data recovery system of the present invention, taking QPSK as an example. Fig. 6 is a schematic diagram of data sampling from the rising edge of the clock after inverting the phase of the present invention. Figure 7 is a schematic diagram of the delay times and sampling clocks corresponding to the four waveforms when QPSK is taken as an example in the present invention Fig. 8 is a timing chart of data transition using QPSK as an example in the system and method of the present invention. Fig. 9 is a timing diagram of data transition using BPSK as an example in the system and method of the present invention.

Claims (12)

A method for clock and data recovery, comprising the following steps: providing at least one delayed signal of the first type as the data information signal and at least one delayed signal of the second type as the clock information signal; generating a sampling clock segment according to a preset data and the at least one clock information signal; Execute multiple reply processes in sequence, and each reply process includes the following steps: sampling the at least one data information signal using a sampling edge of the segment of the sampling clock to obtain a reply data; and According to the reply data and the clock information signal, restore the next segment of the sampling clock for use in the next reply process; and Combine all the reply data to restore a series of data. The clock and data recovery method as described in Claim 1, wherein after the sampling edge of the sampling clock samples the at least one data information signal, at least one sub-data is respectively output, and the at least one sub-data constitutes the reply data. The method for replying clock and data as described in Claim 2, wherein the at least one sub-data is 0 or 1, and the reply data composed of the at least one sub-data is binary data. The method for clock and data recovery as described in Claim 1, wherein one rising edge of the sampling clock is used as the sampling edge, and the at least one data information signal is sampled, and the reply is used after obtaining the reply data The data restores the rising edge of the next segment of the sampling clock, so as to repeatedly sample the at least one data information signal to obtain the next reply data. The method for clock and data recovery as described in Claim 1, wherein the serial data includes a synchronization signal, and the default clock is obtained from the synchronization signal. A clock and data recovery system, comprising: a delay-locked loop generating at least one delayed signal of the first type as the data information signal and at least one delayed signal of the second type as the clock information signal; and A decision-making circuit, electrically connected to the delay-locked loop, wherein the decision-making circuit generates a segment of a sampling clock according to a preset data and the at least one clock information signal, and executes a plurality of reply processes in order to obtain all replies Data, to restore a series of data, wherein, each of the recovery process includes the following steps: Sampling the at least one data information signal by using a sampling edge of a segment of the sampling clock to obtain a reply data; and restoring the next segment of the sampling clock according to the reply data and the clock information signal Sample edges for use in the next recovery process. The clock and data recovery system as described in Claim 6, wherein the decision-making circuit further includes at least one D-type flip-flop, respectively receiving the at least one data information signal, using the sampling edge of the sampling clock to at least one A data information signal is sampled, and at least one sub-data is respectively outputted, and the at least one sub-data constitutes the reply data. The clock and data recovery system as described in Claim 7, wherein the decision circuit further includes a phase rotator, and the at least one clock information signal generated by the delay-locked loop is used as an input signal of the phase rotator, And the reply data output by the at least one D-type flip-flop is used as the selection signal of the phase rotator, after being processed by the phase rotator, the next segment of the sampling clock is synthesized and output, and the sampling clock The sampling edge of the next segment is provided to the at least one D-type flip-flop for sampling. The system for clock and data recovery as claimed in claim 8, wherein the phase rotator is a multiplexer. The clock and data reply system as described in Claim 7, wherein the at least one sub-data is 0 or 1, and the reply data composed of the at least one sub-data is binary data. The clock and data reply system as described in Claim 6, wherein the decision-making circuit uses a rising edge of the sampling clock as the sampling edge to sample the at least one data information signal, and obtain the reply data , and then use the reply data to restore the rising edge of the next segment of the sampling clock to repeatedly sample the at least one data information signal to obtain the next reply data. The clock and data recovery system as described in claim 6, wherein the delay-locked loop and the decision-making circuit are applied to a four-bit phase-shift keying (quarter phase-shift keying, QPSK) modulated signal.

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