JP2003309543A - Clock restoring circuit and data receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the amplitude of a limit cycle signal is large and the jitter dependence of feedback group characteristics is also large in conventional data receiving circuits (clock restoring circuits). <P>SOLUTION: The clock restoring circuit comprises a boundary detecting circuit 202 for detecting a boundary of an input signal in response to a first signal CLKb, and controls a timing of the first signal according to the detected boundary to conduct clock restoration. The clock restoring circuit is configured to have boundary detection timing varying means 207 and 208 for giving a variation portion to the first signal to vary dynamically a boundary detection timing in the boundary detecting circuit, and a variation reducing means 209 for reducing phase variation occurred at a restored clock, according to dynamic change of the boundary detection timing varied by the boundary detection timing varying means. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

The present invention relates to high-speed signal transmission between a plurality of LSI chips or between a plurality of elements and circuit blocks in one chip, or between a plurality of boards and between a plurality of enclosures. In particular, the present invention relates to a clock recovery circuit and a data reception circuit using a feedback loop type clock signal generation circuit.

In recent years, the performance of parts constituting computers and other information processing equipment has been greatly improved. For example, SRAM (Static Random Access Memory) and DR.
The performance improvement of semiconductor memory devices such as AM (Dynamic Random Access Memory), processors, or switch LSIs is remarkable. As the performance of the semiconductor memory device, the processor, etc. is improved, the system performance cannot be improved unless the signal transmission speed between each component or element is improved. Specifically, for example, a speed gap between a storage device (memory) such as SRAM and DRAM and a processor (between LSIs) tends to become larger and larger. In recent years, this speed gap hinders improvement in performance of the entire computer. It is becoming. Further, due to high integration and large size of semiconductor chips, the signal transmission speed between elements and circuit blocks in the chip has become a major factor limiting the performance of the chip. Furthermore, the signal transmission speed between the peripheral device and the processor / chipset is also a factor that limits the performance of the entire system.

By the way, generally, in high-speed signal transmission between circuit blocks or chips, or in a high-speed signal transmission inside a housing, a clock for determining "0" and "1" of data is generated (restored) on the receiving circuit side. Is being done. The recovered clock is adjusted by the feedback circuit inside the circuit so that the recovered signal is always received within a certain phase range with respect to the received data so that correct signal reception is always performed. In this way, it is necessary to recover the clock and determine the data by using the recovered clock.
ecovery). This CDR is the most important element for high-speed data reception, and various methods have been studied. Further, there is a strong demand to provide a data receiving circuit (clock recovery circuit) capable of high-speed and accurate signal transmission using CDR.

[0004]

2. Description of the Related Art In recent years, it is necessary to increase the signal transmission rate per pin in order to cope with an increase in the amount of data transmission between LSIs and boards or between enclosures. This is also to avoid an increase in the cost of the package and the like due to the increase in the number of pins. As a result, recently, the signal transmission speed between LSIs exceeds 2.5 Gbps and is extremely high value such as 10 Gbps or higher (high-speed signal transmission).
Is required.

For example, in order to increase the speed of signal transmission between LSIs, it is necessary that the receiving circuit operates (performs data detection and determination) with respect to the signal sent thereto at a timing that is somewhat accurate. Conventionally, there is known a method of providing a clock recovery circuit (CDR) using a feedback loop type clock signal generation circuit in a signal reception circuit in order to generate a clock (internal clock) of such timing.

That is, in order to realize CDR, an internal clock for receiving data is generated, the phase of the internal clock is compared with the phase of the data, and the feedback of adjusting the phase of the internal clock based on the phase comparison result. A circuit is used.

FIG. 1 is a block diagram showing an example of a conventional data receiving circuit, which is configured as a 4-way × 2 type interleave circuit using CDR. Also,
FIG. 2 is a diagram showing the timing of each signal in the data receiving circuit of FIG.

In FIG. 1, reference numerals 110 to 113 are data judgment units (data judgment flip-flops), 120 to 123 are boundary detection units (boundary detection flip-flops), and 131 and 132 are data and boundary. The conversion circuit is shown. Further, reference numeral 141 is a data determination clock generation circuit, 142 is a boundary detection clock generation circuit, and 105 is a phase difference digital code conversion circuit (PDC:
Phase to Digital Converter) and 106 are digital filters. Further, reference numeral DIL indicates a data input line, DCL indicates a data determination clock line, BCL indicates a boundary detection clock line, and DFL and BFL indicate data and boundary feedback lines.

As shown in FIG. 1, the conventional data receiving circuit includes, for example, a data input line DIL for transmitting data of 10 Gbps and four data determination units 11.
0 to 113 and four boundary detection units 120
Connected to ~ 123 inputs, each corresponding to 2.5 GHz
It is designed to be captured by the clock.

That is, as shown in FIGS. 1 and 2, the data judgment units 110 to 113 have 2.5 GHz output from the data judgment clock generation circuit 141.
And the phases differ by 90 ° (for example, 45 °, 13
Four-phase clocks CLKd0-CLKd3 (of 5 °, 225 ° and 315 ° phase) are provided, 45 °, 13 respectively.
The input data is taken in at phase timings of 5 °, 225 °, and 315 °, and the received data DT0 to DT3 are output to the conversion circuit 131. The conversion circuit 131 is 2.5 GHz
4-bit received data DT0-D synchronized with the clock
The T3 is converted into 32-bit data (DT [31: 0]) synchronized with the 312.5 MHz clock and output to the phase difference digital code conversion circuit 105, and the received data (DT [31: 0]) is next Output to the stage circuit (internal circuit).

Further, the boundary detection units 120-1
In FIG. 23, four-phase clocks CLKb0 to CLKb3 having a phase difference of 90 ° (for example, phases of 0 °, 90 °, 180 ° and 270 °) at 2.5 GHz which is the output of the boundary detection clock generation circuit 142 are provided. The supplied boundary data of the input data is detected at the phase timings of 0 °, 90 °, 180 °, and 270 °, and the boundary detection data BT0 to BT3 are output to the conversion circuit 132. The conversion circuit 132 converts the 4-bit boundary detection data BT0 to BT3 synchronized with the 2.5 GHz clock into 32-bit data (BT [31: 0]) synchronized with the 312.5 MHz clock to convert the phase difference digital code. Output to the conversion circuit 105. Here, the four-phase clock CLK output from the data determination clock generation circuit 141 is output.
d0 to CLKd3 and boundary detection clock generation circuit 14
The four-phase clocks CLKb0 to CLKb3 which are the outputs of 2 have a phase difference of 45 °.

The phase difference digital code conversion circuit 105 includes
The input reception data DT [31: 0] and the boundary detection data BT [31: 0] are compared and processed to obtain 7-bit phase difference information (PDCODE [6: 0], -32 to +3.
2) is output to the digital filter 106. The digital filter 106 feeds back the 6-bit precision data determination phase control code to the data determination clock generation circuit 141 via the feedback line DFL, and the 6-bit precision boundary detection phase control code via the feedback line BFL. Is fed back to the boundary detection clock generation circuit 142. In FIG. 2, the data capture timing (rising timing) of the boundary detection clocks CLKb0 to CLKb3 is the boundary position of the input data. In FIG. BT3 is "1,1,0,1, ..."
It is drawn assuming that.

FIG. 3 is a block diagram showing a data determination clock generation circuit 141 (boundary detection clock generation circuit 142) in the data reception circuit of FIG.

As shown in FIG. 3, the data determination clock generation circuit 141 includes a mixer circuit 1411 and a digital-to-analog converter (DAC: Digital to A).
nalogConverter) 1413. The mixer circuit 1411 uses a clock signal (four-phase clock) and DA.
The output of C1413 is received, and a set of signals having a phase difference of 90 degrees is synthesized from the four-phase clock to generate each intermediate phase. Then, the signal having the intermediate phase is added with the phase shift due to the weight (the output of the DAC 1413) to generate a clock, and the data determination clock CLKd is generated.
(CLKd0, CLKd1, CLKd2, CLKd3) are generated. The boundary detection clock generation circuit 142
Similarly, the boundary detection clock CLKb
(CLKb0, CLKb1, CLKb2, CLKb3) are generated.

The mixer circuit 1411 controls the phase based on the current value representing the weight, and the weight for changing the phase is determined by the data judgment units 110 to 113 and the boundary detection unit in the phase difference digital code conversion circuit 105. From the outputs of 120 to 123, the input data (or the input clock) from the outside and the internal clock (the data determination clock CLKd and the boundary detection clock CLKb) are digitally compared in phase, and the phase is controlled via the digital filter 106. It is supplied to the DAC 1413 as a code (phase control code for data determination).

The DAC 1413 receives the constant current and the phase control code, converts the variable phase weight into a current and supplies the current to the mixer circuit 1411. The phase of the clock CLKd (CLKb) is changed by the amount of change in the current.

Here, the clock recovery circuit (CDR) is
This is the name given by paying attention to the point that the clock for data determination is restored from the input signal. Also, in the data receiving circuit, the data determination circuit determines the data of the input signal using the restored clock and outputs it. It was given paying attention to the points.

In the data receiving circuit (clock recovery circuit) shown in FIGS. 1 and 2, the boundary detection units 120 to 123 used for phase comparison (clock recovery).
If the same circuit as the data determination units 110 to 113 is used, systematic phase shift does not occur, clock recovery can be performed with high accuracy, and phase comparison sensitivity can be increased.

FIG. 4 is a diagram showing an example of latch timing of data and boundary in an input signal.

In FIG. 4, reference numerals DATA [i-2],
DATA [i-1], DATA [i], DATA [i + 1] are, for example, data determination units 110, 111, 112, 11
3 shows the ideal timing of the data latched (judged) by BDATA [i-2], BDATA [i-
1], BDATA [i], BDATA [i + 1] indicate ideal timings of boundaries latched (detected) by the boundary detection units 120, 121, 122, 123, for example.

In the conventional data receiving circuit (clock restoration circuit) described with reference to FIGS. 1 to 4, since the input / output characteristics of the phase difference digital code conversion circuit 105 have a large non-linearity, clock restoration is required. The feedback action to be performed includes limit cycle oscillations inherent in so-called bang-bang control. Further, in the conventional data receiving circuit, there is a disadvantage that the band of the circuit changes depending on the magnitude of the jitter included in the clock for recovering the clock.

[0022]

FIG. 5 is a block diagram showing an example of a data receiving circuit according to the related art, and FIG. 6 is a diagram for explaining the operation of the data receiving circuit shown in FIG.

As is clear from the comparison between FIG. 5 and FIG.
The related art data receiving circuit shown in FIG. 5 is provided with a variation generation circuit 107 and an adding circuit 108 in addition to the conventional data receiving circuit shown in FIG.

As shown in FIG. 5, the data receiving circuit of the related art adds the phase control code (phase control code for boundary detection) from the digital filter 106 to the feedback line BFL which is fed back to the clock generation circuit 142 for boundary detection. The circuit 108 is inserted, and the output of the fluctuation amount generation circuit 107 is applied to the boundary detection clock generation circuit 142 via the addition circuit 108. That is, by supplying the phase control code, which is the output of the digital filter 106, to the boundary detection clock generation circuit 142 including the output of the fluctuation generation circuit 107, the boundary detection timing is changed as shown in FIG. BTi is the original boundary detection timing B
The time τ is effectively shifted before and after the position of Ti0. Here, the fluctuation generation circuit 107 is supplied with an internal reference clock RCLK of 312.5 MHz, for example.

The phase difference digital code conversion circuit 105
The leading / lagging of the phase is determined by several consecutive bit cells, and the sum is used as the output of the phase difference digital code conversion circuit 105. In each of these judgments, a different time (skew) τ is intentionally given to the judgment timing at each judgment, and the skew τ is changed from the original boundary judgment timing.
Only different timing positions will be determined.

FIG. 7 is a block diagram showing an example of the phase difference digital code conversion circuit in the data receiving circuit of FIG.

As shown in FIG. 7, the phase difference digital code conversion circuit 105 includes a timing judgment circuit 151 and a phase difference information output circuit 152. The timing determination circuit 151 receives the 32-bit reception data DT [31: 0] and the boundary detection data BT [31: 0] output from the conversion circuits 131 and 132 and determines the timing. Specifically, for example, data determination is performed using the reception data DATA [i-1], DATA [i] and the boundary detection data BDATA [i]. In addition,
The phase difference information output circuit 152 collects the timing determination results of each bit, adds the determination results of 32 bits, and outputs the result as phase difference information.

FIG. 8 is a diagram for explaining the operation of the phase difference digital code conversion circuit shown in FIG. 7, and FIG. 9 is a diagram for explaining the phase difference information output from the phase difference digital code conversion circuit shown in FIG. FIG.

In FIG. 8A, the latch timing (BTi) by the internal clock (for example, the boundary detection clock CLKb) is ideal latch timing (BTi0).
8B shows the case (EARLY) earlier than
The case where the latch timing by the internal clock is later than the ideal latch timing (LATE) is shown, and FIG. 8C shows the data (DATA [i-
1)) and the next data (DATA [i]), no transition (“0” → “1” or “1” → “0”) appears, that is, when the same data continues (NO TRANSITIO
N) is shown.

As shown in FIGS. 8 and 9, for example, the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [1, 0, 1] or [0, 1]. , 0] ([1, 0, 1] in FIG. 8A)
The timing determination circuit 151 determines that the latch timing by the internal clock is earlier than the ideal latch timing (EARLY), and the code CODEi
As [1: 0], “1,1” (that is, “−1”: delay the phase of the data determination clock) is output to the phase difference information output circuit 152. Also, the received data DATA [i
-1], DATA [i] and boundary detection data BDAT
When A [i] is [1,0,0] or [0,1,1] (corresponding to [1,0,0] in FIG. 8B), the timing determination circuit 151 uses the internal clock for latching. It is determined that the timing is later than the ideal latch timing (LATE), and the code CODEi [1: 0] is "0, 1".
(That is, “+1”: advance the phase of the data determination clock) is output to the phase difference information output circuit 152.

In other cases, that is, the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [i] are [0,0,0] or [1,1,1].
1] (corresponding to [1, 1, 1] in FIG. 8C) or when the boundary detection timing is the boundary position, the received data DATA [i-1], DATA [i] and the boundary detection data BDATA [ When i] is [0,0,1] or [1,1,0], the timing determination circuit 151
“0,0” (that is, “0”) is output to the phase difference information output circuit 152 as the code CODEi [1: 0].

The timing judgment circuit 151 performs the above processing on all bits (DT [31: 0] and BT [31:
0]) for each bit k (where k = 0)
31 to 31) code CODEk [1: 0] is supplied to the phase difference information output circuit 152. Then, the phase difference information output circuit 152 adds all the codes CODEk [1: 0] of each bit k and outputs the phase difference information PDCODE [6: 0] to the digital filter of the next stage. Therefore, the phase difference information P
DCODE [6: 0] has a value within the range of -32 to +32. The phase difference information PDCODE becomes −32 when all the 32 bits are “−1”, and the phase difference information PDCODE becomes +32 when all the 32 bits are included. Is "+1".

FIG. 10 is a diagram for explaining an example of the operation of the data receiving circuit shown in FIG. 5. FIG. 10 (a) shows a nonlinear input / output characteristic, and FIG. 10 (b) shows a stepwise input. It shows the output characteristics.

The above-described related art data receiving circuit of FIG. 5 is different from the conventional data receiving circuit in the variation generating circuit 10.
By adding 7 and the adder circuit 108, the boundary detection timing is shifted before and after the original position. Then, the phase difference digital code conversion circuit 1
In 05, the number of consecutive bit cells is used to determine the lead / lag of the phase and the sum is used as the phase difference information (phase comparison output). .., skew is intentionally given to the determination timing for each determination.

Concretely, for example, the skew is-(3/2) τ,-(1 /
2) τ, (1/2) τ, (3/2) τ. At this time, the input / output characteristic is 4 as shown in FIG.
It has a step-like characteristic composed of steps. This is a conventional single-step nonlinear input / output characteristic (Fig. 1
0 (see (a)) can be interpreted as having a linear input / output characteristic. In this example, 4 hours
A nearly linear characteristic is obtained over the range of τ. And
If the value of 4τ is set to the same level as the maximum value of the jitter input to this system, the phase difference digital code conversion circuit 105 can always be operated in a linear range.

As described above, the related art data receiving circuit shown in FIG. 5 modulates the boundary detection timing before and after the original position so that the phase difference digital code conversion circuit determines whether the phase is advanced or delayed. To have linearity in the input / output characteristics, that is, by substantially linearizing the input / output relationship of the boundary detection units 120 to 123 (phase difference digital code conversion circuit 105), the characteristic characteristic of the nonlinear system is obtained. In addition to reducing the amplitude of the limit cycle signal, the jitter dependence of the feedback loop characteristic is reduced to improve the predictability of the characteristic of the data receiving circuit (clock recovery circuit).

However, in the related art data receiving circuit described with reference to FIGS. 5 to 10, when the boundary detection timing is modulated before and after the original position, the output of the phase difference digital code conversion circuit 105 is A component that fluctuates at the same frequency used for the modulation appears.
The data determination clocks CLKd0 to CLKd3 (CLK are supplied to the data determination units 110 to 113).
The fluctuation component is also included in the phase of d), and this fluctuation component becomes phase noise.

Specifically, for example, SONET (Synchron
ous Optical Network: North American standard for optical communication)
Jitter that occurs in a circuit that performs high-speed signal transmission of about 10 Gbps is specified to be within 10 ps pp, and phase noise that occurs when phase modulation for linearization affects an internal clock (clock for data determination). Is required to be minimized.

In view of the problems of the above-described conventional data receiving circuit, the present invention reduces the amplitude of the limit cycle signal and the jitter dependence of the feedback loop characteristic to improve the predictability of the characteristic, and , The purpose is to minimize the phase noise that occurs when the phase modulation for linearization affects the internal clock. Further, the present invention provides
Another object is to increase the resolution of the phase control code generation circuit and reduce the quantization noise of the clock.

[0040]

According to a first aspect of the present invention, a boundary detection circuit for detecting a boundary of an input signal according to a first signal is provided, and the boundary detection circuit detects the boundary according to the detected boundary. Boundary detection timing for controlling the timing of a first signal to restore a clock, wherein the boundary detection timing is dynamically changed by giving a variation to the first signal and dynamically changing the boundary detection timing in the boundary detection circuit. A clock restoration circuit is provided, which comprises: a varying unit; and a variation reducing unit that reduces a variation in a phase occurring in a restored clock in response to a dynamic change in the boundary detection timing by the boundary detection timing varying unit. .

Further, according to the first aspect of the present invention, a data judgment circuit for judging the data of the input signal by the data judgment clock, and a boundary detection circuit for detecting the boundary of the input signal by the boundary detection clock. A phase control code generating means for generating a phase control code by receiving outputs from the data determination circuit and the boundary detection circuit; and a boundary detection timing in the boundary detection circuit for giving a variation to the phase control code for boundary detection. Boundary detection timing varying means for dynamically changing, and a variation reducing means for reducing a variation in the phase generated in the data determination clock in response to a dynamic change in the boundary detection timing by the boundary detection timing varying means. Data reception times characterized by It is also provided.

According to a second aspect of the present invention, there is provided a clock recovery circuit having an internal clock generation circuit for receiving a first phase control code having a first bit number and generating an internal clock, A phase control code generating circuit for generating a second phase control code having a second number of bits larger than the number of bits, and a predetermined fluctuation pattern that fluctuates in a short time with respect to the second phase control code are added. And an addition processing unit that outputs the first phase control code corresponding to the first bit number, wherein the internal clock generation circuit effectively outputs the phase-controlled internal clock with the resolution of the second bit number. A clock recovery circuit is provided which is characterized in that it is generated.

According to the second aspect of the present invention, the first
A data determination clock generation circuit for receiving a first phase control code having the number of bits of 1 to generate a data determination clock, a data determination circuit for determining data of an input signal by the data determination clock, and a boundary detection clock. A boundary detection circuit for detecting a boundary of the input signal, and an output from the data determination circuit and the boundary detection circuit to generate a second phase control code having a second bit number larger than the first bit number. And a phase control code generating circuit that adds a predetermined fluctuation pattern that fluctuates in a short time to the second phase control code, and outputs the first phase control code corresponding to the first bit number. And a processing unit, wherein the data determination clock generation circuit effectively controls the phase with a resolution of the second number of bits. Data receiving circuit, characterized by generating the data decision clock is also provided.

FIG. 11 is a block diagram showing the principle configuration of the data receiving circuit (clock recovery circuit) according to the first embodiment of the present invention. In FIG. 11, reference numeral 201 is a determination circuit (data determination circuit), 202 is a phase comparison circuit (boundary detection circuit), 205 is a phase code generation circuit, and 207.
Is a fluctuation generation circuit, 208 is an addition circuit, 209 is a fluctuation removal circuit, 241 is a determination clock generation circuit (data determination clock generation circuit), and 242 is a phase comparison clock generation circuit (boundary detection clock generation circuit). )
Is shown.

As shown in FIG. 11, in the data receiving circuit (clock restoration circuit) according to the first embodiment of the present invention, the output of the phase code generation circuit 205 is passed through the fluctuation removal circuit 209 to be used as the determination clock generation circuit. 241 is supplied. That is, the input data is the determination circuit 20.
1 and the phase comparison circuit 202, and the determination circuit 20
1, the phase is compared with the judgment clock CLKd, and the phase comparison circuit 202 uses the phase comparison clock C.
The phase is compared with LKb. The outputs of the judgment circuit 201 and the phase comparison circuit 202 are supplied to the phase control code generation circuit 205, and the phase control code from the phase control code generation circuit 205 is supplied to the judgment clock generation circuit 241 via the fluctuation removal circuit 209. And fluctuation removal circuit 2
It is supplied to the phase comparison clock generation circuit 242 via 09 and the addition circuit 208.

The fluctuation generation circuit 207 is the phase comparison circuit 2
02 generates a variation for modulating the phase comparison timing before and after the original position. The variation from the variation generation circuit 207 is added by the addition circuit 208 to add the phase comparison clock generation circuit 242. To substantially linearize the input / output relationship of the phase comparison circuit 202. The fluctuation removing circuit 209 is provided with the phase control code generating circuit 2 superposed by the output (fluctuation) of the fluctuation generating circuit 207 added by the adding circuit 208.
This is for removing a periodic or aperiodic fluctuation pattern in the output of 05, and the fluctuation pattern is removed by utilizing the fact that the added value (fluctuation: amplitude or frequency) is known. Has become.

Here, the fluctuation eliminating circuit 209 is, for example,
It can be configured as a band elimination filter (notch filter) that removes the frequency component of the added fluctuation. Further, the notch filter may be realized by a normal analog band stop filter or a moving average filter in a cycle of a fluctuation component to be added. Then, the phase comparison circuit 202
By integrating one cycle of the output of the above, it is possible to completely remove the frequency component of the frequency of the added fluctuation, which is 1 time, 2 times, ..., M times. The fluctuation eliminating circuit 209 can also be configured as a part of a filter that processes the output of the phase control code generating circuit 205, for example.

Amount added by the adder circuit 208 (change amount)
Can control (dynamically control) a fluctuation pattern represented by its amplitude and frequency. The amount of addition required for linearization also depends on the magnitude of the phase fluctuation of the data, and by changing the amount of addition according to the magnitude of the phase fluctuation, it is possible to minimize the fluctuation of the output phase due to addition. Is.

FIG. 12 is a block diagram showing the principle configuration of a data receiving circuit (clock recovery circuit) according to the second embodiment of the present invention.

As shown in FIG. 12, in the data receiving circuit (clock restoration circuit) according to the second embodiment of the present invention, the adder circuit 300 is provided between the phase control code generation circuit 205 and the judgment clock generation circuit 241. And adder 3
00, a predetermined addition sequence (for example, a variation pattern “0 → 3 → 1 → 2 → 0 → ...” or “0 → 1 → 2 → 3 →
0 → ... ”) is added.

That is, the linearization (improvement of the phase discrimination ability) by adding the known variation pattern to the phase control code (output of the phase control code generation circuit 205) is performed on the output of the phase control code generation circuit 205. Is also possible. For example, when the phase control code generation circuit 205 is controlled by a digital code, the resolution of the phase control code generation circuit 205 determines the interval of phase values that can be output. However, as shown in FIG. 12, a known variation (for example, variation pattern “0 → 3 → 1”) in the phase control code (code having a resolution higher than that of the phase control code generation circuit 205: internal code n + 2 bit code).
"→ 2 → 0 → ..." or "0 → 1 → 2 → 3 → 0 → ..."), and only the upper bits (upper n bits) that can be decomposed by the determination clock generation circuit 241 in the resulting code are added. It is sent to the determination clock generation circuit 241. By averaging the resulting phases (filtering the fluctuation component), an output with the same resolution as the internal code (phase control code) can be obtained.

As described above, according to the first aspect of the present invention, the amplitude of the limit cycle signal is reduced, and
It is possible to reduce the jitter dependence of the feedback loop characteristic to improve the predictability of the characteristic, and to minimize the phase noise generated by the phase modulation for linearization affecting the internal clock. Further, according to the second aspect of the present invention, since the resolution of the phase control code generation circuit can be increased, it is possible to reduce the quantization noise of the clock. As a result, the timing margin of the receiving circuit is increased, and it is possible to provide a more stable data receiving circuit (clock recovery circuit) capable of high-speed operation.

[0053]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data receiving circuit (clock recovery circuit) according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 13 is a block diagram showing an embodiment of the data receiving circuit according to the present invention.
This is configured as an ay × 2 type interleave circuit.

In FIG. 13, reference numerals 10 to 13 are data judging units (data judging flip-flops),
20 to 23 are boundary detection units (boundary detection flip-flops), and 31 and 32 are data and boundary conversion circuits. Also,
Reference numeral 41 is a data determination clock generation circuit, 42 is a boundary detection clock generation circuit, 5 is a phase difference digital code conversion circuit, 6 is a digital filter, 7 is a fluctuation generation circuit, 8 is an addition circuit, and 9 is The fluctuation elimination circuit is shown. Further, reference numeral DIL indicates a data input line, DCL indicates a data determination clock line, BCL indicates a boundary detection clock line, and DFL and BFL indicate data and boundary feedback lines.

As is clear from the comparison between FIG. 13 and FIG. 5, the data receiving circuit of the present embodiment shown in FIG. 13 is further provided with the fluctuation eliminating circuit 9 in addition to the related art data receiving circuit shown in FIG. , The periodic or aperiodic fluctuation pattern in the output of the phase difference digital code conversion circuit 5 superimposed by the output (fluctuation) of the fluctuation component generation circuit 7 added by the addition circuit 8 is removed, and the phase for data determination is removed. The control code is supplied to the data determination clock generation circuit 41. Here, the fluctuation generation circuit 7 has, for example, 312.5 MHz.
Is supplied with the internal reference clock RCLK. In addition,
In this embodiment, the fluctuation detecting circuit 9 also removes the fluctuation pattern of the boundary detecting phase control code and supplies it to the boundary detecting clock generating circuit 42.

The fluctuation eliminating circuit 9 is a digitally synthesized band elimination filter, and is constituted so that the elimination frequency coincides with the frequency of the modulation signal. This band stop filter can be realized by using a known FIR filter technique. According to the data receiving circuit of the present embodiment,
The amplitude of the limit cycle signal is reduced, the jitter dependence of the feedback loop characteristic is reduced to improve the predictability of the characteristic, and the phase noise caused by the phase modulation for linearization affecting the internal clock is suppressed. be able to.

14 and 15 are diagrams for explaining the linearization processing in the data receiving circuit of FIG. In FIG. 14, reference numeral 1 denotes a data determination unit (data determination flip-flop), and 2 denotes a boundary detection unit (boundary detection flip-flop).

Similar to the data receiving circuit of the related art described with reference to FIGS. 5 to 10, also in the present embodiment, the boundary detecting unit 1 (10 to 13) is provided by the fluctuation generating circuit 7 and the adding circuit 8. The phase of the boundary detection clock CLKb (CLKb0 to CLKb3) to be supplied is changed to perform linearization. However, in the data receiving circuit of the related art described above, the skew (change in phase) is negative with respect to the original boundary timing.
(3/2) τ,-(1/2) τ, (1/2) τ, (3 /
2) In contrast to τ which is variable in an analog manner, in the present embodiment, the phase of the clock CLKb for boundary detection is within a range of, for example, 0.5 UI (Unit Interval: clock cycle on the data side). The average value of the phase information for one cycle is dynamically calculated by using eight steps as a reference.

Specifically, for example, the skew for one step is set to 0.0625 UI, and the input data and the data determination clock (CLKd) are set in the initial state when the power of the device (data receiving circuit) is turned on. Since the phase difference of is large, the linearization range is expanded to, for example, 12 stages (the linearization range is 0.75 UI: (1) side in FIG. 15),
It should be able to handle large jitter of input data. Then, when the apparatus is stable and the phase difference between the input data and the data determination clock becomes small, the linearization range is set to, for example, four stages (the linearization range is 0.25 UI: FIG.
(2 side in 5)). Thus, for example, the linearization range can be dynamically controlled by the initial state, the stable state, or the like (due to the phase difference between the input data and the data determination clock). Here, a state in which the phase difference between the input data and the data determination clock is large, such as the initial state when the power is turned on, is called an unstable state, and the device is stable and the phase difference between the input data and the data determination clock is small. The state in which it has become stable is called the stable state.

The slope (gain) of the variation used for linearization is steep ((3) side in FIG. 15) in the unstable state and gentle ((4) side in FIG. 15) in the stable state. As an alternative, it is possible to dynamically control the inclination of the variation. On the contrary, it is possible to keep the frequency characteristic of the loop constant by maintaining a constant proportional relationship between the phase difference (phase difference between the input data and the data determination clock) and the gain regardless of the linearization range. it can. When the slope (gain) of the fluctuation is dynamically changed, the proportional relationship between the phase difference and the gain is destroyed. For example,
In the stable state of the device where the phase difference between the input data and the data judgment clock is small, if the gain is increased more than necessary (that is, if the slope is steep), the tracking characteristic becomes excessive and jitter occurs in the data judgment clock. In some cases, it is not desirable because it is caused. Further, in the opposite case, that is, when the gain is too small, it may not be possible to follow the phase.

Further, one stage of skew (for example,
0.0625UI is set as a small value (for example, 0.05UI) in the unstable state and a large value (for example, 0.075UI) in the stable state, and the skew setting value for one step is set. Can also be controlled dynamically.

In the process of locking an internal clock (for example, a data judgment clock) to the input data, the time constant of the CDR loop is set to be short in the initial state and then changed to a longer time constant in the steady state. Due to
The time that the internal clock locks to the input data can be reduced. This means changing the cutoff frequency of the loop between the initial state and the steady state. That is,
If the time constant of the loop is short, the cutoff frequency is high, and if the time constant of the loop is long, the cutoff frequency is low. In this case, it is also possible to make the period of the fluctuation component added to the boundary detection phase control code given to the boundary detection clock generation circuit 42 variable, and to change the frequency of the fluctuation component to be added together with the change of the cutoff frequency. it can.

Further, the amplitude of the fluctuation component added to the boundary detection phase control code is made variable, and when the phase difference between the input data and the data judging clock is small, the fluctuation component amplitude is also controlled to be small. You can also At this time, the gain of the phase detector changes depending on the amplitude of the fluctuation added to the phase control code for boundary detection, but the parameters of the digital filter are automatically adjusted to control the frequency characteristics of the loop to be the same. May be.

The amplitude of the variation required for linearizing the phase detector is the magnitude of the input of the phase detector (that is, the phase difference between the input data and the boundary detection clock).
However, in the present embodiment, since linearization may be performed only in the range that covers the input range of phase detection, fluctuations of the clock phase due to fluctuations should be minimized by not giving fluctuations more than necessary. Is also possible.

FIG. 16 is a diagram showing an example of the output pattern of the variation generating circuit in the data receiving circuit of FIG. 13, FIG. 16 (a) shows an example of a triangular wave, and FIG. 16 (b) shows a zigzag wave. Shows an example of.

In the triangular wave shown in FIG. 16 (a), one cycle (3.2 ns × 8 = 15.6 ns) is composed of 8 steps where the time for one step is 1 / (312.5 MHz) = 3.2 ns. The frequency of the triangular wave is 312.5MHz / 8.
It becomes 39.1 MHz. In addition, the zigzag wave shown in FIG. 16 (b) has one cycle (3.2 ns × 2 = 6.4 ns) composed of two steps whose time is 3.2 ns.
The frequency of the zigzag wave is 312.5 MHz / 2 = 15
It becomes 6.25 MHz.

That is, the triangular wave shown in FIG.
When the code value is in the range of -2 to +2, for example, 0 → + 1 →
The pattern is + 2 → + 1 → 0 → -1 → -2 → -1 → 0 → ..., and the frequency of the fluctuation is 39.1 MHz. In addition, the zigzag wave shown in FIG.
When the code value is in the range of -4 to +4, for example, 0 → -4 →
+ 1 → -3 → + 2 → -2 → + 3 → -1 → + 4 → 0 → + 3
The pattern is such that the fluctuation frequency is 156.25 MHz, which is higher than the triangular wave, and therefore the fluctuation that appears in the data determination clock (internal clock) becomes smaller due to the low-pass characteristics of the feedback loop. There are advantages.

FIG. 17 is a block diagram showing an example of the fluctuation eliminating circuit in the data receiving circuit of FIG. 13, in the case where the fluctuation is a triangular wave as shown in FIG. 16 (a) (and FIG. 16 (b)). This is a configuration example of the fluctuation removing circuit 9 applicable to the case of the zigzag wave as shown in FIG.

As shown in FIG. 17, the fluctuation eliminating circuit 9
Is configured as a notch filter, and has eight stages of flip-flops 911 to 918 and a subtraction circuit 9 connected in series.
2, an adder circuit 93, a flip-flop 94, and a divider circuit 95. Flip-flops 911 to 918
Is, for example, sequentially fetched data with a clock of 312.5 MHz, and has eight stages of flip-flops 911 to 91.
8 is 3.2 ns (= 1 / (312.
Phase control code (phase control code for data determination) corresponding to a triangular wave that forms one cycle with 8 steps of 5 MHz))
To remove the fluctuations in. Here, the adder circuit 93 and the flip-flop 94 constitute an integrator circuit, and are for outputting a low frequency component in the initial state and at the time of lock. Is divided by the number 8 corresponding to the eight-stage flip-flops 911 to 918 and output.

FIG. 18 is a diagram for explaining the operation of the fluctuation eliminating circuit of FIG.

As is apparent from FIG. 18, the fluctuation eliminating circuit (notch filter) 9 shown in FIG. 17 can remove the triangular wave having the frequency of 39.1 MHz as shown in FIG. 16 (a). . Further, this fluctuation eliminating circuit 9 has a frequency of 15 as shown in FIG.
It can be seen that the 6.25 MHz zigzag wave can also be removed. For the zigzag wave having a frequency of 156.25 MHz, eight-stage flip-flops 911 to 91 are used.
It is possible to remove it by providing only two stages (corresponding to one cycle of the zigzag wave) or 2h stages (h is a positive integer: corresponding to h times one cycle of the zigzag wave) instead of 8. is there.

FIG. 19 is a block diagram showing another example of the fluctuation eliminating circuit in the data receiving circuit of FIG.
(A) shows the fluctuation elimination circuit as FIR (Finit-duration Impul)
se Response) shows a filter configured,
FIG. 19B shows the fluctuation elimination circuit which is configured by a moving average circuit.

As shown in FIG. 19A, the fluctuation eliminating circuit 9 may be composed of, for example, a known FIR filter composed of delay elements 961 to 963 and adders 971 to 974, or FIG. As shown in (b),
For example, a delay element (eg, flip-flop) 981
.About.983 and the averaging circuit 99, a known moving average circuit may be used. Here, FIG. 19 (a)
19 (b), and the number of stages of delay elements 961 to 963 and adders 971 to 974 in the FIR filter of FIG.
The number of stages of the delay elements 981 to 983 in the moving average circuit is defined in accordance with the fluctuation component to be removed (the output of the fluctuation component generation circuit 7 given via the addition circuit 8),
As a result, the fluctuation from the past one cycle to the present time is removed. Further, the FIR filter of FIG. 19A and the moving average circuit of FIG.
The variation of the triangular wave that constitutes one cycle in stages (and FIG.
The variation of the zigzag wave as shown in (b) can be removed. The fluctuation component of the zigzag wave is, for example, as the fluctuation elimination circuit 9, an FIR filter having one delay element (961) and two adders (971, 972), or one delay element (981) and an average. It can be eliminated by using a moving average circuit with a circuit (99).

FIG. 20 is a block diagram showing another example of the data receiving circuit according to the present invention.

As is clear from the comparison between FIG. 20 and FIG. 13 described above, the data receiving circuit of the present embodiment has the addition circuit 8
Is directly supplied with the output of the digital filter 6, and the output of the fluctuation eliminating circuit 90 (data determination phase control code) is
It is supplied only to the data determination clock generation circuit 41. It is necessary to supply the data determination clock generation circuit 41 with the data determination phase control code from which the variation pattern is removed by the variation removal circuit 90, but to the boundary detection clock generation circuit 42. This is because it is not always necessary to supply the boundary detection phase control code from which the fluctuation pattern has been removed by the fluctuation removing circuit 90.

This is because the fluctuation of the output of the digital filter 6 supplied to the adding circuit 8 is smaller than the amplitude of the output of the fluctuation generating circuit 7. The data receiving circuit shown in FIG. 20 has an advantage that the stability of the feedback is not impaired because the delay due to the fluctuation removing circuit 90 is removed from the feedback loop on the boundary detection side.

FIG. 21 is a block diagram showing still another example of the data receiving circuit according to the present invention, and FIG. 22 is a diagram for explaining the operation of the data receiving circuit of FIG.

As shown in FIG. 21, in the data receiving circuit of the present embodiment, the digital filter 600 generates a 6-bit precision phase control code and supplies it to the adder circuit 8 and also via the fluctuation eliminating circuit 900. And supplies the 8-bit precision phase control code to the adder circuit 80. That is, the digital filter 600 sends the phase control code having a higher resolution (eg, 8-bit accuracy) than the resolution (eg, 6-bit accuracy) of the data determination clock generation circuit 41 to the addition circuit 80 via the fluctuation removal circuit 900. Supply,
The adder circuit 80 adds the output (fluctuation amount) of the fluctuation amount generation circuit 70, and determines the upper 6 bits (6 bit precision) of the data control phase control code corresponding to the resolution of the data determination clock generation circuit 41. To the clock generating circuit 41 for clock. Further, the digital filter 600 is
The 6-bit precision phase control code is supplied to the adder circuit 8,
The boundary detection phase control code to which the output of the fluctuation amount generation circuit 7 is added by the addition circuit 8 is supplied to the boundary detection clock generation circuit 42. This is the same as in each of the above-described embodiments. The triangular wave shown in a) and Fig. 1
This will be performed using the zigzag wave shown in 6 (b).
The fluctuation generation circuits 7 and 70 have, for example, 31
An internal reference clock RCLK of 2.5 MHz is supplied.

Specifically, as shown in FIG. 22A, for example, the fluctuation eliminating circuit 900 (digital filter 6
When the 8-bit precision phase control code which is the output of (00) is "-1", the addition circuit 80 causes the fluctuation amount generation circuit 7
When a cyclic fluctuation pattern of "0 → 1 → 2 → 3 → 0 → ..." which is an output of 0 is added, a phase control code (data determination phase) of 6-bit precision output from the addition circuit 80 is added. The control code is (-1 + 0 + 0) by rounding operation.
+0) /4=-0.25 (average code). That is, it is understood that the 8-bit precision phase control code "-1" becomes the 6-bit precision phase control code "-0.25".

Further, specifically, as shown in FIG. 22B, for example, when the 8-bit precision phase control code output from the fluctuation eliminating circuit 900 (digital filter 600) is "-3", When the addition circuit 80 adds the cyclic variation pattern “0 → 1 → 2 → 3 → 0 → ...”, which is the output of the variation generation circuit 70, the addition circuit 80
The 6-bit precision phase control code, which is the output of, becomes (−1-1-1 + 0) /4=−0.75 (average code) by rounding operation. That is, the 8-bit precision phase control code "-3" is converted to the 6-bit precision phase control code "-".
It turns out that it will be 0.75 ”.

As described above, the value of the data determination phase control code supplied to the data determination clock generation circuit 41 is an 8-bit precision code whose average value is the output of the fluctuation removal circuit 900 (digital filter 600). Will show the same variation pattern as.

FIG. 23 is a diagram showing an example of the variation added to the data determination phase control code in the data receiving circuit of FIG.

As described above, the fluctuation component (output of the fluctuation component generation circuit 70) added to the data determination phase control code by the addition circuit 80 is, for example, "0 → 1" as shown in FIG. → 2 → 3 → 0 → ... ”is a periodic fluctuation pattern (sawtooth wave pattern), and this fluctuation pattern is, for example,“ 0 → 3 → 1 → 2 → as shown in FIG. It may be a periodic variation pattern (harmonic pattern) such as “0 → ...”.

The fluctuation pattern "0 → 3" shown in FIG.
"→ 1 → 2 → 0 → ..." has a higher frequency component than the variation pattern "0 → 1 → 2 → 3 → 0 → ..." shown in FIG. 23A, that is, each variation is added 8 The 6-bit precision phase control code (the input signal of the data determination clock generation circuit 41) obtained by rounding the bit precision phase control code is shown in the harmonic variation pattern shown in FIG. The frequency component is higher than that of the sawtooth wave fluctuation pattern shown in FIG. As a result, the fluctuation amount in the signal averaged by the LPF (low-pass filter: integrating circuit 415 by CR; see FIG. 24) of the data determination clock generation circuit 41 is the harmonic fluctuation pattern shown in FIG. Is smaller than the sawtooth wave fluctuation pattern shown in FIG. 23A, the harmonic wave fluctuation pattern of FIG. 23B is preferable. It goes without saying that the output of the fluctuation amount generating circuit 70 can be variously modified depending on the number of bits of the applied phase control code and the like.

FIG. 24 is a block diagram showing an example of a data determination clock generation circuit in the data reception circuit of FIG.

As shown in FIG. 24, the 6-bit precision data determination phase control code output from the adder circuit 80 is the DAC in the data determination clock generation circuit 41.
413 and the CR integration circuit 415.
Is supplied to the mixer circuit 411 via. Then, the phase control code for data determination is averaged by the time constant of the integrating circuit 415 by this CR, and the resolution of the phase actually output becomes equivalent to 8 bits. Therefore, in the data receiving circuit of the present embodiment, it is possible to improve the resolution of the digitally controlled clock generation circuit (data determination clock generation circuit 41) and reduce the quantization error in digital control. .

In addition, the data receiving circuit of the embodiment shown in FIG. 21 has a fluctuation amount generating circuit 70 and an adding circuit 80 in addition to the data receiving circuit of FIG. Is made into 8 bits.

FIG. 25 is a block diagram showing still another example of the data receiving circuit according to the present invention.

The data receiving circuit of the embodiment shown in FIG.
A variation generation circuit 70 and an addition circuit 80 are added to the data reception circuit of FIG. 13, and the data determination phase control code output from the digital filter 6 is converted into 8 bits. As described above, in the first mode (see FIG. 11 and the like) and the second mode (see FIG. 12 and the like) of the present invention, one or both of them may be appropriately applied to configure the data receiving circuit. it can.

(Supplementary Note 1) A boundary detection circuit for detecting the boundary of the input signal according to the first signal is provided, and the timing of the first signal is controlled according to the detected boundary to restore the clock. And a boundary detection timing changing means for dynamically changing the boundary detection timing in the boundary detection circuit, and a boundary detection timing changing means by the boundary detection timing changing means. A clock recovery circuit, comprising: a fluctuation reducing unit configured to reduce a fluctuation of a phase generated in a recovered clock according to a dynamic change of timing.

(Supplementary Note 2) In the clock restoration circuit according to Supplementary Note 1, the boundary detection timing variation means generates a variation component and a variation component from the variation component generation circuit. A clock recovery circuit comprising: an adder circuit that adds to a signal.

(Supplementary Note 3) In the clock recovery circuit according to Supplementary Note 2, the fluctuation generating circuit generates a triangular wave-like fluctuation that increases and decreases stepwise over one cycle of fluctuation. Clock recovery circuit.

(Supplementary Note 4) In the clock recovery circuit according to Supplementary Note 2, the fluctuation component generating circuit generates a zigzag fluctuation component that changes while repeating increase and decrease a plurality of times within one cycle of fluctuation. Clock recovery circuit.

(Supplementary Note 5) In the clock recovery circuit according to Supplementary Note 3 or 4, the fluctuation generating circuit generates a fluctuation over a wide phase range in an unstable state and a narrow phase in a stable state. A clock recovery circuit characterized by generating a variation over a range.

(Supplementary Note 6) In the clock recovery circuit according to Supplementary Note 3 or 4, the fluctuation generating circuit generates a large gain fluctuation in an unstable state and a small gain fluctuation in a stable state. A clock recovery circuit characterized by generating a minute.

(Supplementary Note 7) In the clock recovery circuit according to Supplementary Note 3 or 4, the fluctuation generating circuit generates a fluctuation in which one unit time is increased in an unstable state, and in a stable state. Is a clock recovery circuit characterized by generating a variation by reducing the unit time of one step.

(Supplementary Note 8) In the clock restoration circuit according to Supplementary Note 2, the fluctuation reducing means outputs the signal related to the restored clock over one cycle or a plurality of cycles of the fluctuation output by the fluctuation generating circuit. A clock recovery circuit characterized by averaging.

(Supplementary Note 9) In the clock recovery circuit according to Supplementary Note 8, the fluctuation reducing means is a notch filter,
A clock recovery circuit, which is an FIR filter or a moving average circuit.

(Supplementary Note 10) In the clock recovery circuit according to Supplementary Note 1, the boundary detection circuit includes a plurality of boundary detection units, and each of the boundary detection units detects a boundary according to each boundary detection clock. A clock recovery circuit characterized by performing.

(Supplementary Note 11) A clock restoration circuit having an internal clock generation circuit for receiving a first phase control code having a first bit number and generating an internal clock, the second clock signal having a second bit number larger than the first bit number. Corresponding to the first number of bits by adding a predetermined variation pattern that fluctuates in a short time with respect to the second phase control code And an addition processing unit for outputting the first phase control code, wherein the internal clock generation circuit effectively generates an internal clock whose phase is controlled by the resolution of the second number of bits. Clock recovery circuit.

(Supplementary Note 12) In the clock recovery circuit according to Supplementary Note 11, the addition processing means adds “0 → 1 → 2 → 3 →” to the 8-bit precision phase control code from the phase control code generating circuit. A clock restoration circuit characterized by adding a periodic variation pattern of "0 → ...".

(Supplementary note 13) In the clock recovery circuit according to supplementary note 11, the addition processing means adds "0 → 3 → 1 → 2 →" to the 8-bit precision phase control code from the phase control code generation circuit. A clock restoration circuit characterized by adding a periodic variation pattern of "0 → ...".

(Supplementary Note 14) In the clock recovery circuit according to Supplementary Note 11, the internal clock generation circuit includes a plurality of data judging units, and each of the data judging units outputs data in accordance with each data judging clock. A clock recovery circuit characterized by making a determination.

(Supplementary Note 15) A data judging circuit for judging data of an input signal by a data judging clock, a boundary detecting circuit for detecting a boundary of the input signal by a boundary detecting clock, the data judging circuit and the boundary detecting circuit. Phase control code generating means for receiving an output from the circuit and generating a phase control code;
A variation is given to the boundary detection phase control code,
Boundary detection timing changing means for dynamically changing the boundary detection timing in the boundary detection circuit, and reduction of a phase change generated in the data determination clock in response to a dynamic change in the boundary detection timing by the boundary detection timing changing means. And a fluctuation reducing means for controlling the fluctuation.

(Supplementary Note 16) In the data receiving circuit according to supplementary note 15, the boundary detection timing variation means is configured to generate a variation component and generate a variation component from the variation component generation circuit for detecting the boundary. A data receiving circuit, comprising: an addition circuit that adds the phase control code.

(Supplementary Note 17) In the data receiving circuit according to Supplementary Note 16, the phase difference between the data of the input signal and the data determination clock and the gain of the feedback loop are:
A data receiving circuit, which maintains a constant proportional relationship regardless of the amplitude of the fluctuation generated by the fluctuation generating circuit.

(Supplementary Note 18) In the data receiving circuit according to Supplementary Note 16, the fluctuation generating circuit allows the output pattern to be variable.

(Supplementary Note 19) In the data receiving circuit according to Supplementary Note 18, the fluctuation generating circuit allows the frequency of a certain output pattern to be variable in an initial state and a steady state. .

(Supplementary Note 20) In the data receiving circuit according to Supplementary Note 16, the fluctuation component generating circuit generates a triangular-wave-like fluctuation component that increases and decreases stepwise over one cycle of fluctuation. Data receiving circuit.

(Supplementary Note 21) In the data receiving circuit according to Supplementary Note 16, the fluctuation generation circuit generates zigzag fluctuations that change while repeating increase and decrease a plurality of times within one cycle of fluctuation. Data receiving circuit.

(Supplementary Note 22) In the data receiving circuit according to supplementary note 20 or 21, the fluctuation generating circuit generates a fluctuation over a wide phase range in an unstable state and a narrow phase in a stable state. A data receiving circuit characterized by generating a variation over a range.

(Supplementary Note 23) In the data receiving circuit according to Supplementary Note 20 or 21, the fluctuation generation circuit generates a large gain fluctuation in an unstable state and a small gain fluctuation in a stable state. A data receiving circuit characterized by generating a minute.

(Supplementary Note 24) In the data receiving circuit according to Supplementary Note 20 or 21, the fluctuation generating circuit generates a fluctuation by increasing one unit time in an unstable state, and in a stable state. Is a data receiving circuit characterized by generating a fluctuation amount by reducing the unit time of one step.

(Supplementary Note 25) In the data receiving circuit according to supplementary note 16, the fluctuation reducing means outputs the signal related to the recovered clock over one cycle or a plurality of cycles of the fluctuation output by the fluctuation generating circuit. A data receiving circuit characterized by averaging.

(Supplementary note 26) In the data receiving circuit according to supplementary note 25, the fluctuation reducing means is a notch filter, an FIR filter or a moving average circuit.

(Supplementary note 27) A data judging clock generating circuit for receiving a first phase control code having a first bit number and generating a data judging clock, and data for judging data of an input signal by the data judging clock. A determination circuit, a boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock, and a second bit larger than the first number of bits by receiving outputs from the data determination circuit and the boundary detection circuit. A phase control code generation circuit for generating a number of second phase control codes, and a predetermined fluctuation pattern that fluctuates over a short period of time with respect to the second phase control code are added to correspond to the first number of bits. An addition processing unit that outputs a first phase control code, and the data determination clock generation circuit effectively A data receiving circuit, wherein a data determination clock whose phase is controlled with a resolution of 2 bits is generated.

(Supplementary note 28) In the data receiving circuit according to supplementary note 27, the addition processing means adds "0 → 1 → 2 → 3 →" to the 8-bit precision phase control code from the phase control code generating circuit. A data receiving circuit characterized by adding a periodic fluctuation pattern of "0 → ...".

(Additional Remark 29) In the data receiving circuit according to Additional Remark 27, the addition processing means performs "0 → 3 → 1 → 2 →" on the 8-bit precision phase control code from the phase control code generating circuit. A data receiving circuit characterized by adding a periodic fluctuation pattern of "0 → ...".

(Additional remark 30) In the data receiving circuit according to any one of additional remarks 15 to 29, the boundary detection circuit includes a plurality of boundary detection units, and each of the boundary detection units responds to each boundary detection clock. Data reception, characterized in that each of the data determination circuits includes a plurality of data determination units, and each of the data determination units performs data determination in response to each data determination clock. circuit.

[0121]

As described above in detail, according to the data receiving circuit (clock recovery circuit) of the present invention, the amplitude of the limit cycle signal is reduced, and the jitter dependence of the feedback loop characteristic is also reduced. It is possible to improve the predictability of the above, and to minimize the phase noise caused by the phase modulation for linearization affecting the internal clock. Further, according to the data receiving circuit (clock recovery circuit) of the present invention, it is possible to increase the resolution of the phase control code generating circuit and reduce the quantization noise of the clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a conventional data receiving circuit.

FIG. 2 is a diagram showing the timing of each signal in the data receiving circuit of FIG.

FIG. 3 is a block diagram showing a data determination clock generation circuit in the data reception circuit of FIG.

FIG. 4 is a diagram showing an example of data and boundary latch timing in an input signal.

FIG. 5 is a block diagram showing an example of a data receiving circuit according to related art.

FIG. 6 is a diagram for explaining the operation of the data receiving circuit shown in FIG.

7 is a block diagram showing an example of a phase difference digital code conversion circuit in the data receiving circuit of FIG.

FIG. 8 is a diagram for explaining the operation of the phase difference digital code conversion circuit shown in FIG.

9 is a diagram for explaining phase difference information output from the phase difference digital code conversion circuit shown in FIG. 7. FIG.

10 is a diagram for explaining an example of the operation of the data receiving circuit shown in FIG.

FIG. 11 is a block diagram showing a principle configuration of a data receiving circuit according to the first embodiment of the present invention.

FIG. 12 is a block diagram showing a principle configuration of a data receiving circuit according to a second embodiment of the present invention.

FIG. 13 is a block diagram showing an embodiment of a data receiving circuit according to the present invention.

FIG. 14 is a diagram (No. 1) for explaining the linearization processing in the data receiving circuit of FIG. 13;

FIG. 15 is a diagram (No. 2) for explaining the linearization process in the data receiving circuit of FIG. 13;

16 is a diagram showing an example of an output pattern of a fluctuation component generation circuit in the data reception circuit of FIG.

17 is a block diagram showing an example of a fluctuation elimination circuit in the data receiving circuit of FIG.

FIG. 18 is a diagram for explaining the operation of the fluctuation eliminating circuit in FIG. 17.

19 is a block diagram showing another example of the fluctuation eliminating circuit in the data receiving circuit of FIG.

FIG. 20 is a block diagram showing another example of the data receiving circuit according to the present invention.

FIG. 21 is a block diagram showing still another example of the data receiving circuit according to the present invention.

22 is a diagram for explaining the operation of the data receiving circuit of FIG. 21. FIG.

23 is a diagram showing an example of a variation added to the data determination phase control code in the data receiving circuit of FIG. 21.

24 is a block diagram showing an example of a data determination clock generation circuit in the data reception circuit of FIG.

FIG. 25 is a block diagram showing still another example of the data receiving circuit according to the present invention.

[Explanation of symbols]

1, 10-13, 110-113 ... Data determination unit 2, 20-23, 120-123 ... Boundary detection unit 5, 105 ... Phase difference digital code conversion circuit 6, 106, 600 ... Digital filter 7, 70, 107, 207 ... Fluctuation generation circuit 8, 80, 108, 208 ... Addition circuit 9, 90, 109, 209, 900 ... Fluctuation removal circuit 31, 32; 131, 132 ... Conversion circuit 41, 141 ... Data determination clock generation circuit 42 , 142 ... Boundary detection clock generation circuit 201 ... Judgment circuit 202 ... Phase comparison circuit 205 ... Phase control code generation circuit 241 ... Judgment clock generation circuit 242 ... Phase comparison clock generation circuits 411, 1411 ... Mixer circuits 413, 1413 ... Digital-to-analog converter (DA
C) 415 ... Integrator circuits DATA [i-2], DATA [i-1], DATA [i], DAT
A [i + 1] ... Data determination timing BDATA [i-2], BDATA [i-1], BDATA [i], B
DATA [i + 1] ... Boundary detection timing CLKb; CLKb0, CLKb1, CLKb2, CLKb3 ...
Boundary detection clock CLKd; CLKd0, CLKd1, CLKd2, CLKd3 ...
Data judgment clock

Claims (10)

[Claims] 1. A boundary detection circuit for detecting a boundary of an input signal according to a first signal, and controlling a timing of the first signal according to the detected boundary to restore a clock. A clock recovery circuit, wherein a boundary detection timing changing means for giving a variation to the first signal and dynamically changing a boundary detection timing in the boundary detection circuit, and a boundary detection timing by the boundary detection timing changing means A clock recovery circuit, comprising: fluctuation reducing means for reducing fluctuations in a phase occurring in a recovered clock according to a dynamic change. 2. A clock recovery circuit having an internal clock generation circuit that receives a first phase control code of a first number of bits and generates an internal clock, the second bit being larger than the first number of bits. A phase control code generation circuit for generating a number of second phase control codes, and a predetermined fluctuation pattern that fluctuates in a short time with respect to the second phase control code, Clock recovery, wherein the internal clock generation circuit effectively generates an internal clock whose phase is controlled by the resolution of the second number of bits. circuit. 3. A data judgment circuit for judging data of an input signal by a data judgment clock, a boundary detection circuit for detecting a boundary of the input signal by a boundary detection clock, and the data judgment circuit and the boundary detection circuit. Phase control code generation means for receiving the output of the phase control code and generating a phase control code, and giving a variation to the boundary detection phase control code,
Boundary detection timing changing means for dynamically changing the boundary detection timing in the boundary detection circuit, and reduction of a phase change generated in the data determination clock in response to a dynamic change in the boundary detection timing by the boundary detection timing changing means. And a fluctuation reducing means for controlling the fluctuation. 4. The data receiving circuit according to claim 3, wherein the fluctuation generation circuit generates fluctuations over a wide phase range in an unstable state and over a narrow phase range in a stable state. A data receiving circuit characterized by generating a variation. 5. The data receiving circuit according to claim 3, wherein the fluctuation generating circuit generates a large gain fluctuation in an unstable state and a small gain fluctuation in a stable state. A data receiving circuit characterized by: 6. The data receiving circuit according to claim 3, wherein the fluctuation generating circuit generates a fluctuation by increasing one unit time of one step in an unstable state and one step in a stable state. A data receiving circuit characterized in that a fluctuation is generated by reducing the unit time of. 7. The data receiving circuit according to claim 3, wherein the fluctuation reducing means averages the signals related to the recovered clock over one cycle or a plurality of cycles of the fluctuation output by the fluctuation generating circuit. A data receiving circuit characterized by the following. 8. The data receiving circuit according to claim 7, wherein the fluctuation reducing means is a notch filter, an FIR filter or a moving average circuit. 9. A data determination clock generation circuit for receiving a first phase control code having a first bit number and generating a data determination clock, and a data determination circuit for determining data of an input signal by the data determination clock. A boundary detection circuit that detects a boundary of the input signal by a boundary detection clock; and a second number larger than the first number of bits by receiving outputs from the data determination circuit and the boundary detection circuit.
Corresponding to the first bit number by adding a phase control code generation circuit for generating a second phase control code having the number of bits of And an addition processing unit that outputs the first phase control code, wherein the data determination clock generation circuit effectively generates a data determination clock whose phase is controlled by the resolution of the second bit number. A data receiving circuit characterized by. 10. The data receiving circuit according to claim 3, wherein the boundary detection circuit includes a plurality of boundary detection units, and each boundary detection unit responds to each boundary detection clock. A data receiving circuit characterized in that each of them detects a boundary, and the data judging circuit includes a plurality of data judging units, and each of the data judging units judges data in accordance with each data judging clock. .