JP3053008B2 - Signal generation method and apparatus, voltage generation method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal generating method and apparatus for generating a pulse signal from digital numerical data, and a voltage generating method and apparatus for converting digital numerical data into an analog voltage.

[0002]

2. Description of the Related Art Conventionally, a PWM (Pulse Pulse) has been used as a signal generation device for generating a pulse signal from digital numerical data.
Width Modulation) circuits and the like are used. If a CR integration circuit is connected to the subsequent stage of such a signal generation device, a voltage generation device that converts digital numerical data into an analog voltage can be formed. The present invention can be used for a PLL (Phase Locked Loop) circuit that follows an input frequency.

Here, a signal generator and a PLL circuit as described above will be described below with reference to FIGS. FIG. 7 is a block diagram showing a PWM circuit as a signal generation device, and FIG. 8 is a block diagram showing a PLL circuit. First, as shown in FIG. 7, a PWM circuit 1 exemplified as a signal generation device has a data input terminal 2 to which a D-type FF (Flip Flop) circuit 3 is connected. ing.

The PWM circuit 1 has a 3-bit counter circuit 4, which is connected to one of a pair of input terminals of a first comparator 5. The other input terminal of the first comparator 5 is connected to a memory or the like that constantly generates “0” as 3-bit numerical data. One output terminal of the first comparator 5 is connected to the FF circuit 3. Connected to control terminal.

The output terminal of the FF circuit 3 is connected to one of a pair of input terminals of a second comparator 6, and the other input terminal of the second comparator 6 is connected to the output terminal of the counter circuit 4. Have been. Output terminals of the first and second comparators 5 and 6 are individually connected to a set terminal and a reset terminal of the RS-type FF circuit 7, respectively.
An output terminal of the F circuit 7 is connected to a 1-bit signal output terminal 8.

In the PWM circuit 1 having the above structure, 3-bit numerical data is externally input to the data input terminal 2, and a pulse signal having a pulse width corresponding to the numerical value is externally output from the signal output terminal 8. More specifically, since the 3-bit counter circuit 4 repeatedly counts “0 to 7”, the first comparator 5 that compares this with “0”
Outputs a detection signal only when the output data of the counter circuit 4 becomes “0”.

Since this is output to the control terminal of the D-type FF circuit 3 connected to the data input terminal 2, the FF circuit 3 outputs a 3-bit numerical value every time the count value of the counter circuit 4 becomes "0". Input data externally. Further, since the detection signal of the first comparator 5 is also output to the set terminal of the RS-type FF circuit 7, the FF circuit 7 is set every time the count value of the counter circuit 4 becomes "0".

The numerical data externally input to the D-type FF circuit 3 and the count value of the counter circuit 4 are compared by a second comparator 6, and the output signal of the second comparator 6 is used as an RS-type FF circuit 7 is input to a reset terminal. Therefore, the output of the FF circuit 7 is
Is set to "0" and reset when the numerical data input to the data input terminal 2 and the count value of the counter circuit 4 match, so that the PWM circuit 1 has a 3-bit external input. A pulse signal having a pulse width corresponding to the numerical data is externally output from the signal output terminal 8.

The above-described PWM circuit 1 outputs a pulse signal corresponding to numerical data of an external input.
As shown in the figure, if a CR integrator 11 is connected to the subsequent stage, a voltage generator 12 for converting numerical data into an analog voltage can be formed, and a PLL circuit 13 and the like can be formed by using the voltage generator 12. Can be formed.

The PLL circuit 13 has an external input terminal 14
The external input terminal 14 is connected to one of a pair of input terminals of the phase error detection circuit 15. A voltage generator 12 is connected to the phase error detection circuit 15 via a loop filter 16, and the voltage generator 12 is connected to a VCO (Voltage Controlled Oscillator).
17 is connected to the other input terminal of the phase error detection circuit 15.

In the PLL circuit 13 described above, the phase error between the signal frequency of the external input of the external input terminal 4 and the oscillation frequency fed back from the VCO 17 is detected by the phase error detection circuit 15, and this phase error is detected by the loop filter. After being filtered at 16, the voltage is converted into an analog voltage by the voltage generator 12. Since the oscillation frequency of the VCO 17 changes in accordance with this analog voltage, the PLL
The circuit 13 can make the oscillation frequency to be fed back follow the signal frequency of the external input.

[0012]

The above-described PWM circuit 1 can generate a pulse signal corresponding to digital numerical data, and a voltage generating device 12 using the PWM circuit 1 can generate a pulse signal. Since an analog voltage can be output in accordance with numerical data, for example, a PLL
It can be used as a part of the circuit 13.

However, the pulse signal output from the PWM circuit 1 as described above has a pulse width corresponding to the input numerical data. However, as shown in FIG. 9, only one pulse signal is output in one cycle. The width of the pulse changes. For this reason, even if the pulse signal output from the PWM circuit 1 is integrated by the CR integration circuit 11 or the like to generate an analog voltage, it is difficult to generate a stable analog voltage with a remarkable voltage fluctuation. Therefore, the PWM circuit 1 as described above is replaced with the PLL circuit 1
3, the oscillation frequency of the VCO 17 is not stable, so that the oscillation frequency cannot be made to follow the signal frequency of the external input satisfactorily.

Further, in the PWM circuit 1 as described above, a pulse signal corresponding to the numerical data of the external input is output each time the counter circuit 4 counts the specified numerical value, so that the numerical data of the external input changes. Even counter circuit 4
The pulse signal of the external output does not change until the counting is completed. For this reason, the PWM circuit 1 does not have good responsiveness, and even if this is used for the PLL circuit 13, the oscillation frequency to be fed back cannot quickly follow the signal frequency of the external input.

For example, if the count number of the counter circuit 4 is reduced, the responsiveness of the PWM circuit 1 can be improved.
The accuracy and the like of the L circuit 13 will be reduced. On the other hand, if the count number of the counter circuit 4 is increased, the number of pulse signal stages that can be output from the PWM circuit 1 is also increased.
Although the accuracy of the circuit 13 can be improved, the response of the PWM circuit 1 is reduced as described above.

In particular, when the count number of the counter circuit 4 is large, even when the numerical data of the external input continuously changes, the numerical data greatly changes at the time of being taken into the FF circuit 3. Become. In this case, although the numerical data of the external input changes continuously, the pulse signal of the external output changes stepwise, and it is meaningless to increase the number of stages of the pulse signal.

That is, in the conventional PWM circuit 1, a pulse signal can be externally output in response to an external input of digital numerical data, but the pulse signal is output in a form in which the voltage fluctuation becomes small when the voltage changes to an analog voltage. Can not
It is difficult to achieve both the responsiveness of a pulse signal output from the outside and the number of output stages.

Similarly, in the conventional voltage generation device 12, an analog voltage can be externally output in response to an external input of digital numerical data, but it is difficult to output an analog voltage with a small voltage fluctuation, It is difficult to achieve both the responsiveness of the analog voltage and the number of output stages.

The present invention has been made in view of the above-described problems, and has a configuration in which when a pulse signal is output to the outside in accordance with numerical data of an external input, a voltage fluctuation is converted into a minute analog voltage. A signal generation method and apparatus capable of outputting pulse signals and outputting pulse signals of a large number of stages with good responsiveness. When an analog voltage is externally output in accordance with numerical data of an external input, voltage fluctuation is very small. It is an object of the present invention to provide a voltage generating method and apparatus capable of outputting a large analog voltage and outputting a large number of analog voltages with good responsiveness.

[0020]

According to the signal generation method of the present invention, the input of n-bit numerical data is accepted every unit time, and the input n-bit numerical data is used as a first input and a second input " It is added to the (n + 1) -bit numerical data and output as "n + 1" bits, and the "n + 1" -bit addition result is fed back as the second input of the above-described addition operation, and the highest-order bit data of the addition result is extracted. Then, the extracted maximum bit data is delayed by a unit time, the delayed bit data and the undelayed bit data are exclusively ORed, and the result of the exclusive OR operation is output as a signal. I did it.

Therefore, the most significant bit is extracted from the addition result of "n + 1" bits obtained by adding the previous addition result to the n-bit numerical data, and this is XORed with the previous most significant bit. When the n-bit numerical data is processed and a signal is output in this way, the output signal is a number of pulses proportional to the numerical data. However, in this case, the plurality of pulses are generated at substantially uniformly discrete positions without being continuous,
When the input numerical data changes, the number of pulses of the output signal changes continuously.

According to another aspect of the present invention, there is provided a signal generating apparatus, comprising: a data input means for receiving input of n-bit numerical data per unit time; and n-bit numerical data input to the data input means as a first input. A numerical value adding means for adding to two-input numerical value data of "n + 1" bits and outputting the data as "n + 1"bits; and a numerical value adding means for delaying the addition result of "n + 1" bits of the numerical value adding means by a unit time. Numerical delay means as a second input, bit extracting means for extracting the highest order bit data of the addition result of the numerical value adding means, and delaying the highest order bit data extracted by the bit extracting means by a unit time Bit delay means, and exclusive use of the bit data delayed by the bit delay means and the bit data extracted and not delayed by the data extraction means. And logical operation means for physical sum, and comprising: a signal output means for signal outputs an operation result of the logic operation means.

Therefore, when the input of the n-bit numerical data is accepted by the data input means for each unit time,
The input n-bit numerical data is added as the first input to the "n + 1" -bit numerical data of the second input by the numerical value adding means and output as "n + 1" bits. The result of addition of the "n + 1" bits is The value is delayed by a unit time by the numerical value delay means and becomes the second input of the numerical value adding means.
The most significant bit data of the addition result of the numerical value adding means is extracted by the bit extracting means, and the extracted most significant bit data is delayed by the unit time by the bit delay means. The delayed bit data and the non-delayed bit data are exclusive ORed by the logic operation means, and the operation result is output as a signal by the signal output means.

That is, the most significant bit is extracted from the "n + 1" -bit addition result obtained by adding the previous addition result to the n-bit numerical data, and this is XORed with the previous most significant bit. When the n-bit numerical data is processed and a signal is output in this way, the output signal is a number of pulses proportional to the numerical data. However, in this case, the plurality of pulses are generated at substantially uniformly discrete positions without being continuous,
When the input numerical data changes, the number of pulses of the output signal changes continuously.

According to another signal generating apparatus of the present invention, a data input terminal to which n-bit numerical data is input, and the n-bit numerical data input to the data input terminal as a first input for each unit time "N +" which is added to two-input "n + 1" -bit numerical data and output with "n + 1" -bit
An adder having a "1" configuration, a first flip-flop circuit which delays an addition result of "n + 1" bits of the adder by a unit time and serves as a second input of the adder, A bit extraction wiring for extracting the maximum bit data, a second flip-flop circuit for delaying the maximum bit data extracted by the bit extraction wiring by a unit time, and a second flip-flop circuit delayed by the second flip-flop circuit An exclusive-OR circuit that performs an exclusive-OR operation on the extracted bit data and the non-delayed bit data input from the bit extraction wiring, and a signal output terminal that outputs a calculation result of the exclusive OR circuit. , Is provided.

Therefore, when n-bit numerical data is input to the data input terminal, the numerical data is accepted by the adder every unit time. In this adder, the input n-bit numerical data is taken as the first input, and added to the “n + 1” -bit numerical data of the second input to obtain “n +
The result of addition of the "n + 1" bits is delayed by a unit time by the first flip-flop circuit to become the second input of the adder, and at the same time, the highest order bit data of the addition result is output. The extracted maximum bit data is delayed by a unit time by the second flip-flop circuit, and the delayed bit data and the undelayed bit data are exclusive ORed. The exclusive OR is performed by the circuit, and the signal is output from the signal output terminal.

That is, the most significant bit is extracted from the "n + 1" -bit addition result obtained by adding the previous addition result to the n-bit numerical data, and this is XORed with the previous most significant bit. When the n-bit numerical data is processed and a signal is output in this way, the output signal is a number of pulses proportional to the numerical data. However, in this case, the plurality of pulses are generated at substantially uniformly discrete positions without being continuous,
When the input numerical data changes, the number of pulses of the output signal changes continuously.

According to the voltage generation method of the present invention, the input of n-bit numerical data is accepted for each unit time, and the input n-bit numerical data is used as a first input, and the second input “n + 1” -bit numerical data is input. And outputs the result as “n + 1” bits. The result of addition of the “n + 1” bits is fed back as the second input of the above-described addition operation, and the highest-order bit data of the addition result is extracted. The highest-order bit data is delayed by a unit time, the delayed bit data and the non-delayed bit data are exclusively ORed, the result of the exclusive OR is integrated, and an analog voltage is output. I did it.

Therefore, the most significant bit is extracted from the addition result of “n + 1” bits obtained by adding the previous addition result to the n-bit numerical data, and the output signal obtained by performing an exclusive OR operation on the most significant bit with the previous most significant bit is an analog signal. Integrated into voltage. When the n-bit numerical data is processed and a voltage is generated in this manner, when constant numerical data is continuously input, the analog voltage is output in a state of small fluctuation, and when the input numerical data changes. , The analog voltage changes continuously.

One voltage generating device of the present invention includes the signal generating device of the present invention, and signal integrating means for integrating an output signal of the signal generating device and outputting an analog voltage. Therefore, when the signal generation device of the present invention generates and outputs a pulse signal from the input numerical data, the signal integration means integrates the pulse signal into an analog voltage.
An analog voltage corresponding to the numerical data is output.

However, since the output signal of the signal generating device is generated at a position where a plurality of pulses are not substantially continuous but discretely distributed, the analog voltage output from the signal integrator is output in a state where the fluctuation is very small. . Since the number of pulses of the output signal of the signal generator changes continuously when the input numerical data changes, the analog voltage output from the signal integrator continuously changes when the numerical data changes. .

Another voltage generating device of the present invention includes the signal generating device of the present invention, and a CR integration circuit that integrates an output signal of the signal generating device and outputs an analog voltage. Therefore, when the signal generation device of the present invention generates and outputs a pulse signal from the input numerical data, the CR integration circuit integrates the pulse signal into an analog voltage.
An analog voltage corresponding to the numerical data is output.

However, since the output signal of the signal generation device is generated at a position where a plurality of pulses are not substantially continuous but discretely distributed, the analog voltage output from the CR integration circuit is output in a state where the fluctuation is very small. . In addition, the output signal of the signal generator continuously changes the number of pulses when the input numerical data changes, so that the analog voltage output from the CR integrator changes continuously when the numerical data changes. .

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. Note that the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description is omitted.

FIG. 1 is a block diagram showing a signal generator according to one embodiment of the present invention, and FIG. 2 is a time chart showing the relationship between numerical data input to the signal generator and pulse signals output.

FIGS. 3A and 3B show the relationship between the signals of the respective units when the numerical data of "1" is continuously input to the signal generator. FIG. 3A shows a reference clock input to a clock input terminal. b) is numerical data input to a data input terminal as data input means, (c) is numerical data output from an adder as numerical value adding means, and (d) is numerical data output from an adder and is a numerical delay means. Numerical data delayed by a certain first FF circuit, (e) is the most significant bit data of the numerical data output from the adder to the bit extraction wiring as bit extracting means, and (f) is bit delaying means. The most significant bit data delayed by the second FF circuit, (g) is a pulse signal output from the exclusive OR circuit as the logical operation means to the signal output terminal as the signal output means.

FIGS. 4 and 5 also show the relationship between the signals of the respective parts of the signal generating apparatus as in FIG. 3. FIG. 4 shows the case where numerical data of "4" is continuously input, and FIG. This is a case where changing numerical data is input. FIG. 6 is a time chart showing the operation of the voltage generation device that includes the signal generation device as a part, and showing the relationship between the pulse signal and the analog voltage.

The signal generating apparatus 21 of the present embodiment is similar to that of FIG.
As shown in FIG. 1, a data input terminal 22 corresponding to data input means is provided, and this data input terminal 22 is connected to a first input terminal of an adder 23 which is a numerical value adding means. One output terminal of the adder 23 is connected to a first FF circuit 24 which is a first flip-flop circuit corresponding to a numerical delay means. Connected to the second input terminal.

However, the data input terminal 3 is connected to the first input terminal of the adder 23 by 3-bit parallel wiring, but the output terminal and the second input terminal of the adder 23 are connected to the first FF circuit 24. Are connected by 4-bit parallel wiring. The 4-bit output wiring of the adder 23 is separated only from the wiring for transferring the most significant bit data, and this is used as a bit extraction wiring 25 corresponding to bit extraction means, as a second flip-flop corresponding to bit delay data. It is connected to a second FF circuit 26 which is a circuit.

The output terminal of the second FF circuit 26 and the bit extraction wiring 25 are connected to a pair of input terminals of an exclusive OR circuit 27 which is a logical operation means. It is connected to a signal output terminal 28.
Note that the signal generation device 21 of the present embodiment also has a clock input terminal 29 which is an input terminal of a clock signal, and the clock input terminal 29 is connected to the FF circuits 24 and 26.
And the like.

In the above-described configuration, the signal generating apparatus 1 of the present embodiment, as shown in FIG. 2, responds to a digital input of 3-bit numerical data by outputting eight pulses of the number corresponding to the numerical value. The signal is output at the cycle of. More specifically, when 3-bit numerical data is externally input to the data input terminal 22, the numerical data is received by the adder 23 at each unit time of one clock.

In the adder 23, the input 3-bit numerical data is used as the first input, added to the 4-bit numerical data of the second input, and output as 4-bit data. The result is delayed by one clock by the first FF circuit 24 and becomes the second input of the adder 23.

At the same time, the 4-bit addition result of the adder 23 is extracted by the bit extraction wiring 25 only for the most significant bit data, and the extracted most significant bit data is delayed by one clock by the second FF circuit 26. I'm done. The delayed bit data is exclusive ORed with the undelayed bit data by the exclusive OR circuit 27,
The result of this logical operation is output as a signal from the signal output terminal 28.

For example, when "1" is continuously input as 3-bit numerical data to the signal generating apparatus 1 of the present embodiment, as shown in FIG. It is sequentially integrated with one FF circuit 24. At this time, the numerical data output from the adder 23 and fed back through the first FF circuit 24 is 4 bits, and the most significant bit data is extracted by the bit extraction wiring 25. Each time the input of the numerical data of the bit “1” reaches eight times, it alternates between “0” and “1”.

This bit data is delayed by one clock in the second FF circuit 26 and is subjected to an exclusive OR operation in the exclusive OR circuit 27 with the bit data which is not delayed. Since a pulse is generated only once every eight clocks in the signal output from the signal output terminal 28 after the exclusive OR operation, the pulse corresponding to the 3-bit "1" is generated as in the conventional case. It can be used as a signal.

The signal generator 1 of this embodiment has three
When "4" is continuously input as numerical data of bits, as shown in FIG. 4, this "4" is sequentially integrated by the adder 23 and the first FF circuit 24, and the most significant bit is added. Data is extracted by the bit extraction wiring 25.

This bit data becomes “0” and “1” every time the 3-bit numerical data of “4” reaches twice.
And the bit data delayed by one clock in the second FF circuit 26 and not delayed are XORed by the exclusive OR circuit 27. In the signal output from the signal output terminal 28 after the exclusive OR operation, a pulse is generated only four times in eight clocks. This is used as a pulse signal corresponding to 3 bits "4". be able to.

However, as shown in FIG. 9, the conventional "4"
In the pulse signal corresponding to, the generation and pause of the four pulses generated in eight clocks were continuous by four clocks, but the signal generator 21 of the present embodiment generates four pulses generated in eight clocks. The occurrence and the pause are each one clock. That is, in the signal generator 21 of the present embodiment, when outputting a pulse signal corresponding to the input numerical data, the pulse is generated at substantially uniformly discrete positions as shown in FIG.

For this reason, the signal generator 2 of the present embodiment
1 is connected to a CR integration circuit as signal integration means to form a voltage generation device (not shown).
When the analog signal is output by integrating the output signal of FIG. 1 by the CR integrator circuit, as shown in FIG. 6, the analog voltage has a small fluctuation and the output becomes stable. For example, when such a voltage generator is used in a PLL circuit, the analog voltage output from the voltage generator to the VCO is stable, so that the performance of causing the oscillation frequency to follow the input frequency can be stabilized.

When the 3-bit numerical data input to the signal generating device 21 of the present embodiment changes, FIG.
As shown in the figure, the number of pulses corresponding to the numerical data is generated discretely for each clock in the output signal.
The number of the pulses continuously changes every clock in accordance with the change of the numerical data.

For this reason, the signal generator 2 of the present embodiment
In 1, when a pulse signal is externally output in response to an external input of digital numerical data, even if the number of bits of the pulse signal that can be output by increasing the number of bits of the counter circuit 23 is large, the output of the pulse signal is large. Since the responsiveness does not decrease, a pulse signal having a large number of stages can be output with good responsiveness.

Accordingly, the signal generator 21 according to the present embodiment
When a voltage generating device is formed by connecting a CR integrating circuit to the subsequent stage, the output analog voltage continuously changes in real time in response to a change in the input numerical data.
For example, when such a voltage generator is used for a PLL circuit, the analog voltage output from the voltage generator to the VCO continuously changes in real time, so that the responsiveness of causing the oscillation frequency to follow the input frequency is improved. be able to.

The present invention is not limited to the above-described embodiment, but allows various modifications without departing from the gist of the present invention. For example, in the above embodiment, n bits of numerical data input to the signal generation device 21 are exemplified as 3 bits, but this may be a desired number of bits corresponding to the specifications of the device.

[0054]

Since the present invention is configured as described above, it has the following effects.

In the signal generation method according to the first aspect of the present invention, n
Accepts input of bit numerical data every unit time,
The input n-bit numerical data is added as the first input to the "n + 1" -bit numerical data of the second input and output as "n + 1" bits, and the result of addition of the "n + 1" bits is calculated by the above-described addition operation. As the second input, extracts the highest-order bit data of the addition result, delays the extracted highest-order bit data by a unit time, and outputs the delayed bit data and the non-delayed bit data. Is exclusive-ORed and the result of the exclusive-OR operation is output as a signal.
When n-bit numerical data is input, a signal corresponding to the number of pulses can be output, and pulses of the output signal can be generated at substantially uniformly discrete positions. When the numerical data to be changed changes, the number of pulses of the output signal can be changed continuously.

According to a second aspect of the present invention, there is provided a signal generating apparatus comprising:
A data input means for receiving input of bit numerical data every unit time, and n-bit numerical data input to the data input means as a first input and "n +"
A numerical value adding means for adding the numerical value data of 1 bit and outputting with "n + 1"bits;
Numerical value delay means for delaying the bit addition result by a unit time and serving as a second input of the numerical value addition means, bit extraction means for extracting the highest-order bit data of the addition result of the numerical value addition means, Bit delay means for delaying the maximum bit data extracted by the means by a unit time, and exclusive use of the bit data delayed by the bit delay means and the bit data extracted and not delayed by the data extraction means. By providing a logical operation means for performing an OR operation and a signal output means for outputting a signal of the operation result of the logical operation means, when n-bit numerical data is input, the number of pulses corresponds to this. It is possible to output the pulse of the signal to be output in this way at substantially uniformly discrete positions,
When the input numerical data changes, the number of pulses of the output signal can be changed continuously.

According to a third aspect of the present invention, there is provided a signal generating apparatus comprising:
A data input terminal to which bit numerical data is input, and adding the n-bit numerical data input to the data input terminal to the second input “n + 1” -bit numerical data as a first input per unit time An adder having an “n + 1” configuration outputting with “n + 1” bits, and a first flip-flop circuit which delays the addition result of the “n + 1” bits of the adder by a unit time and uses the result as a second input of the adder; A bit extraction wiring for extracting the highest order bit data of the addition result of the adder, a second flip-flop circuit for delaying the highest order bit data extracted by the bit extraction wiring by a unit time, Exclusive logic for exclusive-ORing the bit data delayed by the two flip-flop circuits and the non-delayed bit data input from the bit extraction wiring Circuit, and a signal output terminal for outputting the operation result of the exclusive OR circuit. When n-bit numerical data is input, a signal corresponding to the number of pulses Can be output, and the pulses of the output signal can be generated at substantially uniformly discrete positions. When the input numerical data changes, the number of pulses of the output signal changes continuously. be able to.

According to a fourth aspect of the present invention, there is provided a voltage generation method comprising:
Accepts input of bit numerical data every unit time,
The input n-bit numerical data is added as the first input to the "n + 1" -bit numerical data of the second input and output as "n + 1" bits, and the result of addition of the "n + 1" bits is calculated by the above-described addition operation. As the second input, extracts the highest-order bit data of the addition result, delays the extracted highest-order bit data by a unit time, and outputs the delayed bit data and the non-delayed bit data. Is exclusive-ORed, and the result of the exclusive-OR operation is integrated to output an analog voltage. When n-bit numerical data is input, an analog voltage corresponding to this is output. When constant numerical data is continuously input, the analog voltage can be output with a small fluctuation, and the input numerical data can be changed. When, it is possible to change the analog voltage continuously.

According to a fifth aspect of the present invention, there is provided a voltage generating apparatus, comprising: a signal generating apparatus according to the second aspect; signal integrating means for integrating an output signal of the signal generating apparatus to output an analog voltage;
Is provided. Therefore, when the signal generation device according to the second aspect generates and outputs a pulse signal from the input numerical data, the signal integrator integrates the pulse signal into an analog voltage. By being output, when n-bit numerical data is input, an analog voltage corresponding to this can be output, and when constant numerical data is continuously input,
The analog voltage can be output in a state where the fluctuation is small, and when the input numerical data changes, the analog voltage can be changed continuously.

According to a sixth aspect of the present invention, there is provided a voltage generating apparatus, comprising: a signal generating apparatus according to the third aspect; a CR integration circuit for integrating an output signal of the signal generating apparatus to output an analog voltage;
Is provided. Therefore, when the signal generation device according to the third aspect generates and outputs a pulse signal from the input numerical data, the CR integration circuit integrates the pulse signal into an analog voltage. By being output, when n-bit numerical data is input, an analog voltage corresponding to this can be output, and when constant numerical data is continuously input,
The analog voltage can be output in a state where the fluctuation is small, and when the input numerical data changes, the analog voltage can be changed continuously.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a signal generation device according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating a relationship between numerical data input to a signal generation device and a pulse signal output;

FIG. 3 is a time chart illustrating a relationship between signals of respective units of the signal generation device to which numerical data of “1” is continuously input.

FIG. 4 is a time chart illustrating a relationship between signals of respective units of the signal generation device to which numerical data of “4” is continuously input.

FIG. 5 is a time chart illustrating a relationship between signals of respective units of the signal generating apparatus when sequentially changing numerical data is input.

FIG. 6 is a time chart showing a relationship between a pulse signal and an analog voltage.

FIG. 7 is a block diagram showing a PWM circuit which is a signal generation device of a conventional example.

FIG. 8 is a block diagram showing a PLL circuit that includes a PWM circuit as a part.

FIG. 9 is a time chart showing a relationship between a pulse signal and an analog voltage.

[Explanation of symbols]

Reference Signs List 21 signal generating device 22 data input terminal corresponding to data input means 23 adder serving as numerical value adding means 24 first flip-flop circuit serving as numerical delay means 25 bit extracting wiring serving as bit extracting means 26 bit extracting means serving as bit delay means Two flip-flop circuits 27 Exclusive OR circuit as logic operation means 28 Signal output terminal as signal output means

Claims (6)

(57) [Claims] 1. An input of n-bit numerical data is received for each unit time, and the input n-bit numerical data is added as a first input to a second input of “n + 1” -bit numerical data to obtain “n + 1”. The result of addition of the “n + 1” bits is fed back as the second input of the above-described addition operation, and the highest-order bit data of the addition result is extracted. A signal generation method for delaying by a unit time, performing an exclusive OR operation on the delayed bit data and the non-delayed bit data, and outputting a result of the exclusive OR operation. 2. A data input means for receiving an input of n-bit numerical data every unit time; and n-bit numerical data inputted to said data input means as a first input and a second input of "n + 1" bits A numerical value adding means for adding to the numerical data and outputting the data as "n + 1"bits; Bit extracting means for extracting the most significant bit data of the addition result of the numerical value adding means; bit delay means for delaying the most significant bit data extracted by the bit extracting means by a unit time; Logic operation means for performing an exclusive OR operation on the bit data delayed by the means and the bit data extracted by the data extraction means and not delayed; And it has a signal generation device anda signal output means for signal outputs an operation result of the logic operation means. 3. A data input terminal to which n-bit numerical data is input, and using the n-bit numerical data input to the data input terminal as a first input, a "n + 1" bit of a second input per unit time. An adder having an “n + 1” configuration for adding to the numerical data and outputting the result as “n + 1” bits; and a second input of the adder which delays an addition result of “n + 1” bits of the adder by a unit time. One flip-flop circuit, a bit extraction wiring for extracting the maximum bit data of the addition result of the adder, and a second flip-flop for delaying the maximum bit data extracted by the bit extraction wiring by a unit time Exclusive logic between the bit data delayed by the second flip-flop circuit and the non-delayed bit data input from the bit extraction wiring. An exclusive OR circuit for summation, exhaust another OR circuit operation result is that the signal generating device comprises a signal output terminal that is the signal output, the. 4. An input of n-bit numerical data is accepted for each unit time, and the input n-bit numerical data is added as a first input to a second input of “n + 1” -bit numerical data to obtain “n + 1”. The result of addition of the “n + 1” bits is fed back as the second input of the above-described addition operation, and the highest-order bit data of the addition result is extracted. A voltage generation method that delays by a unit time, performs an exclusive OR operation on the delayed bit data and the non-delayed bit data, integrates the operation result of the exclusive OR operation, and outputs an analog voltage. . 5. A voltage generation device comprising: the signal generation device according to claim 2; and signal integration means for integrating an output signal of the signal generation device and outputting an analog voltage. 6. A voltage generation device comprising: the signal generation device according to claim 3; and a CR integration circuit that integrates an output signal of the signal generation device and outputs an analog voltage.