JPH03135226A - Frequency synthesizer device - Google Patents

Abstract

PURPOSE:To reduce jitters and to constitute a device by means of an integrated circuit by providing a delay means delaying the carry signal of an adder by means of an output signal and reducing the jitters of the signal of a setting frequency. CONSTITUTION:The adder 1 adds frequency setting data to the output signal for respective reference clocks, outputs the signal of the setting frequency and outputs the carry signal when an output value reaches a prescribed value. The delay means 3 delays the carry signal of the adder 1 by the output signal and reduces the jitters of the signal of the setting frequency. Thus, the delay means 3 can be constituted by a logic circuit or the like and jitters can be reduced, whereby the device can be constituted by the integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency synthesizer device used in standard signal generators and the like.

Prior Art FIG. 6 shows the configuration of a conventional frequency synthesizer device.

In FIG. 6, 7 is an adder that adds set frequency data 6 to the feedback signal of the output signal for each reference clock (frequency fs) from the reference clock generator 8, and 9 is an adder in which sine wave data is stored in advance. , a sine wave data memory that outputs sine wave data at an address specified by the output signal of the adder 7; lO is a D/A that converts the sine wave data read from the sine wave data memory 9 into an analog signal;
Converter 11 and 12 are a low-pass filter and a comparator, respectively, for suppressing jitter of the sine wave signal converted by the D/A converter 10 and outputting it as a pulse train.

As shown in FIG. 7, the adder 7 which outputs an m-bit signal is used so that the output signal of n (km) bits starting from the upper bit MSB becomes the address of the sine wave data memory 9. The sine wave data memory 9 stores quantized amplitude data at each sampling point obtained by dividing one cycle of the sine wave into 21 equal parts.

The adder 7 outputs discontinuous values by adding the set frequency data at the timing of the reference clock, and therefore, amplitude data corresponding to the set frequency data is read out from the sine wave data memory 9.

Furthermore, when the set frequency data is set only to the (mn) bit output signal of the adder 7, the timing of carrying the least significant bit LSB changes depending on the set frequency data due to repeated addition. Do not output discrete values, or change the frequency of the output signal depending on the set frequency data.

Here, the output signal of the D/A converter 10 is discontinuous in phase due to the digital synthesis method, and is therefore a sine wave with jitter. This amount of jitter is determined by the resolution of the D/A converter 10, and is the standard for the n-bit D/A converter 10. This jitter is shaped by a low-pass filter 11 and a comparator, and output as a signal with less jitter.

Problems to be Solved by the Invention However, in the above conventional frequency synthesizer device, the D/A converter 10, the a-pass filter 11 . Since the comparator 12 is used, there is a problem that it cannot be constructed using an integrated circuit.

SUMMARY OF THE INVENTION In view of the above conventional problems, it is an object of the present invention to provide a frequency synthesizer device that can reduce sick and can be configured with an integrated circuit.

Means for Solving the Problems In order to achieve the above object, the present invention adds frequency setting data to the output signal for each reference clock to output a signal of the set frequency, and also adjusts the output value to a predetermined value. It consists of an adder that outputs a carry signal when the set frequency is reached, and a delay means that delays the carry signal of the adder by the output signal to reduce the jitter of the signal at the set frequency.

Operation According to the present invention, the delay means can be constructed from a logic circuit or the like, and therefore jitter can be reduced, and the delay means can be constructed from an integrated circuit.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the frequency synthesizer device according to the present invention, FIG. 2 is a block diagram showing the detailed configuration of the first delay circuit, and FIG. 3 is the addition of FIG. 1. 4 is a block diagram showing an example of the adder of FIG. 1, and FIG. 5 is a timing chart showing main signals in a frequency synthesizer device using the adder of FIG. 4. It is.

In FIG. 1, 1 indicates the case where the frequency setting data m is added to the output signal for each reference clock (frequency fs, period Ts) from the reference clock generation circuit 2, and the output value reaches a predetermined value. The adder 1 is an n-bit adder that outputs a carry signal in parallel.

3 has a delay circuit τ that delays the carry signal of adder 1 according to the output signal and outputs a pulse train, and as shown in FIG. a switch 2a that outputs the carry signal as is;
It has a switch 2b1 and a delay device 2c for time delaying the output value 1.2...n) of the adder 1.

Next, the operation of the above embodiment will be explained with reference to FIG.

In the above configuration, the adder repeatedly adds the setting data m to the output value at the timing of the reference clock having the frequency fs, and the carry signal rises at a predetermined time To.

Here, add! Frequency r of the output signal of the added value of i-device 1
o can be expressed as fo = mba.m. Therefore, if m/2n is an integer, the output signal at frequency fo will be a jitter-free signal, and if it is not an integer, it will be a jittery signal.

That is, as shown in FIG. 3, the output value of adder 1 is
It increases by an integral multiple of the set value m, and when it reaches 2n or more, the carry signal becomes high level. Therefore, (H/2
If n is an integer, there is no remainder, so time T. A pulse train repeating at an interval of T can be obtained, and if m/2n is not an integer, a remainder will occur and the time T. is the desired circumference XQT
different from.

Therefore, the delay circuit 3 is connected to the adder 1 as shown in FIG.
At the rise of the carry signal from 2(
1 shows a frequency synthesizer device using an adder 1a of =n) bits.

When frequency data r4j (=m) is set in this adder 1a, m/2n becomes an integer "1", and as shown in FIG. 5, the carry signal becomes high level every time the reference clock A is input. Outputs pulse train B without jitter.

On the other hand, when frequency data r3J (=m) is set in the adder la, m/2nh<a non-integer value "3/4", and a sick time Ts occurs in the carry signal C with respect to the pulse train B. Then, the addition signal of the adder 1a is
Similar to the carry signal C, the jitter can be reduced to the level where the jitter of the time Ts occurs with respect to the pulse train B.

As described in detail, the present invention adds frequency setting data to the output signal for each reference clock to output a signal of the set frequency, and when the output value reaches a predetermined value, Since it is composed of an adder that outputs a carry signal, and a delay means that delays the carry signal of the adder by the output signal to reduce the jitter of the signal at the set frequency, the delay means can be composed of a logic circuit or the like. Therefore, jitter can be reduced and it can be configured with a precision integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one implementation of the frequency synthesizer device ρj according to the present invention, FIG. 2 is a block diagram showing the detailed configuration of the first delay circuit, and FIG. 3 is the addition of FIG. 1. FIG. 4 is a block diagram showing the adder 1 of FIG. 1, and FIG. 5 is an explanatory diagram showing the operation of the adder of FIG. 6 is a block diagram showing a conventional frequency synthesizer device, and FIG. 7 is a block diagram showing a detailed configuration of the adder shown in FIG. 6. 1...Adder, 2...Basic clock generation circuit, 3 delay circuit. Figure 1

Claims (2)

[Claims] (1) Means for generating a reference clock; For each reference clock, frequency setting data is added to the output signal to output a signal of the set frequency, and a carry signal is generated when the output value reaches a predetermined value. 1. A frequency synthesizer device comprising: an adder that outputs a signal; and a delay means that delays a carry signal of the adder with an output signal to reduce jitter of a signal at a set frequency. (2) The adder outputs a signal at a set frequency as a multi-bit parallel signal, and the delay means includes a plurality of delay devices that delay each output signal of the adder (1).
) frequency synthesizer device described.