RU2788980C1 - Measuring generator of paired pulses - Google Patents

Abstract

FIELD: electrical impulse generation.

SUBSTANCE: measuring generator of paired pulses contains an adder, one input of which is the input for controlling the pulse generation frequency, and the second input is connected to the output of the register, in which the information input is connected to the output of the adder, and the clock input is connected to the output of the reference generator, a comparator and two delay triggers are additionally introduced. In this case, the first delay trigger is connected by its information input to the transfer output of the adder, the synchronization input to the output of the reference generator, and the output to the information input of the second delay trigger. The second delay trigger with its synchronization input is connected to the output of the comparator, one of the inputs of which is connected to the output of the register, and the second input serves as the input for controlling the delay between the generated pulses. The outputs of the generator are the outputs of the first and second delay triggers, respectively.

EFFECT: invention enables to expand the functionality by generating a pair of pulses of adjustable frequency with a programmable delay between them.

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Description

The technical field to which the invention belongs

The present invention relates to the technique of generating electrical oscillations, namely to measuring generators of paired pulses with a programmable delay between them.

State of the art

Pair pulse generators separated by an adjustable time interval are used in measuring technology, information transmission systems, rotary transformer control devices, and quadrature signal processing systems. The circuitry of such generators combines analog and digital signal processing methods.

An analog generator of paired pulses is known according to the author's certificate of the USSR No. 1072258, IPC H03K 5/22, containing a pulse duration expander, amplifiers, resistors and an output unit capable of proportionally changing the duration of the generated pulses and the time interval between them. However, due to the analog design, this analog does not have the frequency stability of the generated pulses and does not allow digital control of the delay time between them.

An analogue of the present invention is a generator of paired pulses with digital phase shift generation according to the author's certificate of the USSR No. 526062, IPC H03K 3/78, built on the basis of a phase-locked loop system, supplemented by several pulse counters, triggers, a delay element and a code comparison circuit. This analog has increased reliability and accuracy, however, it has a long time for establishing the operating mode due to the transient process that occurs during the frequency tuning process. Also known is the generator of paired pulses, proposed in the author's certificate 1812623, IPC H03K 5/13, built entirely on a digital element base, including a pulse counter, a trigger, logic gates and an analog-to-digital converter. Due to this, the device has increased reliability and stability of the generated pulses. The principle of operation of this device is based on the recalculation of reference pulses, as a result of which the tuning step of the time parameters is equal to the period of the reference frequency. In addition, paired pulses are output to a common output. These features of the device limit its functionality when using the generator in measuring technology. Also known is a digital synthesizer of multiphase signals according to the patent of the Russian Federation 2423782, IPC H03L 27/00, using the method of direct digital synthesis, which provides high frequency setting accuracy. The device contains connected in series the first memory register, the first digital storage device, the second digital storage device, the first code converter, the first digital-to-analog converter, the first low-pass filter; serially connected second memory register and a frequency divider with a variable division ratio; serially connected clock generator and delay unit; connected in series the first inverter, the second digital-to-analog converter, the second low-pass filter; moreover, the output of the frequency divider with a variable division ratio is connected to the input of the first digital storage device, the outputs of the delay unit are connected to the clock input of the frequency divider with a variable division ratio, to the clock input of the first and to the clock input of the second digital storage device, to the clock input of the first and to the clock input of the second digital-to-analog converters; the most significant bit of the second digital drive is connected to the inversion control input of the first code converter, while from the output of the first code converter the signals of the most significant bits through the inverter are fed to the information inputs of the second digital-to-analogue converter; the first and second inputs of the digital synthesizer of polyphase signals are the inputs of the first and second registers of the memory, and the first and second outputs of the digital synthesizer of polyphase signals are the outputs of the first and second low-pass filters. To expand the functionality of the device, additionally connected in series the third memory register, the adder, the second code converter, the third digital-to-analog converter, the third low-pass filter; connected in series the second inverter, the fourth digital-to-analog converter, the fourth low-pass filter; in addition, the output of the second digital storage device is connected to the input of the adder, and the most significant bit of the adder is connected to the inversion control input of the second code converter; the output of the second code converter is connected to the input of the second inverter, the outputs of the delay unit are connected to the clock input of the third and the clock input of the fourth digital-to-analog converters, and the input of the third memory register is the third input of the digital synthesizer of polyphase signals, and the third and fourth outputs of the digital synthesizer of polyphase signals are the outputs of the third and a fourth low pass filter.

The disadvantage of this analog is its complexity and the inability to adjust the delay time between the generated signals.

The closest in technical essence to the proposed invention is the basic circuit of a direct digital frequency synthesizer, presented in numerous publications, in particular, shown in Figure 4 in the article by L. Ridiko “DDS: direct digital frequency synthesis (Components and technologies. - 2001, No. 7 , see also the electronic resource URL: http://ra3ggi.qrz.ru/UZLY/dds.htm). The prototype device contains a serially connected multi-bit adder, a storage register, a permanent memory, a digital-to-analog converter and a low-pass filter, the output of which is a signal output, and the digital output of the storage register, in which the clock input is connected to the output of the clock generator, is connected to a digital the input of the first term of the multi-bit adder, the second digital input of which is the input of the signal frequency control code. A multi-bit adder with feedback on the first digital input through the storage register forms an accumulative adder (accumulator). This device is highly accurate and fast in frequency setting, and due to the read-only memory programmability, it is capable of generating arbitrary waveforms. In a number of measurement tasks, it is sufficient to generate rectangular pulses.

The prototype device has a single signal output and is not capable of generating a pair of pulses offset relative to each other by a given time interval. This is its disadvantage.

Disclosure of the essence of the invention

The aim of the present invention is to expand the functionality by generating two square wave pulses on separate outputs with a digitally adjustable frequency and delay between them. This goal is achieved by introducing into a device containing an adder, one input of which is the input for controlling the pulse generation frequency, and the second input is connected to the output of the register, in which the information input is connected to the output of the adder, and the clock input is connected to the output of the reference oscillator, a comparator and two delay triggers. In this case, the first delay trigger is connected by its information input to the transfer output of the adder, by the synchronization input to the output of the reference oscillator, and by its output to the information input of the second delay trigger. The second delay trigger with its synchronization input is connected to the output of the comparator, one of the inputs of which is connected to the output of the register, and the second input serves as an input for controlling the delay between the generated pulses. The outputs of the generator are the outputs of the first and second delay triggers, respectively.

In essence, its basic part was borrowed from the prototype device - the battery responsible for tuning the frequency of the generated pulses, and digital nodes were added that ensure the generation of the second output pulse with a programmable delay relative to the first output pulse. Brief description of the drawings

In FIG. 1 is a functional electrical diagram of a measurement pair pulse generator in accordance with the present invention.

In FIG. 2 shows the timing diagrams of signals in the characteristic nodes of the measuring generator of paired pulses.

Implementation of the invention

Shown in FIG. 1, the functional diagram of the measuring pair pulse generator consists of an adder 1, one input of which 2 serves as the input of a digital code that sets the frequency of the generated pulses, the other input is connected to the output of register 3, the information input of the adder 1 connected to the output, and the clock input to the output of the reference oscillator 4. Thanks to the feedback of adder 1 through register 3, they together form a digital accumulator. The circuit contains a comparator 5 connected by one input to the output of register 3, the other input of which serves as input 6 for controlling the delay between the generated pulses, as well as the first 7 and second 8 D-type delay triggers and output terminals 9 and 10. The first delay trigger 7 with its information input connected to the transfer output of the adder 1, the synchronization input to the output of the reference oscillator 4, and the output to the information input of the second delay trigger 8 and the first output terminal 9. The synchronization input of the second delay trigger 8 is connected to the output of the comparator, and its output to the second output terminal 10. Adder 1, register 3 and comparator 5 are n-bit digital nodes.

On the timing diagrams of signals (Fig. 2), illustrating the operation of the device, individual diagrams for convenience of description are indicated by numbers corresponding to the outputs of the same nodes of the circuit of Fig. 1. With each cycle set by the reference oscillator 4, the output state of the accumulator (register 3) receives an increment specified by the code D _F at the input 2 of the adder 1. As a result, the output binary number N at the output of register 3 monotonically increases in steps of height D _F , at the output transfer of the adder 1 periodically at the moments of overflow of the accumulator (exceeding the value of N _max = 2 ⁿ ) signals are generated, the frequency of which is

,

,

- частота импульсов опорного генератора 6,

- код управления частотой на входе 2. По фронтам сигнала переноса на соответствующем выходе сумматора 1 очередной импульс опорного генератора 4 взводит первый триггер 7 задержки, на выходе которого и, следовательно, на первом выходе 9 генератора формируются прямоугольные импульсы, следующие со скважностью, равной двум. Компаратор 5 непрерывно сравнивает число N, поступающее с выхода регистра 3, с числом

, определяющим время задержки между выходными импульсами. В момент, когда выходное состояние N на выходе регистра 3 превысит значение

, компаратор 5 вырабатывает импульс, синхронизирующий второй триггер 8 задержки, который передает на второй выходной зажим 10 задержанное логическое состояние первого выхода 9. Поскольку модуль счета аккумулятора составляет

, то значение управляющего кода

может располагаться в пределах

, а время задержки

(см. фиг. 2) определяется количеством отсчитанных периодов опорного генератораwhere n is the capacity of the adder and the storage register,

- pulse frequency of the reference oscillator 6,

- frequency control code at input 2. On the fronts of the transfer signal at the corresponding output of the adder 1, the next pulse of the reference oscillator 4 cocks the first delay trigger 7, at the output of which and, therefore, at the first output 9 of the generator, rectangular pulses are formed, following with a duty cycle equal to two . Comparator 5 continuously compares the number N coming from the output of register 3 with the number

, which determines the delay time between output pulses. At the moment when the output state N at the output of register 3 exceeds the value

, the comparator 5 generates a pulse synchronizing the second delay trigger 8, which transmits to the second output terminal 10 the delayed logic state of the first output 9. Since the battery counting module is

, then the value of the control code

may be located within

, and the delay time

(see Fig. 2) is determined by the number of counted periods of the reference oscillator

.

.

Thus, the proposed device generates a pair of square-shaped pulses with a widely adjustable frequency with high resolution inherent in direct digital synthesis. The time offset between pulses on a pair of outputs can be adjusted within a half-cycle by changing the digital delay code D _f . Compared with the prototype, this means an expansion of the functionality of the device.

Claims (1)

Measuring pair pulse generator containing an adder, one input of which is the input for controlling the frequency of generating pulses, and the second input is connected to the output of the register, in which the information input is connected to the output of the adder, and the clock input is connected to the output of the reference oscillator, characterized in that it a comparator and two delay triggers are additionally introduced, while the first delay trigger is connected with its information input to the transfer output of the adder, the synchronization input to the output of the reference oscillator, and the output serving as the first output of the generator to the information input of the second delay trigger, the second delay trigger, the output of which serves as the second output of the generator, its synchronization input is connected to the output of the comparator, one of the inputs of which is connected to the output of the register, and the second input serves as an input for controlling the delay between the generated pulses.

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