JP3578943B2 - Delay generator and frequency synthesizer and multiplier using the delay generator - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a delay generator that generates a pulse rising with a set time delay, a frequency synthesizer used in a wireless communication device, and a multiplier.
[0002]
[Prior art]
FIG. 15 is a diagram showing a conventional delay generator (reference: Analog Devices, Inc., Linear Data Book 1994/1995, pp. 12-36 to 12-64). As shown in the figure, the current source 2, the capacitor 3, and the switch 8 form an integrator. The trigger circuit 1 opens and closes the switch 8 in response to a leak signal input to the leak signal input terminal 9 and a trigger signal input to the trigger signal input terminal 10, and the integrator operates the ramp wave voltage V_RTo occur. On the other hand, the latch 4 latches the setting data K input to the setting data K input terminal 12 in accordance with the latch signal input to the latch signal input terminal 11 and sets it in the D / A converter 5. The D / A converter 5 has a threshold voltage (final ultimate voltage) V proportional to the setting data K._TTo occur. The comparator 6 has a ramp voltage V_RAnd threshold voltage V_TAnd the ramp wave voltage V_RAnd threshold voltage V_TA pulse which rises at the timing when the signal matches with is output. The one-shot 7 receives the output pulse of the comparator 6 and outputs a pulse having a pulse width corresponding to the time constant τ to the output terminal 13.
[0003]
FIG. 16 is a time chart showing an operation example of the delay generator shown in FIG. 16A shows a trigger signal, FIG. 16B shows a latch signal, FIG. 16C shows setting data K, FIG. 16D shows a leak signal, and FIG. 16E shows a ramp wave voltage V which is a voltage at one end of the capacitor 3._R, (F) shows a threshold voltage V which is an output voltage of the D / A converter 5._T, (G) are output signals output from the output terminal 13 of the delay generator.
[0004]
First, the setting data K is latched in synchronization with the latch signal, and the D / A converter 5 sets the threshold voltage V proportional to the setting data K._TIs output. And the threshold voltage V_TRepresents the unit voltage of the D / A converter 5 as V₀Then, it is expressed by the following equation.
[0005]
(Equation 1)
V_T= −K · V₀
Next, with the trigger signal input as a trigger, a current flows through the capacitor 3 and the ramp voltage V_RChanges. Ramp wave voltage V at time t_RIndicates that the current value of the current source 2 is I, the capacitance value of the capacitor 3 is C, and the rising time of the trigger signal is t.₀Then, it is expressed by the following equation.
[0006]
(Equation 2)
V_R= − (I / C) · (t−t₀)
Next, the comparator 6 determines the ramp wave voltage V_RAnd threshold voltage V_TDetects a match with Time t₀From ramp voltage V_RAnd threshold voltage V_TDelay time t until the output signal rises when_dIs expressed by the following equation from the equations (Equation 1) and (Equation 2).
[0007]
(Equation 3)
t_d= (KV₀・ C) / I
This output signal falls after the time constant τ of one shot 7 has elapsed. Further, the capacitor 3 is leaked by the leak signal, and the ramp wave voltage V_RIs initialized. As described above, the conventional delay generator can generate a delay time proportional to the setting data K expressed by the equation (3).
[0008]
[Problems to be solved by the invention]
By the way, with the performance enhancement of the frequency synthesizer, a delay time proportional to a fraction in which both the numerator and the denominator are variable is required. Such a delay time proportional to the fraction is required, for example, when extracting a signal having no jitter from the output signal of the accumulator, or when reducing the spurious of a fractional-N PLL frequency synthesizer. is there.
[0009]
However, the conventional delay generator has a delay time t proportional to the setting data K, as shown in equation (3)._dCan occur, but a delay time proportional to the fraction cannot occur. Further, as shown in Expression 3, the delay time t_dIs a circuit constant V₀, C, and I, the delay time t_dIn order to improve the absolute accuracy of₀, C and I are indispensable.
[0010]
According to the equation (3), it is possible to generate a delay time proportional to a fraction by changing the current value I of the current source 2, but the circuit constant V₀, C and I are directly the delay time t_dDelay time t_dTo improve the absolute accuracy of₀, C need to be adjusted. As described above, it is difficult for the conventional delay generator to be applied to a frequency synthesizer or the like that requires the accuracy of the delay time.
[0011]
Further, since the conventional multiplier uses the nonlinearity of the element or uses a mixer, a filter is required, so that the manufacturing cost is high.
[0012]
In addition, by using a conventional delay generator to generate pulses at intervals shorter than the cycle of the input signal, an attempt is made to obtain an output signal that is an integral multiple of the frequency of the input signal. Circuit constant V₀, C, and I must be adjusted. Even when the input frequency is fixed, the conventional delay generator uses the circuit constant V to improve the accuracy of the delay generator.₀, C and I need to be adjusted.
[0013]
Further, in the conventional delay generator, the threshold voltage V_TOf the operation time of the comparator 6 depending on the level of the_dIncludes the corresponding error. Also, the ramp voltage V_RIf the operation time of the comparator 6 varies due to the inclination of the_dIncludes the corresponding error. In order to suppress these errors, it is necessary to suppress variations in the operation time of the comparator 6. Specifically, it is necessary to suppress the dependency of the operation time of the comparator 6 on the threshold voltage and the dependency of the ramp wave voltage on the slope. However, it is necessary to supply a large current to the comparator 6, which reduces power consumption. It becomes a problem.
[0014]
The present invention has been made to solve the above-described problem, and has as its object to provide a delay generator capable of generating a delay time proportional to a fraction. It is another object of the present invention to provide a frequency synthesizer capable of extracting a jitter-free signal from an output signal of an accumulator. Another object of the present invention is to provide a multiplier that does not require a filter.
[0015]
[Means for Solving the Problems]
In order to achieve this object, in the present invention, a ramp generation circuit for generating a ramp voltage, threshold voltage supply means for supplying a threshold voltage, and comparing the ramp voltage with the threshold voltage, A delay circuit having a comparator circuit that generates an output pulse when the wave voltage matches the threshold voltage, wherein the ramp generator generates the ramp wave voltage having a two-step gradient as the ramp wave generation circuit.The ramp generation circuit uses the ramp wave voltage having a slope corresponding to the first data input, and the threshold voltage supply means corresponds to the threshold voltage slope corresponding to the second data input. At the same time, the first setting data is sent out as the first data input and the second setting data is sent out as the second data input using a threshold voltage generating circuit having a slope. A data selector unit for transmitting the second setting data as the first data input and transmitting 0 as the second data input is provided. As the ramp wave generating circuit, a current proportional to the first data input is provided. A first current source provided by the first current source, and a first capacitor charged by the first current source and having one end coupled to a predetermined voltage. A second current source for providing a current proportional to the second data input; a second current source charged by the second current source and having one end connected to a predetermined voltage. And a capacitor that generates the threshold voltage at the other end of the second capacitor.
[0018]
In this case, a current switch may be provided in parallel with the second current source.
[0020]
Also, a ramp generation circuit that generates a ramp voltage, a threshold voltage supply unit that supplies a threshold voltage, and the ramp voltage and the threshold voltage are compared by comparing the ramp voltage with the threshold voltage. A delay circuit having a comparator circuit for generating an output pulse, wherein the ramp wave generation circuit generates the ramp wave voltage having a two-step slope, and the ramp wave voltage is used as the ramp wave generation circuit. And a threshold voltage generating circuit that sets the slope of the threshold voltage to the slope corresponding to the second data input as the threshold voltage supply means. Sends the first setting data as the first data input and sends the value obtained by adding the addition data to the second setting data as the second data input; Provided data selector unit for sending a 0 with a second data input and sends the second setting data after a lapse of the constant time as the first data input,The ramp generation circuit includes a first current source for providing a current proportional to the first data input, and a first capacitor charged by the first current source and having one end coupled to a predetermined voltage. A second current source that generates a ramp wave voltage at the other end of the first capacitor and provides a current proportional to the second data input as the threshold voltage generator; A second capacitor charged by the second current source and having one end coupled to a predetermined voltage, and generating the threshold voltage at the other end of the second capacitor.Used.
[0021]
In these cases, the circuit constant included in the ramp generation circuit and the circuit constant included in the threshold voltage generation circuit may have the same value.
[0023]
Also, a ramp generation circuit that generates a ramp voltage, a threshold voltage supply unit that supplies a threshold voltage, and the ramp voltage and the threshold voltage are compared by comparing the ramp voltage with the threshold voltage. A delay circuit having a comparator circuit for generating an output pulse, wherein the ramp wave generation circuit generates the ramp wave voltage having a two-step slope, and the ramp wave voltage is used as the ramp wave generation circuit. The first setting data is sent out as the data input, and the threshold voltage supply means is used to supply a constant threshold voltage. The first setting data is sent as the data input. A data selector for transmitting the second setting data as a data input is provided;The ramp generation circuit includes a current source that selectively provides a current proportional to the data input, and a capacitor that is charged by the current source and has one end coupled to a predetermined voltage. Anything that generates the above ramp wave voltageUsed.
[0024]
Further, in the frequency synthesizer, an accumulator that inputs a clock signal and setting data and accumulates the setting data in synchronization with the clock signal, and outputs the most significant bit of the output of the accumulator or the overflow signal of the accumulator for a predetermined time. The above-mentioned delay generator for delaying is provided.
[0025]
In this case, the number of bits of the accumulator is n, and the value of the output signal of the accumulator immediately before the output signal of the most significant bit rises is θ._p, The setting data is K, and the cycle of the clock signal is T, the delay time of the most significant bit of the delay generator is ｛(2^n-1−θ_p) / K｝ · T.
[0026]
When the number of bits of the accumulator is n, the output signal of the accumulator is θ, the setting data is K, and the cycle of the clock signal is T, the delay time of the overflow signal of the delay generator is ｛(2ⁿ−θ) / K｝ · T.
[0027]
Further, in the multiplier, the plurality of delay generators for inputting the multiplied signal and generating a plurality of types of delay times, and the delay generator for inputting the multiplied signal and generating a delay in each of the plurality of delay generators. A distribution circuit for transmitting the timing and a logical sum means for calculating a logical sum of outputs of the plurality of delay generators are provided.
[0028]
In this case, as the plurality of delay generators, when a period of the multiplied signal is T, an arbitrary time is d, an integer of 2 or more is N, and an integer of 1 or more is M, N kinds of specific delays are set. A generator that generates a time d + (kM / N) T (k is any integer from 0 to N-1) may be used.
[0029]
BEST MODE FOR CARRYING OUT THE INVENTION
(First Embodiment of Delay Generator)
FIG. 1 is a diagram showing a delay generator according to the present invention. As shown in the figure, a ramp generation circuit 26 has a latch 16, a first current source (current switch array) 18 for providing a current corresponding to an output signal of the latch 16, and a terminal which is charged by the current source 18 and has one end connected to a predetermined voltage. And a switch 20 which is provided in parallel with the capacitor 22 and is turned on by an R-side leak signal input from an R-side leak signal input terminal 29. The voltage at one end of the capacitor 22 is a ramp wave. Voltage V_RIs output. The threshold voltage generating circuit 27 serving as a threshold voltage supply means is charged by the latch 17, a second current source (current switch array) 19 for providing a current corresponding to the output signal of the latch 17, and one end thereof. A second capacitor 23 coupled to a predetermined voltage, and a switch 21 provided in parallel with the capacitor 23 and turned on by a T-side leak signal input from a T-side leak signal input terminal 32, as a voltage at one end of the capacitor 23 Threshold voltage V_TIs output. The ramp generation circuit 26 and the threshold voltage generation circuit 27 have the same circuit configuration, and the circuit constant included in the ramp generation circuit 26 and the circuit constant included in the threshold voltage generation circuit 27 have the same value. That is, the capacitance value C of the capacitors 22 and 23 and the unit current I of the current sources 18 and 19₀Are the same value. This can be easily realized by integrating the ramp generation circuit 26 and the threshold voltage generation circuit 27 on the same substrate. A common clock signal input terminal 28 is connected to the ramp wave generation circuit 26 and the threshold voltage generation circuit 27. The data selector section 89 includes selectors 14, 15, and 88, and the data input D which is the first data input._RThe setting data S that is the first setting data input from the setting data S input terminal 30 and the setting data K or 0 that is the second setting data input from the setting data K input terminal 33 And the second data input, data input D_TIs sent to the threshold voltage generation circuit 27. The comparator 24, which is a comparison circuit, outputs a ramp wave voltage V_RAnd threshold voltage V_TAnd the ramp wave voltage V_RAnd threshold voltage V_TA pulse which rises at the timing when the signal matches with is output. The one-shot 25 receives an output pulse of the comparator 24 and outputs an output pulse having a pulse width corresponding to the time constant τ to the output terminal 35.
[0030]
FIG. 2 is a time chart showing an operation example of the delay generator shown in FIG. 2A shows a clock signal input from the clock signal input terminal 28, and FIG._T, (C) is the data input D_R, (D) is a T-side enable signal input from a T-side enable signal input terminal 34, (e) is an R-side enable signal input from an R-side enable signal input terminal 31, and (f) is a threshold voltage V_T, (G) is the ramp voltage V_R, (H) are output signals output from the output terminal 35, (i) is a T-side leak signal, and (j) is an R-side leak signal.
[0031]
In the initial state, the R-side enable signal and the T-side enable signal are low, and the selectors 14, 15, and 88 select the lower side as shown in FIG. At this time, data input D_RAnd data input D_TIs input as 0. A series of processes for generating a delay starts by raising an R-side enable signal and a T-side enable signal. Accordingly, the selectors 14, 15, and 88 all select the upper side, and the data input D_RIs input with setting data S, and data input D_TIs input with setting data K. Subsequently, at the rising edge of the clock signal input first after the rising edge of the R-side enable signal, the latch 16_R= S, and the latch 17 outputs D_T= K is output. In synchronization with this, the current sources 18 and 19 respectively output currents SI proportional to the set data S.₀, Current KI proportional to setting data K₀Is provided, the ramp voltage V having a slope proportional to the setting data S_RAnd a threshold voltage V having a slope proportional to the setting data K_TIs started. Further, the time when the next clock signal rises is t.₀, And the clock cycle is T, time t (t₀−T ≦ t ≦ t₀) The ramp voltage V_RIs represented by the following equation.
[0032]
(Equation 4)
V_R=-(SI₀/ C) · (tt₀+ T)
At time t (t₀−T ≦ t ≦ t₀Threshold voltage V)_TIs represented by the following equation.
[0033]
(Equation 5)
V_T=-(KI₀/ C) · (tt₀+ T)
Further, from the equations (4) and (5), the time t₀Ramp voltage V at_RAnd threshold voltage V_TAre represented by the following equations.
[0034]
(Equation 6)
V_R=-(SI₀/ C) · T
[0035]
(Equation 7)
V_T=-(KI₀/ C) · T
Time t₀By this time, control is performed to lower the T-side enable signal, and the selectors 15a and 88a select the lower side._RHas set data K, data input D_TIs input to each of them. Therefore, at time t₀Latch 16 is D_R= K and the latch 17_T= 0, respectively, and in synchronization with this, the ramp wave voltage V proportional to the setting data S_RChanges to a slope proportional to the setting data K. And time t₀Thereafter (t₀≦ t) ramp wave voltage V_RIs represented by the following equation.
[0036]
(Equation 8)
V_R=-(SI₀/C).T-(KI₀/ C) · (tt₀)
Therefore, the ramp generation circuit 26 generates a ramp voltage V having a two-step gradient._RTo occur. On the other hand, time t₀Thereafter (t₀≤ t) threshold voltage V_TIs the voltage of equation (7), ie, time t.₀Is maintained.
[0037]
Then, the comparator 24 detects the ramp voltage V_RAnd threshold voltage V_TAnd a ramp wave voltage V_RAnd threshold voltage V_TA pulse which rises at the timing when the signal matches with is output. At this time, time t₀From ramp voltage V_RAnd threshold voltage V_TDelay time t until the output signal rises when_dIs expressed by the following equation from the equations (7) and (8).
[0038]
(Equation 9)
t_d= {(KS) / K} · T
Thereafter, since the switches 20 and 21 are turned on at the rise of the R-side leak signal and the T-side leak signal, the capacitors 22 and 23 are leaked and the ramp voltage V_R, Threshold voltage V_TReturns to the initial value. The timing of the R-side leak signal and the T-side leak signal is based on the ramp voltage V_RAnd threshold voltage V_TIt suffices that after the match is detected and the output signal is output. In FIG.₀+ T rises at time t₀Although it is set to fall at + 2T, the output signal may be fed back as each leak signal.
[0039]
As described above, the ramp wave generating circuit 26 has a ramp wave voltage V having a two-stage slope, that is, a slope proportional to the setting data S and a slope proportional to the setting data K._RIs generated, and the setting data S and the setting data K are applied to the data input D, respectively._TOr data input D_RSince the delay generator is an arbitrarily settable value, the delay generator has a delay time t proportional to the fraction (K−S) / K in which both the numerator and the denominator represented by the equation (9) are variable._dCan occur. The circuit constants included in the ramp generation circuit 26 and the threshold voltage generation circuit 27, that is, the capacitance value C of the capacitors 22 and 23 and the unit current I of the current sources 18 and 19₀Have the same value, (Equation 9) does not include circuit constants. Therefore, the value of each circuit constant is equal to the delay time t._dDoes not need to be adjusted even if the value of each circuit constant is different from the design value. Further, since the operations of the ramp generation circuit 26 and the threshold voltage generation circuit 27 are synchronized with the clock signal input from the outside, the delay time t_dCan be improved in absolute accuracy. Further, when the setting data K is fixed, the ramp wave voltage V_RAnd threshold voltage V_TAnd the ramp wave voltage V at the time_RSlope and threshold voltage V_TAre constant regardless of the setting data S. This can greatly reduce the required performance of the comparator 24. This is because the comparator 24 generally has the ramp voltage V_RSlope and threshold voltage V_TThe operation time changes depending on the voltage value of_dHowever, in order to suppress this, it is necessary to carefully design the comparator 24 and an increase in power consumption cannot be avoided.
[0040]
(Second Embodiment of Delay Generator)
FIG. 3 is a diagram showing another delay generator according to the present invention. As shown in the figure, a ramp generation circuit 26a includes a latch 16a, a first current source 18a for providing a current corresponding to an output signal of the latch 16a, a first current source 18a charged by the current source 18a and having one end coupled to a predetermined voltage. And a switch 20a provided in parallel with the capacitor 22a and turned on by an R-side leak signal input from an R-side leak signal input terminal 29a._RIs output. The threshold voltage generating circuit 27a as a threshold voltage supply means is charged by the latch 17a, the second current source 19a for providing a current corresponding to the output signal of the latch 17a, and the current source 19a, and has one end coupled to a predetermined voltage. A second capacitor 23a, a current switch 36 connected in parallel with the current source 19a, and a switch 21a provided in parallel with the capacitor 23a and turned on by a T-side leak signal input from a T-side leak signal input terminal 32a. And the threshold voltage V as the voltage at one end of the capacitor 23a._TIs output. The ramp generation circuit 26 and the threshold voltage generation circuit 27 have substantially the same circuit configuration, and the circuit constant included in the ramp generation circuit 26a and the circuit constant included in the threshold voltage generation circuit 27a have the same value. . That is, the capacitance value C of the capacitors 22a and 23a and the unit current I of the current sources 18a and 19a₀Are the same value. This can be easily realized by integrating the ramp generation circuit 26a and the threshold voltage generation circuit 27a on the same substrate. A common clock signal input terminal 28a is connected to the ramp wave generation circuit 26a and the threshold voltage generation circuit 27a. The data selector 89a is composed of selectors 14a, 15a and 88a._RThe setting data S input from the setting data S input terminal 30a and the setting data K or 0 input from the setting data K input terminal 33a are sent to the ramp generation circuit 26a, and the data input D_TIs transmitted to the threshold voltage generation circuit 27a. The comparator 24a has a ramp voltage V_RAnd threshold voltage V_TAnd the ramp wave voltage V_RAnd threshold voltage V_TA pulse which rises at the timing when the signal matches with is output. The one-shot 25a receives the output pulse of the comparator 24a and outputs an output signal of a pulse having a pulse width corresponding to the time constant τ from the output terminal 35a.
[0041]
FIG. 4 is a time chart showing an operation example of the delay generator shown in FIG. 4A shows a clock signal input from the clock signal input terminal 28a, and FIG._T, (C) is the data input D_R, (D) is a T-side enable signal input from a T-side enable signal input terminal 34a, (e) is an R-side enable signal input from an R-side enable signal input terminal 31a, and (f) is a threshold voltage V_T, (G) is the ramp voltage V_R, (H) are output signals output from the output terminal 35a, (i) is a T-side leak signal, and (j) is an R-side leak signal.
[0042]
The operation of the delay generator shown in FIG. 3 is different from the operation of the delay generator shown in FIG._TAre only slightly different. That is, when the value smaller than the setting data K is α, the current of the current switch 36 is αI₀Then, at time t₀Thereafter (t₀≤ t) threshold voltage V_TIs represented by the following equation.
[0043]
(Equation 10)
V_T=-｛(K + α) I₀/ C｝ ・ T
On the other hand, the ramp voltage V_RIs the same as the delay generator shown in FIG.₀Thereafter (t₀≦ t) ramp wave voltage V_RIs represented by Expression (8). Therefore, at time t₀From ramp voltage V_RAnd threshold voltage V_TDelay time t until the output signal rises when_{d ′}Is expressed by the following equation from the equations (8) and (10).
[0044]
(Equation 11)
t_{d ′}= {(K + α-S) / K} · T
Delay time t in equation (11)_{d ′}And delay time t of equation (9)_dIs (α / K) T, which is a constant in the use of the delay generator in which the setting data K is semi-fixed. That is, in such a usage, the current value αI of the current switch 36 included in the threshold voltage generation circuit 27a is₀Is the delay time t without it_dMeans that a constant time is added. Thus, the addition of the constant time to the delay time generated by the delay generator can be freely performed in the application to the frequency synthesizer and the application to the multiplier. This is because in the frequency synthesizer and the multiplier, only the pulse interval of the pulse output from the delay generator is significant, and the time can be arbitrarily selected. As described above, adding a constant time to the delay time of the delay generator can increase the accuracy of the delay time generated by adding an appropriate constant time when an extremely small delay time needs to be generated. There are advantages.
[0045]
Although the current switch 36 is provided in FIG. 3, the current switch 36 is removed and₀Data input D to -T_RAnd the data input D_TA value K + α obtained by adding the addition data α smaller than the setting data K to the setting data K is sent out at time t.₀Data input D_RAnd the data input D_TBy providing a data selector unit that sends 0 as the delay time t, the delay time t_dTo the same constant time.
[0046]
(Third Embodiment of Delay Generator)
FIG. 5 is a diagram showing another delay generator according to the present invention. As shown in the figure, the ramp generation circuit 26b is charged by the latch 16b, a current source (current switch array) 18b for providing a current corresponding to the output signal of the latch 16b, and the current source 18b, and has one end coupled to a predetermined voltage. The capacitor 22b includes a switch 20b provided in parallel with the capacitor 22b and turned on by an R-side leak signal input from an R-side leak signal input terminal 29b, and a ramp wave voltage V as one end of the capacitor 22b._RIs output. Further, a clock signal input terminal 28b is connected to the ramp generation circuit 26b. On the other hand, a constant threshold voltage V is supplied from a threshold voltage input terminal 37 which is a threshold voltage supply means._TIs given. The data selector 89b is composed of selectors 14b and 88b._RThe setting data S input from the setting data S input terminal 30b and the setting data K or 0 input from the setting data K input terminal 33b are transmitted to the ramp generation circuit 26b. The comparator 24b, which is a comparison circuit, outputs a ramp voltage V_RAnd threshold voltage V_TAnd the ramp wave voltage V_RAnd threshold voltage V_TA pulse which rises at the timing when the signal matches with is output. The one-shot 25b receives the output pulse of the comparator 24b and outputs an output pulse having a pulse width corresponding to the time constant τ to the output terminal 35b.
[0047]
FIG. 6 is a time chart showing an operation example of the delay generator shown in FIG. FIG. 6A shows a clock signal input from the clock signal input terminal 28b, and FIG._R, (E) are R-side enable signals input from the R-side enable signal input terminal 31b, and (f) is a threshold voltage V_T, (G) is the ramp voltage V_R, (H) is an output signal output from the output terminal 35b, and (j) is an R-side leak signal input from the R-side leak signal input terminal 29b.
[0048]
The operation of the delay generator shown in FIG. 5 is different from the operation of the delay generator shown in FIG. 1 in that the threshold voltage generation circuit 27 is removed and the threshold voltage V_TIs different. Time t₀Thereafter (t₀≦ t) ramp wave voltage V_RIs given by equation (8), so that the ramp voltage V_RAnd threshold voltage V input from outside_TDelay time t until the output signal rises when_dCan be represented by the following equation.
[0049]
(Equation 12)
t_d= (-V_TC / KI₀)-(S / K) · T
In the usage of the delay generator in which the setting data K is semi-fixed, the first term on the right side of the equation (12) is a constant. As described above, the addition of the constant time to the delay time generated by the delay generator can be freely performed in the application to the frequency synthesizer and the application to the multiplier. In such an application, the accuracy of the pulse interval output from the delay generator is required, but the time of the output pulse has no meaning. Also, the threshold voltage V_TIs a parameter that affects only the addition of the constant time, so that the threshold voltage V is applied to the application to the frequency synthesizer and the application to the multiplier._TDoes not require high precision.
[0050]
(First Embodiment of Frequency Synthesizer)
FIG. 7 is a diagram showing a frequency synthesizer according to the present invention. As shown in the figure, the frequency synthesizer includes an accumulator 40, a ramp generation circuit, a threshold voltage generation circuit, a comparator, a delay generator main body 41 having one shot, a data conversion circuit 42, and a control circuit 43. The accumulator 40 includes an adder 38 and a latch 39. The setting data K input from the setting data K input terminal 45 is set in the adder 38 of the accumulator 40, the delay generator main body 41, and the data conversion circuit 42. The clock signal input from the clock signal input terminal 44 is supplied to the latch 39 of the accumulator 40 and the delay generator main body 41.
[0051]
FIG. 8 is a diagram for explaining the operation of the frequency synthesizer shown in FIG. The number of bits n of the accumulator 40 is 3, and the setting data K is 3. Most significant bit output signal θ of output signal θ of accumulator 40_MSBIs 2ⁿK = 3 pulses in a time period (8T) of = 8 clock cycles. Therefore, its average frequency f₀Sets the clock frequency to f_CLKThen, it is expressed by the following equation.
[0052]
(Equation 13)
f₀= (K / 2ⁿ) F_CLK
The accumulator 40 by itself is the simplest form of a direct digital synthesizer, and many other types of direct digital synthesizers are also used for calculating phase signals. However, as shown in FIG._MSBContains large jitter. In the observation of the frequency spectrum, the jitter appears as a large spurious component (unwanted wave component), so it is difficult to apply the accumulator 40 alone to the local oscillator for the wireless communication device. In order to suppress the spurious component, a method of generating a sine wave as an output using a ROM is used in the most common direct digital synthesizer. As another method for suppressing the spurious component, a means of phase interpolation is known (reference: V. Reinhardt et al., "A short survey of frequency synthesizing techniques technology", in Proc. , Pp. 355-365, May 1986).
[0053]
As shown in FIG. 8, the means for phase interpolation is the output signal θ of the accumulator 40._MSBIs delayed for each pulse and the delayed output signal θ_idealGenerate. Delay time δ of this pulse_tIs the output signal θ_MSBIs the value of the output signal θ just before_pThen, it is expressed by the following equation.
[0054]
[Equation 14]
δ_t= ｛(2^n-1−θ_p) / K｝ ・ T
For example, as shown in FIG. 8, the first output signal θ_MSBValue θ of the output signal just before_pIs 3, the first output signal θ_MSBAbout δ_t= {(4−3) / 3} · T = T / 3 (calculated by equation (14)), the delay output signal θ_idealMatches the first pulse of
[0055]
As a conventional means for phase interpolation, a delay generator in which a threshold voltage generation circuit and a ramp wave generation circuit shown in the related art are configured by different circuits (references: H. Nosaka, T. Nakagawa, and A. Yamagishi, "A phase interpolation direct digit1 synthesizer with a digita11y contro11ed de1day generator", in 1997 Symp. V. N. Kochemasov and A. N. Fadeev, "Digital-computer synth. Esizers of two-ever1 signaals with phase-error compensation ", Te1communications and radio engineering, vol. 36/37, pp. 55-59, Oct. 1982). However, these delay generators need to adjust the delay time (delay amount) in order to increase the accuracy, and there is a problem that it is difficult to adjust the unit delay time.
[0056]
Since the delay generator according to the present invention as shown in FIGS. 1, 3 and 5 can obtain an arbitrary delay time without any adjustment, as shown in FIG. A direct digital synthesizer using a generator as a means for phase interpolation can obtain a low spurious output signal without adjustment.
[0057]
In the frequency synthesizer shown in FIG. 7, the output signal θ of the accumulator 40 is input to the data conversion circuit 42 and the control circuit 43. The control circuit 43 generates an R-side enable signal and a T-side enable signal from the output signal θ. T side enable signal is output signal θ_MSBRises one clock before rising, and the pulse width is output as a signal of one clock. The R-side enable signal is output with the pulse width of the T-side enable signal being 2 clocks. Output signal θ_MSBThe T-side enable signal that rises one clock before can be calculated from the output signal θ._MSBA signal obtained by correcting the pulse width of (1) to one clock may be used as the T-side enable signal. In this case, since one clock differs from the T-side enable signal shown in FIG. 9E, all other signals input to the delay generator main body 41 may be delayed by one clock. The T-side enable signal and the R-side enable signal function as trigger signals that cause the delay generator main body 41 to start delay generation as described above. Data input D to be sent to delay generator body 41_RIs set by the data conversion circuit 42. As described above, the data conversion circuit 42 and the control circuit 43 play the role of the data selectors 89, 89a, 89b of the delay generator of the present invention shown in FIGS. 1, 3, and 5. The delay time of the delay generator main body 41 is expressed by the following equation (9), while the delay time δ required by the direct digital synthesizer is_tIs represented by Expression (14). Where the value θ_pIs represented by θ-K from its definition. Therefore, equation (14) can be represented by the following equation.
[0058]
(Equation 15)
δ_t= [｛K- (θ-2^n-1)｝ / K] ・ T
Comparing equation (15) with equation (9), it can be seen that the setting data S set in the delay generator main body 41 may be calculated by the following equation.
[0059]
(Equation 16)
S = θ-2^n-1
That is, the data conversion circuit 42 first receives the output signal θ of the accumulator 40, calculates the subtraction of Expression (16), and outputs the setting data S. Further, at the next clock, the data conversion circuit 42 outputs the data input D._RIs output as setting data K. Expression (16) can be realized by discarding the most significant bit from the output signal θ and extracting the lower n−1 bits in the n-bit binary operation. The R-side leak signal and the T-side leak signal are used by feed-hacking the output signal of the delay generator main body 41.
[0060]
With such a configuration, the delay generator main body 41 has the delay time δ shown in Expression (14)._tThis frequency synthesizer outputs a square wave with a small spurious component whose fundamental frequency is represented by the following equation (13).
[0061]
FIG. 9 is a time chart showing an operation example of the frequency synthesizer shown in FIG. 9A shows a clock signal, FIG. 9B shows an output signal θ of the accumulator 40, and FIG. 9C shows an output signal θ of the accumulator 40._MSB, (D) is the ramp voltage V_R, (E) is the T-side enable signal, and (f) is the threshold voltage V._T, (G) are output signals output from the output terminal 46, (h) is a T-side leak signal, and (i) is an R-side leak signal. The number of bits n of the accumulator 40 is 3, and the setting data K is 3. Also, the output signal θ_MSBThe timing one clock cycle after the rising edge of the clock signal at time t₀To match. Inside the delay generator body 41, the output signal θ_MSBAt the same time as the rising edge of the first pulse, the ramp voltage V has a slope proportional to S = 6−4 = 2 (calculated from equation (16))._RIs generated. At the same time, the threshold voltage V has a slope proportional to K = 3._TChange the value of. Time of rising of next clock (time t of delay generator₀), The ramp voltage V_RChanges to a slope proportional to K = 3, while the threshold voltage V_TIs retained. Time t₀Delay time until the output signal rises from_tBecomes (１ ／) T as calculated from the equation (9). The output signal is fed back as a T-side leak signal and an R-side leak signal, and the threshold voltage V_TAnd ramp wave voltage V_RIs initialized.
[0062]
When a toggle flip-flop (T-FF) is added to the output terminal, it is possible to obtain a rectangular wave synthesizer output with a duty ratio of 50%. In this case, the fundamental frequency is the average frequency f shown in Expression (13).₀Half of
[0063]
The point to be noted in FIG. 9 is that the ramp wave voltage V_RIs the threshold voltage V_TAt the time when the output signal rises, the threshold voltage V_TIs always the same voltage and the ramp voltage V_RIs always constant. The actual operation time of the comparator has a dependency on the threshold voltage and a dependency on the ramp voltage slope, but since this does not affect the delay time, the pulses of the output signal of the frequency synthesizer are ideally arranged at equal intervals.
[0064]
As described in the description of the delay generator shown in FIGS. 3 and 5, in application to a frequency synthesizer, an arbitrary constant time can be added to the delay time generated by the delay generator. That is, the threshold voltage V of the delay generator_TMay have a constant voltage deviation, or the threshold voltage generation circuit may be removed to remove the threshold voltage V_TMay be externally input as a constant voltage. In frequency synthesizer applications, the delay generator may generate a very small delay time depending on the frequency setting, and the threshold voltage V_TBy adding an appropriate voltage, it is not necessary to generate an extremely small delay time, and there is an advantage that the accuracy of the delay time can be easily obtained.
[0065]
As described above, in the frequency synthesizer shown in FIG. 7, the delay generator for generating the delay time proportional to the fraction in which both the numerator and the denominator shown in FIG. 1 and the like are variable is used as a means for phase interpolation in the direct digital synthesizer. Therefore, a signal without jitter can be extracted from the output signal of the accumulator. Further, since all required delay times can be obtained without adjustment, a low spurious output signal can be generated. In addition, since the delay generator main body 41 performs an operation of fixing the setting data K in a semi-fixed manner, the performance requirement for the comparator can be greatly eased. This is effective in reducing the power consumption and cost of the entire frequency synthesizer. Also, there is no need to adjust circuit constants in the delay generator specifically for the clock frequency.
[0066]
(Second Embodiment of Frequency Synthesizer)
By the way, until now, the output signal θ_MSBHas been described as the reference timing of the T-side enable signal and the R-side enable signal of the delay generator main body 41. However, the frequency synthesizer can also be configured by using the overflow signal of the accumulator as the reference timing. Can be.
[0067]
FIG. 10 is a diagram showing another frequency synthesizer according to the present invention. As shown in the figure, the frequency synthesizer includes an accumulator 40a, a delay generator main body 41a, a data conversion circuit 42a, and a control circuit 43a. The accumulator 40a includes an adder 38a and a latch 39a. The setting data K input from the setting data K input terminal 45a is set in the adder 38a of the accumulator 40a, the delay generator main body 41a, and the data conversion circuit 42a. The clock signal input from clock signal input terminal 44a is applied to latch 39a of accumulator 40a and delay generator main body 41a. The overflow signal OF of the accumulator 38a is sent to the data conversion circuit 42a and the control circuit 43a.
[0068]
FIG. 11 is a diagram for explaining the operation of the frequency synthesizer shown in FIG. The number of bits n of the accumulator 40a is 3, and the setting data K is 3. The overflow signal OF of the accumulator 40a is 2ⁿK = 3 pulses are included in time 8T of = 8 clock cycles. Therefore, its average frequency f₀Is represented by Expression (13). The overflow signal OF is delayed for each pulse by the delay generator main body 41a, and the delayed output signal θ_idealAre re-arranged into equally spaced pulse trains. The delay time δ_tIs represented by the following equation.
[0069]
[Equation 17]
δ_t= ｛(2ⁿ−θ) / K｝ · T
On the other hand, the delay time t generated in the delay generator main body 41a_dIs represented by equation (9), so the setting data S is calculated by the following equation.
[0070]
(Equation 18)
S = K + θ-2ⁿ
That is, in the data conversion circuit 42a, the operation of the expression (18) may be performed and transmitted to the delay generator main body 41a. In an n-bit binary operation, the expression 2ⁿHas no meaning, so that S = K + θ. Further, considering the operation of the accumulator 40a, K + θ is “the output signal θ after the next clock cycle when the overflow signal OF rises”. That is, the output signal θ at the next timing can be directly used as the setting data S.
[0071]
FIG. 12 is a time chart showing an operation example of the frequency synthesizer shown in FIG. 12A shows a clock signal, FIG. 12B shows an output signal θ of the accumulator 40a, FIG. 12C shows an overflow signal OF of the accumulator 40a, and FIG._R, (E) is the T-side enable signal, and (f) is the threshold voltage V._T, (G) are output signals output from the output terminal 46a, (h) is a T-side leak signal, and (i) is an R-side leak signal. The number of bits n of the accumulator 40a is 3, and the setting data K is 3. Further, the timing one clock cycle after the rise of the overflow signal OF is set to the time t in the delay generator main body 41a.₀To match. Further, inside the delay generator main body 41a, the ramp wave voltage V has a slope proportional to S = 6 + 3-8 = 1 (calculated by the equation (18)) at the same time as the rising edge of the first pulse of the overflow signal OF._RIs generated. At the same time, the threshold voltage V has a slope proportional to K = 3._TTo change the voltage. Time of rising of next clock (time t of delay generator₀), The ramp voltage V_RChanges to K = 3, while the threshold voltage V_TIs retained. Time t₀Delay time until the output signal rises from_tBecomes (2/3) T as calculated from Expression (9). The output signal is fed back as a T-side leak signal and an R-side leak signal, and the threshold voltage V_TAnd ramp wave voltage V_RIs initialized.
[0072]
If a toggle flip-flop (T-FF) is added to the output terminal, it is possible to obtain a rectangular wave synthesizer signal with a duty ratio of 50%. In this case, the fundamental frequency is the average frequency f shown in Expression (13).₀Half of
[0073]
The point to be noted in FIG._RIs the threshold voltage V_TAt the time when the output signal rises, the threshold voltage V_TIs always the same voltage and the ramp voltage V_RIs always constant. The actual operating time of the comparator has a threshold voltage dependency and a ramp voltage slope dependency, but since this does not affect the delay time, the pulses of the frequency synthesizer output signal are ideally arranged at equal intervals. .
[0074]
As described in the description of the delay generator shown in FIGS. 3 and 5, in the application to the frequency synthesizer, an arbitrary constant time can be added to the delay time generated by the delay generator main body 41a. That is, the threshold voltage V of the delay generator body 41a_TMay have a constant voltage deviation, or the threshold voltage generation circuit may be removed and V_TMay be externally input as a constant voltage. In addition, in an application to a frequency synthesizer, the delay generator may generate an extremely small delay time depending on the frequency setting._TBy adding an appropriate voltage to the delay time, there is no need to actually generate an extremely small delay time, and there is an advantage that the accuracy of the delay time can be easily obtained.
[0075]
(Embodiment of multiplier)
FIG. 13 is a diagram showing a multiplier according to the present invention. In the figure, reference numeral 47 denotes a T-FF serving as a distribution circuit, 48 to 53 are D-FFs, 54 to 59 are capacitors having the same capacitance value C, 60 to 65 are switches, and 66 and 68 are current values I.₀Current sources (current switches), 67 and 69 have a current value of 3I₀Current source (current switch), 70 to 75 have a current value of 4I₀Current sources (current switches), 76 to 79 are comparators, 80 to 83 are pulse width adjustment circuits, 84 is an OR gate as OR means, 85 is a one-shot multivibrator (one shot), 86 is a clock signal input A terminal 87 is an output terminal. This multiplier has N types of specific delay times t, where T is the cycle of the multiplied signal, d is an arbitrary time, N is an integer of 2 or more, and M is an integer of 1 or more._d= D + (kM / N) T (k is any integer from 0 to N-1), so that the frequency of the input multiplied signal is N / M times higher. Get the signal.
[0076]
The multiplier shown in FIG. 13 is a configuration example of a doubler when d = (1/4) T, N = 2, and M = 1, and N = 2 types of specific delay times t_dAre generated, that is, two delay generators, that is, first to fourth delay generators (delay generators having comparators 76 to 79, respectively). The first delay generator has a ramp voltage V_R= V1, threshold voltage V_T= V3, and the second delay generator uses the ramp voltage V_R= V2, threshold voltage V_T= V3, and the third delay generator uses the ramp voltage V_R= V4, threshold voltage V_T= V6, and the fourth delay generator uses the ramp voltage V_R= V5, threshold voltage V_T= V6. Specific delay time t_d= (1/4) T is generated by the second and fourth delay generators and has a specific delay time t_d= (3/4) T is generated by the first and third delay generators.
[0077]
FIG. 14 is a time chart showing an operation example of the multiplier shown in FIG. 14A shows a clock signal, FIG. 14B shows a non-inverted signal CLK1 of the T-FF 47, FIG. 14C shows an inverted signal CLK2 of the T-FF 47, and FIG. 14D shows first and second delay generators. Voltages V1 to V3, (e) are voltages V4 to V6 of the third and fourth delay generators, and (f) is an output signal output from output terminal 87.
[0078]
The operation of the first and second delay generators will be described below. When the non-inverted signal CLK1 is in the high state, the voltage V1 becomes I₀, The voltage V2 is 3I₀, The voltage V3 is 4I₀Becomes a ramp wave having a slope proportional to. During the period of the clock period T from the rise of the non-inverted signal CLK1, the voltage ratio always changes with the voltage ratio of V1: V2: V3 = 1: 3: 4, and this voltage ratio is maintained until the moment when the non-inverted signal CLK1 falls. . When the non-inverted signal CLK1 falls (that is, when the inverted signal CLK2 rises), the voltage V3 holds that voltage, while the voltages V1 and V2 become 4I.₀Becomes a ramp wave having a slope proportional to. After a lapse of time (1/4) T from the rise of the inverted signal CLK2, the voltage V2 matches the voltage V3. This is equivalent to setting K = 4 and S = 3 in Expression (9). Further, after a lapse of time (3/4) T from the rise of the inverted signal CLK2, the voltage V1 matches the voltage V3. This is equivalent to setting K = 4 and S = 1 in equation (9).
[0079]
The operation of the third and fourth delay generators is only different from the operation of the first and second delay generators described above in clock cycle T. As described above, since the four delay generators sequentially generate the output signal pulses every time (１ ／) T, it can be seen that the multiplier shown in FIG. 13 performs the double operation.
[0080]
It should be noted in FIG. 14 that the ramp wave voltage V_R(Voltages V1, V2, V4, V5) are equal to the threshold voltage V_T(Voltages V3 and V6), and when the output signal rises, the threshold voltage V_TIs always the same voltage and the ramp voltage V_RIs always constant. The actual operating time of the comparator has a threshold voltage dependency and a ramp voltage slope dependency, but since this does not affect the delay time, the pulses of the output signal of the multiplier are ideally arranged at equal intervals. .
[0081]
As described in the description of the delay generator shown in FIGS. 3 and 5, in the application of the delay generator to the multiplier, the threshold voltage V_TAccuracy is not required. That is, the threshold voltage V_TThe current values of the current switches 72 and 75 for generating the voltages V3 and V6 corresponding to₀The voltage V3 and the voltage V6 may be externally input as constant voltages.
[0082]
As described above, in the multiplier shown in FIG. 13, by using a delay generator similar to the delay generator shown in FIG. 1 or the like as means for generating pulses at intervals shorter than the cycle of the input signal, As compared with the conventional multiplier using the non-linearity and the conventional multiplier using the mixer, a filter is not required and multi-stage connection is possible without a filter. This is effective in expanding the frequency range of the multiplier and reducing the circuit scale. In addition, since pulses can be generated accurately at equal intervals without adjustment, an output signal with low jitter and low spurious can be obtained. Further, as compared with a conventional multiplier using a PLL frequency synthesizer, the circuit scale is small and the power consumption is low. Also, there is no need to adjust circuit constants in the delay generator specifically for the input frequency. The use of a delay generator similar to the delay generator shown in FIG. 1 and the like is effective in preventing deviations in circuit constants from design values and fluctuations in power supply from causing deterioration of spurious characteristics. Further, since the ramp voltage has a two-step gradient, there is an advantage that the threshold voltage at the time when the comparator operates is constant and the ramp voltage gradient is constant. This greatly eases the performance requirements for the comparator, and is effective in reducing the power consumption and cost of the entire multiplier.
[0083]
In the above-described embodiment, the value α and the addition data α are smaller than the setting data K. However, these values may be set to arbitrary values.
[0084]
【The invention's effect】
As described above, the delay generator according to the present invention can generate a delay time proportional to a fraction.
[0085]
When a current switch is provided in parallel with the second current source, a constant time can be added to the delay time.
[0086]
At the same time, the first setting data is sent out as the first data input, and the value obtained by adding the addition data to the second setting data is sent out. After a lapse of a predetermined time, the second setting data is sent out as the first data input. When a data selector for transmitting data and transmitting 0 as the second data input is provided, a constant time can be added to the delay time.
[0087]
When the circuit constant included in the ramp generation circuit and the circuit constant included in the threshold voltage generation circuit have the same value, it is not necessary to adjust the circuit constant.
[0088]
Further, in the frequency synthesizer according to the present invention, a signal without jitter can be extracted from the output signal of the accumulator.
[0089]
The number of bits of the accumulator is n, and the value of the output signal of the accumulator immediately before the output signal of the most significant bit rises is θ._p, The setting data is K, and the period of the clock signal is T, the delay time of the most significant bit of the delay generator is ｛(2^n-1−θ_p) / K｝ · T, the performance requirement of the comparator of the delay generator can be greatly relaxed, and the operation time of the comparator does not affect the delay time. Are ideally arranged at equal intervals, and there is no need to adjust circuit constants in the delay generator specifically for the clock frequency.
[0090]
When the number of bits of the accumulator is n, the output signal of the accumulator is θ, the setting data is K, and the cycle of the clock signal is T, the delay time of the overflow signal of the delay generator is ｛(2ⁿ-Θ) / K｝ · T, the performance requirements of the delay generator for the comparator can be greatly relaxed, and the operation time of the comparator does not affect the delay time. The pulses of the output signal are ideally arranged at regular intervals, and there is no need to adjust circuit constants in the delay generator specifically for the clock frequency.
[0091]
Further, the multiplier according to the present invention does not require a filter.
[0092]
Further, as a plurality of delay generators, when the cycle of the multiplied signal is T, an arbitrary time is d, an integer of 2 or more is N, and an integer of 1 or more is M, N kinds of specific delay times d + ( k · M / N) T (where k is any integer from 0 to N−1) can be used to greatly reduce the performance requirements of the delay generator comparator. Since the operating time of the multiplier does not affect the delay time, the pulses of the output signal of the multiplier are ideally arranged at equal intervals, and it is necessary to adjust the circuit constants in the delay generator specifically for the input frequency. Absent.
[Brief description of the drawings]
FIG. 1 is a diagram showing a delay generator according to the present invention.
FIG. 2 is a time chart illustrating an operation example of the delay generator illustrated in FIG. 1;
FIG. 3 is a diagram showing another delay generator according to the present invention.
FIG. 4 is a time chart showing an operation example of the delay generator shown in FIG. 3;
FIG. 5 is a diagram showing another delay generator according to the present invention.
FIG. 6 is a time chart showing an operation example of the delay generator shown in FIG. 5;
FIG. 7 is a diagram showing a frequency synthesizer according to the present invention.
8 is an explanatory diagram of an operation of the frequency synthesizer shown in FIG.
FIG. 9 is a time chart illustrating an operation example of the frequency synthesizer illustrated in FIG. 7;
FIG. 10 is a diagram showing another frequency synthesizer according to the present invention.
11 is an explanatory diagram of an operation of the frequency synthesizer shown in FIG.
FIG. 12 is a time chart illustrating an operation example of the frequency synthesizer illustrated in FIG. 10;
FIG. 13 is a diagram showing a multiplier according to the present invention.
FIG. 14 is a time chart illustrating an operation example of the multiplier illustrated in FIG. 13;
FIG. 15 is a diagram showing a conventional delay generator.
16 is a time chart showing an operation example of the delay generator shown in FIG.
[Explanation of symbols]
18, 18a... First current source
18b ... current source
19, 19a ... second current source
22, 22a... First capacity
22b ... capacity
23, 23a... Second capacity
24, 24a, 24b ... comparator
26, 26a, 26b ... ramp wave generation circuit
27, 27a, 27b ... threshold voltage generation circuit
36 ... Current switch
37: threshold voltage input terminal
40, 40a ... accumulator
41, 41a ... delay generator body
42, 42a ... data conversion circuit
43, 43a ... control circuit
54-59 ... Capacity
66-75 ... Current switch
76-79… Comparator
84… OR gate
89, 89a, 89b ... data selector section

Claims (10)

A ramp generation circuit that generates a ramp voltage, a threshold voltage supply unit that supplies a threshold voltage, and a comparison between the ramp voltage and the threshold voltage, when the ramp voltage matches the threshold voltage. A delay circuit having a comparison circuit for generating an output pulse, wherein the ramp wave generation circuit generates the ramp wave voltage having a two-step slope,
The ramp generation circuit uses the ramp wave voltage having a slope corresponding to a first data input, and the threshold voltage supply means sets the slope of the threshold voltage to a slope corresponding to a second data input. At the same time, the first setting data is transmitted as the first data input, and the second setting data is transmitted as the second data input. A data selector unit for transmitting the second setting data as a data input and transmitting 0 as the second data input;
The ramp generation circuit includes a first current source for providing a current proportional to the first data input, and a first capacitor charged by the first current source and having one end coupled to a predetermined voltage. A second current source that generates a ramp wave voltage at the other end of the first capacitor and provides a current proportional to the second data input as the threshold voltage generator; and a second capacitor coupled to be charged and one end to a predetermined voltage by the second current source, characterized by using the one that generates the threshold voltage to the other end of said second capacitor Delay generator . 2. The delay generator according to claim 1, wherein a current switch is provided in parallel with the second current source. A ramp generation circuit that generates a ramp voltage, a threshold voltage supply unit that supplies a threshold voltage, and a comparison between the ramp voltage and the threshold voltage, when the ramp voltage matches the threshold voltage. A delay circuit having a comparison circuit for generating an output pulse, wherein the ramp wave generation circuit generates the ramp wave voltage having a two-step slope,
The ramp generation circuit uses the ramp wave voltage having a slope corresponding to a first data input, and the threshold voltage supply means sets the slope of the threshold voltage to a slope corresponding to a second data input. At the same time, the first setting data is sent as the first data input, and the value obtained by adding the additional data to the second setting data is sent as the second data input, A data selector unit for transmitting the second setting data as the first data input after a predetermined time has elapsed and transmitting 0 as the second data input;
The ramp generation circuit includes a first current source for providing a current proportional to the first data input, and a first capacitor charged by the first current source and having one end coupled to a predetermined voltage. A second current source that generates a ramp wave voltage at the other end of the first capacitor and provides a current proportional to the second data input as the threshold voltage generator; and a second capacitor coupled to be charged and one end to a predetermined voltage by the second current source, characterized by using the one that generates the threshold voltage to the other end of said second capacitor Delay generator . 4. The delay generator according to claim 1, wherein a circuit constant included in the ramp generation circuit and a circuit constant included in the threshold voltage generation circuit have the same value. A ramp generation circuit that generates a ramp voltage, a threshold voltage supply unit that supplies a threshold voltage, and a comparison between the ramp voltage and the threshold voltage, when the ramp voltage matches the threshold voltage. A delay circuit having a comparison circuit for generating an output pulse, wherein the ramp wave generation circuit generates the ramp wave voltage having a two-step slope,
The ramp wave generating circuit uses a ramp voltage gradient that corresponds to a data input, and the threshold voltage supply means supplies a constant threshold voltage. The data input is a first setting. A data selector for transmitting data and transmitting second setting data as the data input after a lapse of a predetermined time ;
The ramp generation circuit includes a current source that selectively provides a current proportional to the data input, and a capacitor that is charged by the current source and has one end coupled to a predetermined voltage. A delay generator using the above-mentioned ramp wave voltage generator . An accumulator for inputting a clock signal and setting data and accumulating the setting data in synchronization with the clock signal, and delaying a most significant bit of an output of the accumulator or an overflow signal of the accumulator by a predetermined time . A frequency synthesizer, comprising: the delay generator according to any one of claims 5 to 7. When the number of bits of the accumulator is n, the value of the output signal of the accumulator immediately before the output signal of the most significant bit rises is θ _p , the setting data is K, and the cycle of the clock signal is T, the delay occurs. 7. The frequency synthesizer according to claim 6, wherein the delay time of the most significant bit of the device is {(2 ^n-1-[ theta] _p ) / K} .T. When the number of bits of the accumulator is n, the output signal of the accumulator is θ, the setting data is K, and the cycle of the clock signal is T, the delay time of the overflow signal of the delay generator is {(2 ⁿ − The frequency synthesizer according to claim 6, wherein θ) / K} · T. A plurality of delay generators according to any one of claims 1 to 5, wherein a multiplied signal is input and a plurality of types of delay times are generated, and said plurality of delay generators are input with said multiplied signal and each of said plurality of delay generators A frequency multiplier, comprising: a distribution circuit for transmitting a timing of delay generation; and a logical sum unit for calculating a logical sum of outputs of the plurality of delay generators. As the plurality of delay generators, when the cycle of the multiplied signal is T, an arbitrary time is d, an integer of 2 or more is N, and an integer of 1 or more is M, N kinds of specific delay times d + ( 10. The multiplier according to claim 9, wherein a multiplier for generating (k.M / N) T (k is any integer from 0 to N-1) is used.

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