RU2771741C1 - Method and device for recording and storing voltage - Google Patents

Abstract

FIELD: automatics.

SUBSTANCE: invention relates to automatics and analog computing. The analog voltage recording and storage device contains two sawtooth voltage generators (SVG), a boundary voltage adder (BVA), an SV adder (SVA), an SV offset unit (SVOU), the first output of the voltage recording and storage device is connected to the first input of the first SVG and to the first input of the BVA, the second output of the voltage recording and storage device is connected to the second input of the SVG, the third the output of the voltage recording and storage device is connected to the second input of the first SVG, the fourth output of the voltage recording and storage device is connected to the third input of the first SVG, the output of the BVA is connected to the fourth input of the first SVG, to the first input of the second SVG and to the first input of the SVOU, the first output of the first SVG is connected to the first input of the SVA, the second output of the first SVG is connected to the second input of the second SVG, the third output of the first SVG is connected to the second input of the SVA and the second input of the SVOU, the first output of the second SVG is connected to the third input of the SVA, the second output of the second SVG is connected to the fourth input of the SVA and the third input of the BSPS, the first output of the SVA is connected to the fourth input of the SVOU, the second output of the SVA is connected to the output of the SVOU and to the output of the voltage recording and storage device.

EFFECT: ensuring the possibility of long-term storage in the volatile memory of the constant voltage of a given value, reducing the recording time in the analog memory of a given voltage level.

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Description

The invention relates to instrumentation and can be used in devices for processing or converting analog information.

Attempts to maintain voltage and current values for a long time are associated with the presence of elements that have a certain inertia of these parameters in time. These elements include inductances, which have the inertia of the current values, and capacitors, with the inertia in the voltage of the accumulated charge. Due to energy leaks, both of these elements will gradually reduce the accumulated energy potential. Therefore, attempts to build analog RAM based on existing long-term storage elements have significant limitations. Methods for compensating for energy losses lead to a significant complication of circuit solutions, hardware costs and a decrease in reliability.

The task arises of creating a circuit variant of recording and storing analog voltage values in time, refusing to store voltage on energy storage devices and analog-to-digital conversions, which lead to an increase in equipment complexity, reduce the accuracy and speed of memory elements.

Known electrically controlled resistive elements of analog memory [SU1840837A1 Yushina L.D. (RU), Terekhov V.I. (RU) "Electrically controlled resistive element with analog memory"; Khrapovitskaya Yu. V., Maslova N. E., Zanaveskin M. L. “Perspective structures with a memory effect created on the basis of inorganic materials” // Science and Education (MGTU named after N. E. Bauman) (electronic journal). - 2013. - No. 12. - P. 1. DOI: 10.7463/1213.0669629.], which allow you to create circuits for recording and long-term storage of the input voltage value due to reversible chemical reactions that change the resistance of the element. The disadvantage of memory devices based on such elements, in comparison with the technical solution stated below, is the low speed of recording information, which prevents their use as elements of random access memory.

An analog storage device [RU 2018980 C1] is known, in which the claimed increase in accuracy, stability and speed of the device is achieved by supplying an additive error with the opposite sign to the output voltage circuit in order to fully compensate it. The device contains the first and second analog switches, access-and-hold devices, storage capacitors, a control unit, analog switches, and a buffer amplifier. The disadvantage of the device is the use of capacitors as a memory element, which are discharged over time and therefore cannot be used as a reliable source of long-term data storage, and the digital compensation method complicates the device.

Known device and method for simplified recording and playback of an analog signal [RU 2204176 C2]. The device options include an interface for interpreting external commands, controls, means for converting analog signals to digital form and digital information to analog form, memory, a multiplexer, an audio filter, and a demultiplexer. The memory is divided into a plurality of sectors and commands are given to read data bytes, wherein if the bytes contain zeros, the current memory sector is identified as empty, and if the bytes are non-zero, the current memory sector is identified as a message sector. This device and method relate to hybrid digital-analog devices. The disadvantage is the need for signal conversions, which leads to additional write and read delays and a significant complication of the circuit.

The closest in terms of the method and device for generating the level of the stored voltage is an analog storage device [RU 2178207 C1], which is selected as a prototype. The prototype contains two operational amplifiers, two capacitors, a resistor, three switches, a constant voltage source, a pulse shaper, two logic inverters, two 2I logic gates. The prototype records the values of the input analog signal by matching the input voltage with the voltage of the sawtooth signal generated in the device. The input voltage is rewritten periodically at fixed time intervals and stored on two capacitors connected to the operational amplifiers. The disadvantage of the prototype with respect to the claimed technical solution is the need to periodically rewrite the values of the input voltage, tk. the use of capacitors as a memory element does not allow for a long time to keep its fixed values.

The technical result of the claimed invention consists in providing the possibility of long-term storage of a given voltage value in a volatile memory, reducing the time for recording a given voltage level in an analog memory compared to known methods based on analog-to-digital conversions and capacitive charge accumulation, simplifying the device through the use of event control operating modes without the use of digital circuits. The patent-pending approach is based on converting a voltage value into a time interval.

и периодом Т, напряжение ПС U₁(t) изменяют по закону, представленному выражением:The goal in the method of recording and storing voltage V lying within the values from E ₀ to E (E ₀ < E) is achieved by generating two linearly varying periodic sawtooth signals (PS) U ₁ (t ) and U ₂ (t) with amplitude

and period T, the voltage of the PS U ₁ (t) is changed according to the law represented by the expression:

(1) ,

(one) ,

U ₁ (t) - the first linearly changing periodic sawtooth signal;

t is the current time;

E ₀ - constant value of the lower value of the recorded voltage;

E is the constant value of the upper value of the recorded voltage;

n is the number of the period of a linearly varying periodic sawtooth signal, n ≥0;

T is the duration of the period;

T ⁺ - left border of intervals [nT, (n+1)T];

T ^- - right border of intervals [nT,(n+1)T];

the voltage of the PS U ₂ (t) is changed according to the law represented by the expression:

(2),

(2)

– задержка ПС U₂(t) по времени относительно ПС U₁(t), where

– delay of PS U ₂ (t) in time relative to PS U ₁ (t),

U ₂ (t) - the second linearly changing periodic sawtooth signal; to form the voltage values V(t) PS U ₁ (t) and U ₂ (t) are added according to the law represented by the expression:

(3),

(3)

to change the value of the voltage V(t) in the range from E ₀ to E, change the time delay τ of the voltage of the PS U ₂ (t) relative to the voltage of the PS U ₁ (t) from 0 to T, to store the voltage V ₀ in the range E ₀ ≤ V ₀ ≤ E, the voltage of the PS U ₁ (t) is compared with the voltage V ₀ when at time t ₀ , nT≤ t ₀ ≤(n+1)T, the voltage U ₁ (t ₀ ) reaches the value U ₁ (t ₀ )=V ₀ the voltage of the PS generator U ₂ (t) is reset to the value 0, the voltage generator of the PS U ₂ (t) is restarted with a delay τ=t ₀ -nT, they begin to generate a linearly decreasing periodic voltage of the PS U ₂ ( t) with a delay τ, at which the voltage of the PS U ₂ (τ + nT) = 0, immediately after the restart of the voltage generator of the PS U ₂ (t), the supply of the recorded voltage V ₀ is stopped and the output voltage V(t) = V ₀ is formed according to expressions (1, 2, 3).

Figure 1 shows a block diagram of the device.

The goal in the device for recording and storing voltage (UZKhN) (Fig. 1) is achieved by the fact that for the formation of each PS, two sawtooth signal generators (SGS) are used - the first GPS (1) and the second GPS (2), the boundary voltage adder (SGN ) (3), the sawtooth signal adder (SPS) (4), the PS bias unit (ACAS) (5), the first output (6) of the UZKhN is connected to the first input (7) of the first GPS (1) and to the first input (8) SGN (3), the second output (9) of the UZKhN is connected to the second input (10) of the SGN (3), the third output (11) of the UZKhN is connected to the second input (12) of the first GPS (1), the fourth output (13) of the UZKhN is connected to by the third input (14) of the first GPS (1), the output (15) of the SGN (3) is connected to the fourth input (16) of the first GPS (1), to the first input (17) of the second GPS (2) and to the first input (18) ACAS (5), the first output (19) of the first GPS (1) is connected to the first input (20) of the PCS (4), the second output (21) of the first GPS (1) is connected to the second input (22) of the second GPS (2), the third output (23) of the first GPS (1) is connected to the second input (24) of the SPS (4) and with the second input (25) of the ACAS (5), the first output (26) of the second GPS (2) is connected to the third input (27) of the PCS (4), the second output (28) of the second GPS (2) is connected to the fourth input (29) SPS (4) and with the third input (30) ACAS (5), the first output (31) SPS (4) is connected to the fourth input (32) ACAS (5), the second output (33) SPS (4) is connected to the output ( 34) ACAS (5) and with UZKhN output (35).

In FIG. 2 shows voltage diagrams explaining the method and operation of the device in the voltage storage mode V(t).

Figure 3 shows voltage diagrams that explain the method and operation of the device in the recording mode of the stored voltage V(t).

Consider the procedure for generating the output voltage using the patented method. Let the delay τ=0. Then according to expressions (1-3)

(4)

(4)

From (4) it follows that with a delay τ=0 V(t)≡ E ₀ .

Let the delay τ>0. Then according to expressions (1-3)

(5)

(5)

From (5) it follows that with a delay τ=Const≠0

, (6)

, (6)

The voltage V(t) is a constant value, which is determined by the delay τ=Const≠0. Thus, it has been proven that the application of the proposed method leads to the storage of the recorded voltage throughout the entire time of operation of the generators.

Plots explaining the patented method in the mode of writing voltage values to memory are shown in Fig.3.

Initially, a zero voltage level and a delay τ=0 were applied to the input (11) of the UCP. Let from the moment of time t ₁ to the input (11) UZKhN begins to apply the voltage level U _in =V ₁ >0, and to the fourth input (13) UZKhN recording signal U _cp . This event causes the write mode to start executing.

At time t ₂ , when the values of the voltages V ₁ and U ₁ (t ₂ ) coincide, the voltage of the second GPS (2) is reset to zero (U ₂ (t ₂ )=0) and it starts to generate a linearly decreasing voltage with a delay τ _{1 =} t2. The recording mode is turned off and the voltage storage mode V ₁ is switched to. The output voltage V(t) takes on the value V ₁ . This voltage is stored at the output (35) of the UZKhN until a signal for recording a new voltage value arrives.

At the time t ₃ begins supplying the recorded voltage V ₂ <0 , and the fourth input (13) UZKhN receives a recording signal U _cp . The device goes back into recording mode. At time t ₅ when the voltage values V ₂ =U ₁ (t ₅ ) coincide, the voltage generator U ₂ (t ₅ )=0 is reset and it starts generating a new linearly decreasing voltage with a delay τ ₂ = t ₅ -t ₄ . In this case, the recording mode is turned off, and the UZKhN switches to the voltage storage mode V(t)= V ₂ .

As follows from the description of the recording mode, the maximum recording time does not exceed the period T linearly varying voltages U ₁ (t) and U ₂ (t).

Let's consider the work of the UPC (Fig. 1), which implements the method presented above. In UZKhN, an event-based method for controlling the operation modes of blocks based on continuum processors [RU 2739723 C1] is used.

In the voltage storage mode, both HPS (1) and (2) generate sawtooth linearly varying voltages with a period of T and with an amplitude of E-E₀, the value of which is set by the SGN adder (3). At the output (19) of the first HPS (1), a linearly increasing sawtooth voltage U_one(t) starting from level E₀. Upon reaching the level E (at the end of the period), the voltage is reset to the initial E₀ and a new generation cycle begins (Fig. 2). In this case, the logical level of completion of the process of generating a linearly increasing signal is fed to the event output (23). At the output (26) of the second HPS (2), a linearly decreasing voltage U₂(t) starting from level 0 and shifted relative to the voltage U_one(t) to τ. Upon reaching the level (-E + E₀), the voltage is reset to the initial value and a new generation cycle begins (Fig. 2). In this case, the event output (28) is supplied with a logical level of completion of the process of generating a linearly decreasing signal U₂(t).

The outputs (33) and (34) of the SPS (4) and ACAS (5) are combined, because the output signals of these blocks are incompatible. When ACAS (4) is connected, the signal from ACAS (5) is disconnected from the output (35) of the UPC and vice versa, when ACAS (5) is connected, the signal from the ACAS (4) is disconnected from the output (35) of the UPC. The switching control of the SPS (4) and ACAS (5) is carried out by event signals coming from the outputs (23) and (28) of the first GPS (1) and the second GPS (2). As a result, a combination of two incompatible signals is formed at the output:

(7)

(7)

in the first case and

(8)

(eight)

in the second case.

The logic level supplied from the output (23) with a value of one disconnects the output (33) of the SPS (4) from the output (35) of the UPC and connects the output (34) of ACAS (5) to the output (35) of the UPC. The logic level supplied from the output (28) with a value of one disables the output (34) of the ACAS (5) and connects the output (33) of the SPS (4) to the output (35) of the UPC. The stable state of the output keys of the SPS (4) and ACAS (5) is maintained until a signal appears at the outputs (23) and (28). With the simultaneous appearance of one at the event outputs (23) and (28), SPS (4) will always be connected to the output of the UZKhN and the signals are added according to formula (7).

(Фиг. 3). Далее УЗХН работает в режиме хранения значения напряжения. To transfer the UZKhN to the recording mode, a writeable analog voltage is applied to its third input (11), and a logical level one is applied to its fourth input (13). At the same time, in the first HPS (1), the levels of the linearly increasing voltage are compared with the recorded voltage level V. If the values match at the second (event) output (21), a logical recording level is formed, which is fed to the second (event) input (22) of the second HPS (2). The signal comparison mode in the first GPS (1) ends. When a logic level one is applied to the input (22) in the GPS (2), the voltage is reset to the initial value and a new cycle of generation of a linearly decreasing voltage begins

(Fig. 3). Further UZKhN works in the voltage value storage mode.

The accuracy and duration of voltage storage in the memory device is related to the characteristics of the PS generators. It is determined by the linearity of the generated voltages, a decrease in the sawtooth voltage reset delay when the amplitude values are reached, and the stability of the generators.

The above information allows us to conclude that the proposed device and method provide the claimed advantages in comparison with the prototype.

The analysis of the prior art carried out by the applicant made it possible to establish that there are no analogues characterized by sets of essential features identical to all the features of the claimed method and device, which indicates that the claimed invention complies with the patentability condition "novelty".

The proposed method and device are industrially applicable to existing technical means and meet the criterion of "inventive step", since they do not explicitly follow from the prior art.

Thus, the proposed technical solutions meet the established conditions for the patentability of the invention.

Claims (8)

1. A method for recording and storing voltage, in which, to obtain a given value of constant voltage, two linearly varying periodic sawtooth signals (PS) U ₁ ( t ) and U ₂ ( t ) are generated with amplitude

and period T , the voltage of the PS U ₁ ( t ) is changed according to the law represented by the expression

voltage PS U ₂ ( t ) change according to the law represented by the expression

where n is a natural series of numbers, n ≥0, T ⁺ is the left boundary of the intervals [ nT , ( n +1) T ], T ^- is the right boundary of the intervals [ nT ,( n +1) T ],

- the delay of the PS U ₂ ( t ) in time relative to the PS U ₁ ( t ), to form the output specified DC voltage V , the voltages of the PS U ₁ ( t ) and U ₂ ( t ) are added according to the law represented by the expression

to change the value of the output voltage V ( t ) in the range from E ₀ to E , change the delay

voltage PS U ₂ ( t ) relative to the voltage PS U ₁ ( t ) from 0 to T , to store the voltage V ₀ in the range E ₀ ≤ V ₀ ≤ E, the voltage PS U ₁ ( t ) is compared with the voltage V ₀ , when at time t ₀ , nT ≤ t ₀ ≤( n +1) T , the voltage of the substation U ₁ ( t ₀ ) reaches the value U ₁ ( t ₀ )= V ₀ the voltage of the generator of the substation U ₂ ( t ) is reset to values 0 , voltage generator PS U ₂ ( t ) start again with a shift

\ u003d t ₀ - nT , they begin to generate a linearly decreasing periodic voltage of the substation U ₂ ( t ) with a shift

, at which the voltage U ₂ (

+ nT )=0, immediately after restarting the voltage generator of the PS U ₂ ( t ), the supply of voltage V ₀ is stopped and the output voltage V ( t )= V ₀ is formed according to expressions (1, 2, 3). 2. An analog voltage recording and storage device (UZKhN), which uses two PS (GPS) generators, a boundary voltage adder (SGN), a PS adder (SPS), a PS bias unit (ACAS), the first output of the UZKhN is connected to the first input of the first GPS and with the first input of the SGN, the second output of the UZKhN is connected to the second input of the SGN, the third output of the UZKhN is connected to the second input of the first GPS, the fourth output of the UZKhN is connected to the third input of the first GPS, the output of the SGN is connected to the fourth input of the first GPS, to the first input of the second GPS and with the first ACAS input, the first output of the first GPS is connected to the first input of the GPS, the second output of the first GPS is connected to the second input of the second GPS, the third output of the first GPS is connected to the second input of the ACAS and to the second ACAS input, the first output of the second GPS is connected to the third input SPS, the second output of the second GPS is connected to the fourth input of the SPS and to the third input of ACAS, the first output of the SPS is connected to the fourth input of ACAS, the second output of the SPS is connected to the output of ACAS and to the output of the UPC.

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