JP2757714B2 - Frame pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame pulse generating circuit, and more particularly to a frame pulse generating circuit for generating a frame pulse signal indicating a head position of a frame.

[0002]

2. Description of the Related Art Conventionally, a frame pulse generation circuit of this type has a frame pulse generation counter for generating an output frame pulse signal only with an internal clock signal which is an output signal of an internal clock generation source, an external input clock signal and an external input signal. There were two counters, a frame pulse generation counter for generating a counter load pulse signal from a frame pulse signal and regenerating an output frame pulse signal.

[0003]

In the conventional frame pulse generation circuit, two counters, a frame pulse generation counter for an internal clock signal and a frame pulse generation counter for an external input clock signal and an external input frame pulse signal, are used. Therefore, there is a problem that the circuit scale becomes large.

An object of the present invention is to provide a frame pulse generation counter for generating an output frame pulse signal from an internal clock signal and a new output frame pulse signal from an external input clock signal and an external input frame pulse signal. It is another object of the present invention to provide a frame pulse generation circuit that can reduce the circuit scale by also using the frame pulse generation counter to be reset.

[0005]

A frame pulse generating circuit according to the present invention includes a selecting circuit for selecting one of an external input clock signal and an internal clock signal, and a counter initial value which can be set from the outside. A frame pulse generation counter that counts up a clock signal selected by a circuit, outputs a counter load pulse signal at the time of full counting, loads a first counter initial value, and generates an output frame pulse signal; A load pulse generating circuit for inputting an external input frame pulse signal when a signal is selected to generate a counter load pulse signal for the frame pulse generating counter, and a counter pulse signal output from the load pulse generating circuit The frame pulse generation counter And a counter initial setting unit for generating a counter initial value operation signal for operating the counter initial value to a second counter initial value greater than the first counter initial value.

[0006]

In the frame pulse generation circuit according to the present invention, the selection circuit selects one of the external input clock signal and the internal clock signal, and the frame pulse generation counter can externally set a counter initial value. The selected clock signal is counted up, a counter load pulse signal is output at the time of full counting, a first counter initial value is loaded, and an output frame pulse signal is generated,
The load pulse generation circuit inputs an external input frame pulse signal when the external input clock signal is selected by the selection circuit to generate a counter load pulse signal for the frame pulse generation counter, and the counter initial setting unit outputs the load pulse generation signal from the load pulse generation circuit. A counter initial value operation signal for operating the frame initial value of the frame pulse generation counter to a second counter initial value larger than the first counter initial value is generated in accordance with the output counter load pulse signal.

[0007]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of a frame pulse generating circuit according to one embodiment of the present invention. The frame pulse generation circuit according to the present embodiment includes an internal clock generation source 1, a selection circuit 2, a load pulse generation circuit 3, a frame pulse generation counter 4, and a counter initial setting unit 5.
And inverters 6 and 7.

An internal clock generation source 1 outputs an internal clock signal S 1 and applies it to one input terminal of a selection circuit 2.

The selection circuit 2 receives the external input clock signal S2 at the other input terminal and selects either the internal clock signal S1 or the external input clock signal S2 based on the selection signal S17 input to the control terminal. Output to the frame pulse generation counter 4.

The load pulse generation circuit 3 inputs the external input frame pulse signal S3 when the selection signal S17 for selecting the external input clock signal S2 is input to the control terminal, and inverts the external input clock signal S2 by the inverter 6. A counter load pulse signal S4 delayed by one clock from the rise of the external input frame pulse signal S3 is output in synchronization with the signal. When the selection signal S17 for selecting the internal clock signal S1 is input to the control terminal,
The load pulse generation circuit 3 does not operate.

The frame pulse generation counter 4 is a 32-bit counter and has a counter load pulse signal S4.
Or, based on the input of S16, the counter initial value signal S5
By inputting .about.S9, the counter initial value can be set.

When the counter load pulse signal S4 is input, the counter initial setting unit 5 receives the external input clock signal S4.
2 in synchronization with the counter initial value signals S5 to S9.
(Specifically, the lower-order second bit) is output. The counter initial value operation signal S6 changes the values of the counter initial value signals S5 to S6 from the first counter initial value 8 (01000) (the number in parentheses indicates a binary number; the same applies hereinafter) to the second counter initial value 10 ( 0
Change to 1010).

FIG. 2 is a signal waveform diagram showing an example of the operation of the frame pulse generation circuit of the present embodiment. In FIG. 2, it is assumed that the external input frame pulse signal S3 has been input by a preceding circuit (not shown) with a delay of a half clock from a correct phase.

Next, the operation of the frame pulse generating circuit of this embodiment having the above-described configuration will be described.

(1) First, a case where the internal clock signal S1 is selected by the selection circuit 2 by the selection signal S17 will be described.

The internal clock signal S is selected by the selection signal S17.
When 1 is selected, the selection circuit 2 outputs the internal clock signal S1 to the frame pulse generation counter 4.

The frame pulse generation counter 4 receives the internal clock signal S1 and counts up. When the internal clock signal S1 reaches a full count of 31 (11111), it outputs the counter load pulse signal S16 to the frame pulse generation counter 4 itself.

As a result, the frame pulse generation counter 4 receives the counter initial value signals S5 to S9 and is initialized to the first counter initial value 8 (01000), and the most significant counter output signals S10 to S14. An inverted signal of the bit signal S14 by the inverter 7 is output as an output frame pulse signal S15.

Thereafter, the frame pulse generation counter 4
Counts up the internal clock signal S1 again from the first counter initial value 8 (01000), and outputs the output frame pulse signal S rising every 24 bits from 8 to 31.
15 is repeated.

(2) Next, the case where the external input clock signal S2 is selected by the selection circuit 2 by the selection signal S17 will be described (see FIG. 2).

When the external input clock signal S2 is selected by the selection signal S17, the selection circuit 2 outputs the external input clock signal S2 to the frame pulse generation counter 4.

Since the selection signal S17 for selecting the external input clock signal S2 is input to the control terminal, the load pulse generation circuit 3 synchronizes the external input clock signal S2 with the inverted signal of the inverter 6 and outputs the external input frame pulse. A counter load pulse signal S4 delayed by one clock from the rise of the signal S3 is generated and output to the frame pulse generation counter 4 and the counter initial setting unit 5.

The counter initial setting unit 5 outputs a counter load pulse signal S4 output from the load pulse generation circuit 3.
And outputs a counter initial value operation signal S6 for changing the counter initial value of the frame pulse generation counter 4 to the second counter initial value 10 (01010) in synchronization with the external input clock signal S2.

The frame pulse generation counter 4 inputs counter initial value signals S5 to S9 based on the counter load pulse signal S4 output from the load pulse generation circuit 3, and initializes the second counter initial value 10 (01010). Is set. As a result, the value of the frame pulse generation counter 4 becomes 10 (01010) at the second clock after the rising of the external input frame pulse signal S3 at which the value of the frame pulse generation counter 4 should be 8 (01000),
The external input frame pulse signal S3 and the value of the frame pulse generation counter 4 (that is, the output frame pulse signal S
15). If the value of the frame pulse generation counter 4 is 16 (10000) or more immediately before this, since the most significant bit signal S14 of the counter output signals S10 to S14 is inverted, an incorrect output frame pulse is output. Although there is a possibility that the signal S15 is output, it is only for the first time and is canceled immediately thereafter.

The frame pulse generation counter 4 counts up the external input clock signal S2 from the second counter initial value 10 (01010), which is a full count of 3
At 1 (11111), the counter load pulse signal S16 is output to the frame pulse generation counter 4 itself.

As a result, the frame pulse generation counter 4 receives the counter initial value signals S5 to S9 and is initialized to the first counter initial value 8 (01000), and the highest order of the counter output signals S10 to S14. An inverted signal of the bit signal S14 by the inverter 7 is output as an output frame pulse signal S15. This is the first synchronized output frame pulse signal S15 having the correct phase.
Becomes

After the output of the output frame pulse signal S15, the external input frame pulse signal S3 which rises a half clock later is input.
Generates a counter load pulse signal S4 delayed by one clock from the rise of the external input frame pulse signal S3 in synchronization with the inverted signal of the external input clock signal S2 by the inverter 6, and generates the frame pulse generation counter 4 and the counter initial setting. Output to section 5.

The counter initial setting unit 5 outputs a counter load pulse signal S4 output from the load pulse generation circuit 3.
And outputs a counter initial value operation signal S6 for changing the counter initial value of the frame pulse generation counter 4 to the second counter initial value 10 (01010) in synchronization with the external input clock signal S2.

The frame pulse generation counter 4 inputs the counter initial value signals S5 to S9 based on the counter load pulse signal S4 output from the load pulse generation circuit 3, and initializes the second counter initial value 10 (01010). Is set.

Thereafter, the frame pulse generation counter 4
Counts up the external input clock signal S2 again from the second counter initial value 10 (01010),
The operation of outputting the output frame pulse signal S15 rising every 24 bits of 1 is repeated.

In this way, the externally input frame pulse signal S3 input with a half clock delay can be re-generated as a synchronized output frame pulse signal S15 having a correct phase and output.

[0033]

As described above, according to the present invention, a frame pulse generation counter for generating an output frame pulse signal from an internal clock signal and a new output frame pulse signal from an external input clock signal and an external input frame pulse signal are generated. Set the frame pulse generation counter to
By using a single counter, the circuit size can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a frame pulse generation circuit according to one embodiment of the present invention.

FIG. 2 is a signal waveform diagram illustrating an operation of the frame pulse generation circuit according to the embodiment.

[Explanation of symbols]

 Reference Signs List 1 internal clock generation source 2 selection circuit 3 load pulse generation circuit 4 frame pulse generation counter 5 counter initial setting unit S1 internal clock signal S2 external input clock signal S3 external input frame pulse signal S4 counter load pulse signal S5 counter initial value signal S6 counter Initial value operation signal S7 to S9 Counter initial value signal S10 to S14 Counter output signal S15 Output frame pulse signal S16 Counter load pulse signal S17 Selection signal

Claims (1)

(57) [Claims] 1. A selection circuit for selecting one of an external input clock signal and an internal clock signal, and a counter initial value which can be set from the outside, and the clock signal selected by the selection circuit is counted up to perform full counting. Output the counter load pulse signal and
A frame pulse generation counter that loads an initial value of the counter and generates an output frame pulse signal; and a counter for the frame pulse generation counter that inputs an external input frame pulse signal when an external input clock signal is selected by the selection circuit. A load pulse generating circuit for generating a load pulse signal; and a second counter having a counter initial value of the frame pulse generating counter larger than the first counter initial value in response to the counter load pulse signal output from the load pulse generating circuit. A frame pulse generating circuit comprising: a counter initial setting unit that generates a counter initial value operation signal that operates to a counter initial value.