JP3382329B2 - Odd counter circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an odd number counter circuit for generating a clock signal by counting down an odd number while balancing the clock duty of the clock signal.

[0002]

2. Description of the Related Art FIG. 2 shows a clock duty 5 of a conventional example.
It is an example of a counter circuit that generates a clock signal that is 1/3 countdown of 0%. This operation will be described with reference to the operation timing chart of FIG. A clock signal having a clock duty of 50% is input to the input terminal 1. D
Type flip-flops DFF3, 4 and AND gate AND
1, 2 and 1 constitute a 1/3 countdown circuit which operates at the rising edge of the input clock signal a. D-type flip-flops DFF5, 6 and AND gate AND3
4 and 4 constitute a 1/3 countdown circuit which operates at the falling edge of the input clock signal a. AND1 ~
A reset signal (reset at L level) is input to the reset signal input terminal 4 from the reset signal input terminal 3. The Q outputs of DFF1 and DFF3 are input to the OR gate OR1 and this output becomes the output terminal 2. The waveforms of the Q outputs of the DFFs 3 to 6 when the reset signal is released (L → H level) between times t0 to t1 are as shown in d to g of FIG. These output signals are 1/3 countdown clock signals, but the clock duty is not 50%. Therefore, for example, DF
If the Q output of F3 and DFF5 is ORed, the duty 50
% Clock signal is output to the output terminal 2.

In this prior art example, the normal 1/3 countdown clock signal may not be output to the output terminal 2 because the two 1/3 counter circuits cannot be synchronized without the reset signal.

[0004]

However, the conventional example shown in FIG. 2 has the following problems.

1) Especially when the circuit is composed of an ECL circuit, four large-scale DFF circuits and five AND and OR gates are required, and the overall circuit scale is too large. The larger the countdown value, the more problematic.

2) A reset signal for synchronizing the two counter circuits is required, and its release timing is limited to the half cycle period of the input clock, so that it is not suitable for a high-speed clock operation circuit.

Therefore, an object of the present invention is to provide an odd number counter circuit which solves the above problems.

[0008]

In order to achieve the above-mentioned object, the invention of claim 1 uses an odd number (N
1) An odd counter circuit for outputting a countdown output clock signal, wherein a minimum integer N2 larger than N1 / 2 and cascade connection of the flip-flops
The input clock signals input to the N2 flip-flops are selectively selected according to a control signal corresponding to the state of the final stage flip-flop when N2 operation edges of the input clock signals are input to the two flip-flops. And an selecting means for selecting either the output or the inverted output of the final stage flip-flop and supplying it as the control signal to the inverting means. According to a second aspect of the present invention, in the first aspect, means for generating a gate signal at the edge of the input clock signal input first, and control of the supply of the input clock signal to the inverting means by the gate signal. And a means for doing so. Furthermore, the invention of claim 3 is an odd number counter circuit which outputs an output clock signal which is an odd number (N1) countdown from an input clock signal, wherein a minimum integer N2 larger than N1 / 2 is connected in cascade. , Input clock signals to be input to the N2 flip-flops according to a control signal corresponding to the state of the final stage flip-flop when N2 operation edges of the input clock signal are input to the N2 flip-flops. An inverting means for selectively inverting, a means for generating a gate signal at an edge of an input clock signal input first, and a means for controlling the supply of the input clock signal to the inverting means by the gate signal. It is characterized by that.

[0009]

<First Reference Example> FIG. 1 shows a 1/3 counter circuit according to the first reference example. This will be described using the operation timing chart of FIG. The positive phase signal of the input clock signal (a in FIG. 3) to the input terminal 1 and the negative phase signal via the inverter NOT1 are input to the switch S1, and the selected output is input to the clock inputs of the D-type flip-flops DFF1 and DFF2. Connected.
The Q output of DFF1 is connected to the D input of DFF2, and DF
The Q output of F2 controls the D input of DFF1 and the switch S1. If the Q output of DFF1 (b in FIG. 3) and the Q output of DFF2 (c in FIG. 3) are both at the L level immediately before time t1, the N (inverted) Q output of DFF2 becomes H.
This is the level, and the selection output of the switch S1 outputs the positive phase clock signal. At time t1, the Q output of DFF1 is H
The Q output of DFF2 changes to the H level at time t3. In addition, at this time, since the switch S1 selects the reverse phase clock signal, the clock phase of the clock signals of the DFFs 1 and 2 changes as shown in FIG. 3h. Therefore, a thin pulse is generated at the time of change, but only a negative edge of H → L is generated, and since this change is performed after the Q output of the DFF 2 is determined, there is no problem in operation. At time t4, DFF1 changes to L level again, and subsequently at time t6, DFF2 changes to L level. Time t6
, The switch S1 again selects the positive phase clock signal,
The phase of the clock signal changes (Fig. 3h). Similarly, at times t7 and t9, DFF1. Each Q output of DFF2 changes to H level, and at time t9, the output clock phase of the switch S1 is inverted. Since the state at the time t7 is equal to the state at the time t1, the 1/3 countdown clock signal with a duty of 50% is output to the output terminals 2 and 2'by repeating the operation described above. Further, no matter what the initial state of the Q output of DFF1 and DFF2 is, the desired clock signal is output to the output terminals 2 and 2 ', so that the circuit does not need the reset operation.

<Second Reference Example> FIG. 4 is a fifth reference example of 1/5 of a duty of 50%.
The counter circuit which generates the countdown clock signal differs from that of FIG. 1 only in that a D-type flip-flop DFF7 is added. This operation timing chart is shown in FIG. 5b to 5d are the Q output signals of the DFFs 1, 2 and 7, and FIG. 5e is the clock signal of the output of the switch S1. DFF1, 2, and 7 have the same duty 5
A 0% 1/5 countdown clock signal is output. A desired odd number counter circuit can be realized by adding 1 / 7.1 / 9, ... DFF circuits one by one.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 6 shows an example of a counter circuit capable of controlling the phase of an output clock signal which is 1/3 counted down with a duty of 50% in half cycle units of the input clock signal to which the present invention is applied. This operation will be described using the operation time chart of FIG. The difference in configuration from FIG. 1 will be described first. The input clock signal is input to the D-type flip-flop DFF8 via the inverter NOT3 and is input to the AND gate A together with the input clock signal via the switch S2.
The output clock signal input to ND5 is input to the counter circuit having the same configuration as that of FIG. Further, the control signal of the clock signal inversion control switch S1 is set to the Q and NQ of the DFF2.
A switch S3 for either output is provided.
Further, the Q outputs of DFF1 and DFF2 are input to the switch S4, and the output becomes the output terminal 2. Output phase data is D1
There are 3 bits of ~ D3, and the phase data D3 is the switch S2.
, The phase data D1 is for the switch S3, and the phase data D2, D3 are for the exclusive OR gate EXOR1.
And the outputs control the switches S4, respectively. Furthermore, the DFFs 1, 2, 8 are reset by the reset signal (a in FIG. 7) to the phase reset signal terminal 4.

AND when the phase data D3 is at L level
5 outputs are the same as the input clock signal b to the input terminal 1, and when the phase data D1 is L level, the 1/3 countdown clock signals shown by c and e in FIG. Is output. If at this time the phase data D
When 1 is at H level, the first operation clock edge becomes a falling edge, so that clock signals as shown in FIGS. 7d and 7f are output to the Q outputs of DFF1 and DFF2, respectively. On the other hand, when the phase data D3 is at the H level, the Q output of the DFF8 (see FIG.
Since the edge of the clock signal at times t1 and t2 is masked by i), the clock signal of the Q output of DFF2 at the L and H levels of the phase data D1 is shown in FIG.
It becomes like g and h. Therefore, as shown in FIG. 7, a 1/3 countdown clock signal with a duty of 50% in which the clock phase is shifted by a half cycle of the input clock cycle corresponding to the binary value of the phase data D1 to D3 is output to the output terminal. .

[0014]

As described above, according to the present invention, the number of odd-numbered counter circuits that generate odd-numbered countdown clock signals with a duty of 50% can be greatly reduced (about half) as compared with the scale of the conventional example. This is a great advantage particularly when the ECL circuit is used.

[Brief description of drawings]

FIG. 1 is a block diagram of a first reference example for explaining the present invention.

FIG. 2 is a conventional odd-numbered counter circuit diagram.

FIG. 3 is an operation time chart of FIGS. 1 and 2.

FIG. 4 is a block diagram of a second reference example.

FIG. 5 is an operation time chart of FIG.

FIG. 6 is a block diagram of an embodiment of the present invention.

FIG. 7 is an operation time chart of FIG.

[Explanation of symbols]

1 Clock input terminal 2, 2'clock output terminal DFF1, DFF2 D-type flip-flop

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-48432 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 23/66

Claims (3)

(57) [Claims] 1. An odd counter circuit for outputting an output clock signal that is an odd number (N1) countdown from an input clock signal, the minimum integer N2 greater than N1 / 2 being cascaded, and said N2 Of the input clock signals are selectively inverted in response to a control signal corresponding to the state of the final stage flip-flop when N2 operation edges of the input clock signals are input to the flip-flops. An odd counter circuit, comprising: an inverting means for performing the above operation, and a selecting means for selecting either the output or the inverted output of the final stage flip-flop and supplying the selected control signal to the inverting means. 2. The method according to claim 1, further comprising means for generating a gate signal at an edge of an input clock signal input first, and means for controlling the supply of the input clock signal to the inverting means by the gate signal. An odd number counter circuit that is further equipped. 3. An odd number counter circuit for outputting an output clock signal that is an odd number (N1) countdown from an input clock signal, the minimum integer N2 larger than N1 / 2 being cascaded, and said N2 number of cascaded flip-flops. Of the input clock signals are selectively inverted in response to a control signal corresponding to the state of the final stage flip-flop when N2 operation edges of the input clock signals are input to the flip-flops. Inverting means, a means for generating a gate signal at the edge of the input clock signal input first, and a means for controlling the supply of the input clock signal to the inverting means by the gate signal. And odd counter circuit.