JPH0522121A - Frequency divider - Google Patents

Abstract

PURPOSE:To obtain the frequency divider without being affected by the frequency and duty factor of a signal to be frequency divided. CONSTITUTION:A shift register 14 is composed by connecting D flip-flops 1a-5a (only the output of the D flip-flop 5a is non true value side data) to be operated synchronously with the rise of a clock CP in the shape of a loop, and a shift register 15 is composed by connecting D flip-flops 1b-5b (only the output of the D flip-flop 5b is non true value side data) to be operated synchronously with the fall of the clock in the shape of a loop. The exclusive OR of outputs from the D flip-flops la and 2a in the shift register 14 is connected to a set signal input terminal S of an R-S latch 19, and the exclusive OR of outputs from the D flip-flops 3b and 4b in the shift register 15 is connected to a reset signal input terminal R of the R-S latch. The out put of this R-S latch 19 is outputted from a frequency dividing signal output terminal 13. Therefore, the frequency divider is not affected by the frequency or duty factor of the signal to be frequency divided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider for dividing the frequency of an original signal.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional frequency divider. As shown in the figure, the clock input terminal 11 is connected to the trigger signal input terminals T of the D flip-flops 1 to 3 and 6. Further, the clock input terminal 11 is connected to the input terminal of the inverter circuit 7,
Is connected to the trigger signal input terminal T of the D flip-flops 4 and 5. Further, the true value side data output terminal Q of the D flip-flop 1 is
To the data input terminal D of the D flip-flop 2, the true value side data output terminal Q of the D flip-flop 2 to the data input terminal D of the D flip-flop 3, and the true value side data output terminal Q of the D flip-flop 3 to the data of D flip-flop 4. Input terminal D, D
The true value side data output terminal Q of the flip-flop 4 is connected to the data input terminal D of the D flip-flop 5, and the true value side data output terminal Q of the D flip-flop 5 is connected to the data input terminal D of the D flip-flop 6. The non-true value side data output terminals QC of 6 are connected to the data input terminal D of the D flip-flop 1, respectively.

Further, the reset signal input terminal 17 is connected to the reset signal input terminals * R (* indicates a bar. In the figure, the bar is indicated by a bar symbol) of the D flip-flops 1 to 6. Further, the true value side data output terminals Q of the D flip-flops 1 and 2 are connected to the exclusive OR circuit 8
Connected to the input terminal of the D flip-flop 4,
The output terminal Q on the true value side of 5 is connected to the input terminal of the exclusive OR circuit 9. The output terminals of the exclusive OR circuits 8 and 9 are connected to the set signal input terminal S and the reset signal input terminal R of the RS latch 10, respectively.

The output terminal Q of the RS latch 10 is connected to the divided signal output terminal 13.

Next, the operation will be described. FIG. 4 is a timing chart showing the operation of the circuit of FIG. While the reset signal RST on the reset signal input terminal 12 is at the “L” level, the D flip-flops 1 to 6 are in the reset state, and the data output from the true value side data output terminal Q of the D flip-flops 1 to 5 is output. Q1 to Q5 are "H" level, D
The data * Q6 output from the non-true value side data output terminal QC of the flip-flop 6 becomes "L" level. Therefore, the "L" level is given to both of the two input terminals of the exclusive OR circuits 8 and 9, and the levels of the signals G8 and G9 output from the output terminals of the exclusive OR circuits 8 and 9 are It becomes the "L" level.

Next, when the reset signal RST on the reset signal input terminal 11 becomes "H" level, the reset state of the D flip-flops 1 to 6 is released, but the clock CP is input on the clock input terminal 11. Until then, the states of the D flip-flops 1 to 6 do not change.

When the clock CP is input from the clock input terminal 11, the D flip-flops 1 to 3 and 6 are respectively synchronized with the rising edge of the clock CP from the non-true value side data output terminal QC of the D flip-flop 6. Output data * Q6, data Q1, Q2 output from the true value side data output terminals Q of the D flip-flops 1, 2, 5
Memorize The D flip-flops 4 and 5 store the data Q3 and Q4 output from the true value side data output terminals Q of the D flip-flops 3 and 4 in synchronization with the falling of the clock CP.

Therefore, the D flip-flops 1-3,
6 is in synchronization with the rising edge of the clock CP, and D flip-flops 4 and 5 are in synchronization with the falling edge of the clock CP. D flip-flops 1, 2, 3, 4, 5, 6, 1.
The data is shifted onto the loop in the order of.

Here, the data Q output from the true value side data output terminal Q of each of the D flip-flops 1 and 2
Focusing on 1, Q2, Q1 = “H” level, Q2 =
A first state of "L" level is created. Further, focusing attention on the data Q4 and Q5 output from the true value side data output terminals Q of the D flip-flops 4 and 5, respectively,
The second state of "H" level and Q5 = "L" level is created. Similarly, for each of the D flip-flops 1 and 2, a third state of Q1 = "L" level and Q2 = "H" level is created, and the D flip-flops 4,
Q4 = “L” level, Q5 =
A fourth state of "H" level is created.

When the data Q1 and Q2 output from the true value side data output terminals Q of the D flip-flops 1 and 2 are in the first state and the third state, respectively, the output of the exclusive OR circuit 8 G8 becomes "H" level, and in other states, the output G8 of the exclusive OR circuit 8 is "L".
It becomes a level. Similarly, D flip-flops 4, 5
When the data Q4 and Q5 output from the respective true value side data output terminals Q are in the second state and the fourth state, the output G9 of the exclusive OR circuit 9 becomes "H" level, In other states, the output G9 of the exclusive OR circuit 9 is at "L" level.

The RS latch 10 is set in the first and third states and reset in the second and fourth states. Here, the first and third states are created by the D flip-flops 1 and 2 which operate in synchronization with the rising edge of the clock CP, and the second and fourth states use the inverter circuit 7 to cause the falling edge of the clock CP. D that operates in synchronization with
It is created by flip-flops 4 and 5. Therefore, the second state is created 2.5 cycles after the clock when the first state is created, and the third state is created 2.5 cycles after the clock when the second state is created. Therefore, the second state is temporally created in the center of the first and third states. Similarly, after 2.5 cycles of the clock from the timing when the third state is generated, the fourth state is generated, and from the timing when the fourth state is generated, the clock 2.
Since the first state is created after 5 cycles, the fourth state is created temporally in the middle of the third and first states.

Therefore, the output terminal Q of the RS latch 10 outputs a signal Q19 having a duty factor of 50% obtained by dividing the clock CP by a division ratio of 1/5.

[0013]

Since the conventional frequency divider is constructed as described above, the data shift between the D flip-flops 3, 4 and 5 and 6 shown in FIG. It must be performed with a half cycle width of a certain clock CP. When the clock CP has a high frequency, this half cycle width becomes shorter. Therefore, there is a problem that the delay time during data shift between the D flip-flops 3, 4 and between 5, 6 cannot be ignored, and it becomes difficult to operate this frequency divider at high speed.

Further, the half cycle width may be shortened depending on the duty factor of the clock CP, and there is a similar problem.

The present invention has been made to solve the above problems, and an object thereof is to obtain a frequency divider which is not affected by the frequency and duty factor of the clock which is the frequency-divided signal.

[0016]

According to the frequency divider of the present invention, the frequency-divided signal is 1 / n when n is a natural number of 2 or more.
A frequency divider that divides by a division ratio of (2n-1) to generate a divided output from a 2n-1 stage flip-flop that shifts data in synchronization with a rising edge of a divided signal. 2n-1 that shifts data in synchronization with the falling edge of the divided signal
A second shift register including flip-flops of two stages, and a first exclusive OR circuit that generates an exclusive OR of output signal values of the first and second flip-flops of the first shift register , The second n− of the second shift register
A second exclusive logic circuit for generating an exclusive OR of output signal values of the 3rd and 2n-2nd flip-flops;
The leading edge of the divided output is generated in synchronization with the edge from the first level to the second level of the output of the exclusive OR circuit of
And an output edge generation circuit for generating a trailing edge of the frequency-divided output in synchronization with the edge from the first level to the second level of the output of the exclusive OR circuit.

[0017]

In the present invention, the first shift register consisting of 2n-1 stages of flip-flops shifts data in synchronization with the rising edge of the divided signal,
The second shift register composed of 2n-1 stages of flip-flops shifts the data in synchronization with the falling edge of the divided signal, and the first exclusive OR circuit shifts the data of the first shift register to the first shift register. The exclusive OR of the output signal values of the first-stage and second-stage flip-flops is generated, and the second exclusive-logic circuit outputs the second OR of the second shift register.
An exclusive OR of the output signal values of the flip-flops of the (n-3) th stage and the 2n-2nd stage is generated, and the frequency division output edge generation circuit generates the first level from the first level of the output of the first exclusive OR circuit. The leading edge of the divided output is generated in synchronization with the edge to the two levels, and the divided output of the divided output is synchronized with the edge from the first level to the second level of the output of the second exclusive OR circuit. Since the trailing edge is generated, the half-cycle width of the divided signal is not shifted in the first shift register and the second shift register.

[0018]

FIG. 1 is a circuit diagram of a frequency divider showing an embodiment of the present invention. As shown in the figure, the clock input terminal 11
Is a D flip-flop 1 that constitutes the shift register 14.
a to 5a are connected to the trigger signal input terminals. Further, the clock input terminal 11 is connected to the input terminal of the inverter circuit 16, and the output terminal of the inverter circuit 16 constitutes the shift register 15 of the D flip-flop 1.
It is connected to the trigger signal input terminals b to 5b. Further, the true value side data output terminal Q of the D flip-flop 1a in the shift register 14 is the data input terminal D of the D flip-flop 2a, and the true value side data output terminal Q of the D flip-flop 2a is the data of the D flip-flop 3a. The true value side data output terminal Q of the D flip-flop 3a is connected to the input terminal D of the data input terminal D of the D flip-flop 4a.
To the true value side data output terminal Q of the D flip-flop 4a.
Is the data input terminal D of the D flip-flop 5a, and the non-true value side data output terminal QC of the D flip-flop 5a is D
Each of them is connected to the data input terminal D of the flip-flop 1a.

Similarly, the true value side data output terminal Q of the D flip-flop 1b in the shift register 15 is connected to the data input terminal D of the D flip-flop 2b, and the true value side data output terminal Q of the D flip-flop 2b is D. The D flip-flop 3 is connected to the data input terminal D of the flip-flop 3b.
The true value side data output terminal Q of b is the D flip-flop 4b.
To the data input terminal D of the D flip-flop 4b, the true value side data output terminal Q of the D flip-flop 4b to the data input terminal D of the D flip-flop 5b, and the true value side data output terminal QC of the D flip-flop 5b to the data of the D flip-flop 1b. Each is connected to the input terminal D.

Further, the reset signal input terminal 12 is connected to the reset signal input terminals * R of the D flip-flops 1a-5a in the shift register 14 and the D flip-flops 1b-5b in the shift register 15. Further, the true value side data output terminals Q of the D flip-flops 1a and 2a in the shift register 14 are connected to the input terminals of the exclusive OR circuit 17, and the true values of the D flip-flops 3b and 4b in the shift register 15 are true. The value side data output terminal Q is connected to the output terminal of the exclusive OR circuit 18. The output terminals of the exclusive OR circuits 17 and 18 are connected to the set signal input terminal S and the reset signal input terminal R of the RS latch 19, respectively.

The output terminal Q of the RS latch 19 is connected to the divided signal output terminal 13.

Next, the operation will be described. FIG. 2 is a timing chart showing the operation of the circuit of FIG. While the reset signal RST on the reset signal input terminal 12 is at the "L" level, the D flip-flops 1a to 5a in the shift register 14 and the D flip-flops 1b to 5b in the shift register 15 are in the reset state and D True value side data output terminal Q of the flip-flops 1a to 4a and 1b to 4b
Q1a to Q4a and Q1 respectively output from the
b to Q4b are "H" level, D flip-flops 5a,
The data * Q5a and * Q5b respectively output from the non-true value side data output terminal QC of 5b becomes "L" level.
Therefore, the "L" level is given to both of the two input terminals of the exclusive OR circuits 17 and 18, and the signal G output from the output terminals of the exclusive OR circuits 17 and 18 respectively.
The levels of 17 and G18 are "L" level.

Next, when the reset signal RST on the reset signal input terminal 12 becomes "H" level, the reset states of the D flip-flops 1a-5a in the shift register 14 and the D flip-flops 1b-5b in the shift register 15 are reset. However, until the clock CP is input to the clock input terminal 11, each of the D flip-flops 1 to
The state of 6 does not change.

When the clock CP is input from the clock input terminal 11, the D flip-flops 1a and 2a to 5a in the shift register 14 are synchronized with the rising edge of the clock CP and the non-true side of the D flip-flop 5a. The data * Q5a output from the data output terminal QC and the data Q1a to Q4a output from the true value side data output terminals Q of the D flip-flops 1a to 4a are stored.
In addition, the D flip-flop 1b in the shift register 15
And 2b to 5b are data * Q5b output from the non-true value side data output terminal QC of the D flip-flop 5b and true value side data output of the D flip-flops 1b to 4b, respectively, in synchronization with the fall of the clock CP. The data Q1b to Q4b output from the terminal Q are stored.

Therefore, the D flip-flops 1a to 5a in the shift register 14 are synchronized with the rising of the clock CP, and the D flip-flops 1a, 2a, 3a and 4 are synchronized.
The data is shifted onto the loop in the order of a, 5a, 1a .... Similarly, the D flip-flops 1b to 5b in the shift register 15 are synchronized with the falling edge of the clock CP, and the D flip-flops 1b, 2b, 3b, 4b and 5 are synchronized.
The data is shifted onto the loop in the order of b, 1b ....

Here, focusing on the data Q1a and Q2a output from the true value side data output terminals Q of the D flip-flops 1a and 2a in the shift register 14,
A first state of Q1a = "H" level and Q2a = "L" level is created. In addition, D in the shift register 15
Focusing on the data Q3b and Q4b output from the true value side data output terminals Q of the flip-flops 3b and 4b, respectively, a second state of Q3b = "H" level and Q4b = "L" level is created. Similarly, shift register 1
A third state of Q1a = "L" level and Q2a = "H" level is created for each of the D flip-flops 1a and 2a in the register 4, and Q3b for each of the D flip-flops 3b and 4b in the shift register 15. =
A fourth state of "L" level and Q4b = "H" level is created.

When the data Q1a and Q2a output from the true value side data output terminals Q of the D flip-flops 1a and 2a in the shift register 14 are in the first state and the third state, the exclusive logic is applied. Output G of sum circuit 17
17 becomes "H" level, and in other states, the output G17 of the exclusive OR circuit 17 becomes "L" level. Similarly, when the data Q3b and Q4b output from the true value side data output terminals Q of the D flip-flops 3b and 4b in the shift register 15 are in the second state and the fourth state, respectively, they are exclusive. The output G18 of the OR circuit 18 is at the "H" level, and in other states, the output G18 of the exclusive OR circuit 18 is at the "L" level.

The RS latch 10 is set in the first and third states and reset in the second and fourth states. Here, the first and third states are created by the D flip-flops 1a and 2a in the shift register 14 which operate in synchronization with the rising of the clock CP, and the second and fourth states are generated.
The state is created by the D flip-flops 3a and 4a in the shift register 15 which operates in synchronization with the fall of the clock CP using the inverter circuit 7. Therefore, the second state is created 2.5 cycles after the clock when the first state is created, and the third state is created 2.5 cycles after the clock when the second state is created. Therefore, the second state is temporally created in the center of the first and third states. Similarly, after 2.5 cycles of the clock from the timing when the third state is generated, the fourth state is generated, and from the timing when the fourth state is generated, the clock 2.
Since the first state is created after 5 cycles, the fourth state is created temporally in the middle of the third and first states.

Therefore, the output terminal Q of the RS latch 10 outputs a signal Q19 having a duty factor of 50%, which is obtained by dividing the clock CP by a division ratio of ⅕, which is output from the divided signal output terminal 13. Is output.

As described above, according to the present invention, the D flip-flops 1a to 5a (only the output of the D flip-flop 5a is the non-true value side data) operating in synchronization with the rising edge of the clock are connected in a loop. A shift register configured by connecting the configured shift register 14 and D flip-flops 1b to 5b (only the output of the D flip-flop 5b is the non-true value side data) that operate in synchronization with the falling edge of the clock in a loop shape. 15, the exclusive OR of the outputs of the D flip-flops 1a and 2a in the shift register 14 by the exclusive OR circuit 17 is applied to the set signal input terminal S of the RS latch 19 in the D flip-flop in the shift register 15. The exclusive OR of the outputs of 3b and 4b by the exclusive OR circuit 18 is applied to the reset signal input terminal R of the RS latch. Since the output of the RS latch 19 is output from the frequency division signal output terminal 13 as the output signal of the frequency divider, a frequency divider capable of giving a high frequency clock CP (divided signal) is obtained. be able to.

Although FIG. 1 shows a frequency divider having a division ratio of 1/5, when n is a natural number of 2 or more, the division ratio is 1.
The (/ 2n-1) frequency divider also has 2n-1 D flip-flops 1 that operate in synchronization with the rising edge of the clock CP.
This can be easily realized by a shift register composed of a to (2n-1) a and a shift register composed of 2n-1 D flip-flops 1b to (2n-1) b which operate in synchronization with the falling of the clock CP. In this case, the exclusive OR of the outputs of the D flip-flops 1a and 2a is applied to the set signal input terminal S of the RS latch by the exclusive OR of the outputs of the D flip-flops (2n-3) b and (2n-2) b. By giving a logical sum to the reset signal input terminal R of the RS latch, the output signal of the frequency divider can be output from the output terminal of the RS latch.

In FIG. 1, the exclusive OR circuit 17,
18 output terminals are respectively connected to the set signal input terminal S and the reset signal input terminal R of the RS latch 19, and the output signal of the frequency divider is synchronized with the rising edge of the output G17 of the exclusive OR circuit 17. Rising, exclusive OR circuit 1
Although the example in which the output G18 of FIG. 8 falls in synchronization with the rise of the output G18 is shown, the output terminals of the exclusive OR circuits 17 and 18 are connected to the reset signal input terminal R and the reset signal input terminal S of the RS latch 19, respectively. The output signal of the frequency divider is
The exclusive OR circuit 17 may fall in synchronization with the rising edge of the output G17 and may rise in synchronization with the rising edge of the output G18 of the exclusive OR circuit 18.

Further, instead of the RS latch, a latch that performs an edge operation is used, and the output signal of the frequency divider rises in synchronization with the fall of the output G17 of the exclusive OR circuit 17, and the exclusive OR is obtained. It falls in synchronization with the fall of the output G18 of the circuit 18, or the exclusive OR circuit 17
The output G17 may fall in synchronization with the fall of the output G17, and the output G18 of the exclusive OR circuit 18 may rise in synchronization with the fall of the output G18.

[0034]

As described above, according to the present invention, when the frequency-divided signal is a natural number of 2 or more, 1 / (2n-
A frequency divider that generates a frequency-divided output by performing frequency division according to the frequency division ratio of 1), and includes a first 2n-1 stage flip-flop that shifts data in synchronization with the rising edge of the frequency-divided signal. Shift register, a second shift register including 2n-1 stages of flip-flops that shift data in synchronization with the falling edge of the divided signal, and first and second stages of the first shift register. First exclusive OR circuit for generating an exclusive OR of the output signal values of the flip-flops, and the 2n-3rd stage of the second shift register, the second
A second exclusive logic circuit that generates an exclusive OR of the output signal values of the n−2 stage flip-flops and an edge from the first level to the second level of the output of the first exclusive OR circuit. In synchronization, the leading edge of the divided output is generated, and the trailing edge of the divided output is generated in synchronization with the edge from the first level to the second level of the output of the second exclusive OR circuit. Since the divided output edge generation circuit is provided, the divided signal is not shifted by the half cycle width in the first shift register and the second shift register, which affects the frequency and duty factor of the divided signal. There is an effect that it is possible to provide a frequency divider that is hard to receive.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a frequency divider showing an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a conventional frequency divider.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

[Explanation of symbols]

 11 clock input terminal 13 frequency division signal output terminal 14 and 15 shift register

Claims (1)

Claim: What is claimed is: 1. A frequency division for dividing a divided signal by a dividing ratio of 1 / (2n-1) when n is a natural number of 2 or more, and generating a divided output. A first n-stage flip-flop that shifts data in synchronization with a rising edge of the divided signal.
Second shift register and a 2n-1 stage flip-flop that shifts data in synchronization with the falling edge of the divided signal.
Shift register, a first exclusive OR circuit that generates an exclusive OR of the output signal values of the first-stage and second-stage flip-flops of the first shift register, and the second shift register 2n-3 stage, 2n-2
A second exclusive logic circuit for generating an exclusive OR of the output signal values of the flip-flops of the stages, and the output of the first exclusive OR circuit is synchronized with the edge from the first level to the second level. To generate a leading edge of the divided output and generate a trailing edge of the divided output in synchronization with an edge of the output of the second exclusive OR circuit from the first level to the second level. A frequency divider having a frequency division output edge generation circuit.