JPH05347555A - Variable frequency divider circuit - Google Patents

Abstract

PURPOSE:To always obtain a dividing signal of the 50% duty despite the change of the dividing ratio. CONSTITUTION:A counter 22 counts the master clocks and outputs the dividing pulses every time the count value is equal to the dividing ratio and also is reset. A comparator 25 compares the count value of the counter 22 with the integer value equal to 1/2 dividing ratio and outputs a coincidence pulse when the coincidence is secured between both values. Each of selection circuits 27-30 selects a coincidence pulse with each shift equal to the half cycle of the master clock when the dividing ratio is odd and then selects the coincidence pulse out of the comparator 25. Then the output circuits 31 and 33 apply the 1/2 division to the OR secured between the dividing pulse of the counter 22 and the coincidence pulse of the selection circuit and then outputs the dividing signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency dividing circuit, and more particularly to a variable frequency dividing circuit for varying a frequency dividing ratio to divide a clock.

[0002]

2. Description of the Related Art FIG. 4 shows a circuit diagram of an example of a conventional variable frequency dividing circuit. In the figure, 11 is a down counter, which is supplied with the master clock MCK shown in FIG. 5A from the terminal 12 and from the terminal 13 with the data N of the division ratio shown in FIG. 5B.
-1 is supplied. The down counter 11 counts down the master clock MCK, and outputs from the terminal 14 the frequency-divided signal shown in FIG. 5 (D) which becomes H level only when the count value shown in FIG. 5 (C) is 0. Further, at the falling edge of this divided signal, data from the terminal 13 is loaded and down counting is performed. This allows the master clock M
A divided signal obtained by dividing CK by N is obtained.

[0003]

The conventional circuit has a problem that the duty ratio of the frequency-divided signal obtained varies depending on the frequency-division ratio, so that it is not possible to always obtain a frequency-divided signal with a duty ratio of 50%.

The present invention has been made in view of the above points,
An object of the present invention is to provide a variable frequency dividing circuit that can always obtain a frequency division signal with a 50% duty even if the frequency division ratio changes.

[0005]

A variable frequency dividing circuit according to the present invention includes a counter for counting a master clock, outputting a frequency dividing pulse each time the count value reaches a value of a frequency dividing ratio, and resetting the divided pulse. Selects a comparison circuit that outputs a match pulse when the count value is compared with an integer value of 1/2 of the division ratio and matches, and a match pulse that is shifted by a half cycle of the master clock when the division ratio is odd. Then, when it is an even number, a selection circuit for selecting and extracting the matching pulse from the comparison circuit,
It has an output circuit which divides the logical sum of the frequency-divided pulse from the counter and the coincidence pulse from the selection circuit into 1/2 and outputs a frequency-divided signal.

[0006]

In the present invention, the comparison circuit and the selection circuit generate the coincidence pulse indicating the intermediate position of the division pulse interval, and divide the logical sum of the division pulse and the coincidence pulse by 1/2. 50% surely even if the division ratio changes arbitrarily
Obtain the duty divided signal.

[0007]

1 shows a circuit diagram of an embodiment of the circuit of the present invention.

In the figure, the data N of the frequency division ratio is input from the terminal 20 and supplied to the 2's complement circuit 21. 2's complement circuit 2
1 inverts each bit of the data N, adds 1 to the least significant bit to generate two's complement data, and supplies the two's complement data to the counter 2 and the shift circuit 23.

The counter 22 is supplied with the master clock from the terminal 24 to count up, supplies the count value to the comparison circuit 25, and supplies the carry to the flip-flop 26 and the data load terminal LD of its own circuit. . The counter 22 loads the 2's complement data from the 2's complement circuit 21 when a carry is supplied to the data load terminal LD. This allows the master clock M
The counter 22 outputs a carry every N pulses of CK,
The master clock MCK is divided by 1 / N. The flip-flop 26 latches the carry with the master clock MCK, delays it by one cycle of the master clock, and supplies it to the OR circuit 31 as a divided pulse.

The shift circuit 23 shifts the 2's complement data to the right by 1
Bit shift, that is, ½, is supplied to the comparison circuit 25. The comparison circuit 25 compares the shifted 2's complement data with the count value of the counter 22 except for the most significant bit, and generates a coincidence pulse that becomes “1” when they coincide with each other and outputs the coincidence pulse to the flip-flops 27 and 28, respectively. Supply.

The flip-flop 27 latches the coincidence pulse at the rising edge of the master clock MCK inverted by the inverter 29, that is, at a timing delayed by a half cycle of the master clock, and supplies it to the selector 30. The flip-flop 28 latches the coincidence pulse when the master clock MCK rises. Since there is a delay in the counter 22, the shift circuit 23, and the comparison circuit 25, the flip-flop 28 latches the match pulse at a timing delayed by about one cycle of the master clock MCK and supplies it to the selector 30.

The selector 30 is supplied with the least significant bit of the frequency division ratio data N from the terminal 32. If the least significant bit is "1", that is, the frequency division ratio is an odd number, a half cycle delay from the flip-flop 27 is performed. The selected match pulse is selected, and when the least significant bit is “0”, that is, the division ratio is even, the match pulse delayed by one cycle from the flip-flop 28 is selected and the selected match pulse is supplied to the OR circuit 31. To do.

The OR circuit 31 takes the logical sum of the divided pulse from the flip-flop 26 and the coincidence pulse from the selector 30 and supplies it as a clock to the flip-flop 33. The flip-flop 33 is supplied with the inverted output of its own circuit to the data terminal to form a 1/2 frequency divider, and the pulse from the AND circuit 31 is frequency divided by 1/2 and output from the terminal 34 as a divided signal. To be done.

Here, using a 4-bit counter 22,
A case where the frequency division ratio N is 7 will be described. Figure 2
With respect to the master clock MCK and the frequency division ratio data N (= 7) shown in (A) and (B), the count value of the counter 22 changes as shown in hexadecimal notation in FIG. As a result, the flip-flop 26 outputs the coincidence pulse shown in FIG. 2 (D), and the comparison circuit 25 generates the coincidence pulse shown in FIG. 2 (E). Since the frequency division ratio is odd, the selector 30 outputs the coincidence pulse delayed by a half cycle of the master clock shown in FIG. 2F, and the terminal 34 outputs the pulse shown in FIG. 2D and the pulse shown in FIG. 2F. Figure 2 that divides the logical sum of
The frequency division signal of 50% duty shown in (G) is output.

Next, a case where the 4-bit counter 22 is used and the frequency division ratio N is 6 will be described. FIG. 3 (A),
Master clock MCK shown in (B), data N of frequency division ratio
In contrast to (= 6), the count value of the counter 22 is as shown in FIG.
It changes as shown in hexadecimal notation in (C). As a result, the flip-flop 26 outputs the match pulse shown in FIG. 3 (D), and the comparison circuit 25 generates the match pulse shown in FIG. 3 (E). Since the division ratio is even, the selector 30 is shown in FIG.
A match pulse delayed by one cycle of the master clock shown in (F) is output, and the logical sum of the pulse shown in FIG. 2D and the pulse shown in FIG.
The frequency division signal of 50% duty shown in (G) is output.

As described above, the divided pulse is generated and
By generating a coincidence pulse that indicates the intermediate position of the division pulse interval and dividing the logical sum of the division pulse and the coincidence pulse by 1/2, a 50% duty cycle is ensured even if the division ratio changes arbitrarily. Can be obtained.

[0017]

As described above, according to the variable frequency dividing circuit of the present invention, it is possible to obtain a frequency-divided signal having a duty of 50% at all times even if the frequency dividing ratio changes, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a circuit of the present invention.

FIG. 2 is a signal timing chart of the circuit of the present invention.

FIG. 3 is a signal timing chart of the circuit of the present invention.

FIG. 4 is a circuit diagram of a conventional circuit.

FIG. 5 is a signal timing chart of a conventional circuit.

[Explanation of symbols]

 21 2's complement circuit 22 counter 23 shift circuit 25 comparison circuit 26-28, 33 flip-flop 29 inverter 30 selector 31 OR circuit

Claims (1)

[Claims] 1. A counter (22) which counts a master clock and outputs and resets a frequency division pulse each time the count value reaches a frequency division ratio value, and a counter (22) which reduces the count value to 1 / Comparison circuit (25) that outputs a coincidence pulse when compared with the integer value of 2 and coincides
And a selecting circuit (27 to 3) that selects a matching pulse shifted by a half cycle of the master clock when the division ratio is odd, and selects and extracts a matching pulse from the comparison circuit when the dividing ratio is even.
0) and an output circuit (31, 33) for dividing the logical sum of the divided pulse from the counter and the coincidence pulse from the selection circuit by 1/2 and outputting the divided signal. Variable divider circuit.