JP2655509B2 - Serial / parallel conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel converter, and more particularly to a serial / parallel converter to which two serial data groups shifted by a half cycle of a clock signal are input.

[0002]

2. Description of the Related Art A conventional serial / parallel conversion circuit to which two serial data groups that can be selected by a user are input is shown in FIG. In FIG. 4, reference numeral 1 denotes a shift register that takes in the serial data signal SI in response to the falling of the clock signal CLK, and 2 denotes a storage register that stores the parallel output of the shift register 1 in response to the control signal C. Note that the output of the storage register 2 is the output of the serial / parallel conversion circuit.

The clock signal CLK of the shift register 1 is either a clock signal CLK1 according to the mode signal M or a clock signal CL delayed by a half cycle by the inverter 3.
K2. That is, the clock signals CLK1, CLK
2 is selected by the switching circuit 4. In this case, the clock signal CLK1 is selected when the mode signal M is "1" by the user, and the clock signal CLK2 is selected when the mode signal M is "0" by the user.

The control signal C of the storage register 2 becomes control signals C1 and C2 according to the mode signal M. here,
The control signal C1 is a carrier signal of a counter (for example, an octal counter) 5 that counts the clock signal CLK1, the control signal C2 is a carry signal of a counter (for example, an octal counter) 6 that counts the clock signal CLK2, These are selected by the switching circuit 7. In this case, when the mode signal M is "1", the control signal C1 is selected. On the other hand, when the mode signal M is "0", the control signal C1 is selected.
2 is selected. The switching circuits 4 and 7 can be constituted by two transfer gates 41 and 42 and an inverter 43 as shown in FIG.

Next, the operation of FIG. 4 will be described with reference to FIG.

When the mode signal M = "1", referring to FIG. 6A, the serial data signal SI (= SI
1) is input in synchronization with the rise of the clock signal CLK1. At this time, the switching circuit 4 has selected the clock signal CLK1, and as a result, the shift register 1 sequentially takes in the serial data D1 to D8 each time the clock signal CLK1 falls. At the same time, the switching circuit 7 selects the control signal C1. Therefore, at time t1 when all the serial data D1 to D8 are taken into the shift register 1,
Then, the control signal C1, which is the carry signal of the counter 5, rises. As a result, the output of the shift register 1 is stored in the storage register 2, and the parallel data PO is output from the storage register 2. The parallel data PO is continuously output until the next control signal C1 is generated.

On the other hand, when the mode signal M = "0", FIG.
Referring to FIG. 2B, the serial data signal SI (= S
I2) is input in synchronization with the rise of the clock signal CLK2, that is, the fall of the clock signal CLK1. At this time, the switching circuit 4 has selected the clock signal CLK2, and as a result, the shift register 1
2, the serial data D1 'to D8' are sequentially taken in at every falling of the clock signal CLK1. At the same time, the switching circuit 7 selects the control signal C2. Therefore, at time t2 when all the serial data D1 'to D8' are taken into the shift register 1, the control signal C2 which is the carry signal of the counter 5 rises. As a result, the output of the shift register 1 is stored in the storage register 2, and the parallel data PO is output from the storage register 2. The parallel data PO is continuously output until the next control signal C2 is generated.

However, in the conventional serial / parallel conversion circuit shown in FIG. 4, one of two types of serial data shifted by a half cycle of the clock signal is taken into the left register 1 at the falling edge of the clock signal CLK1, and the other is taken. Since the data is taken into the shift register 1 at the rise of the clock signal CLK1, the inverter 3 for switching the clock signal is used.
And a switching circuit 4, and counters 5 and 6 and a switching circuit 7 for switching control signals for storing data from the shift register 1 to the storage register 2 are required. There are issues. The parallel data output from the storage register 2 is 2
There is also a problem that the type of serial data is not in phase, and as a result, a circuit for performing data processing in a subsequent stage becomes complicated.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a serial / parallel conversion circuit which has a small circuit scale and in which output parallel data between two types of serial data is in phase.

[0010]

According to the present invention, a first serial data signal which changes at the rising edge of a clock signal and a second serial data signal which changes at the falling edge of the clock signal are provided. A delay circuit for delaying the serial data signal including the half cycle of the clock signal,
The first serial data signal and the second serial data signal are input to the shift register after having the same phase.

[0011]

According to the above-described means, the first serial data signal and the second serial data signal are input to the shift register in the same phase, so that the clock signal of the shift register and the control signal of the storage register are equal to each other. The same is applied to the first serial data signal and the second serial data signal.

[0012]

FIG. 1 is a block circuit diagram showing a first embodiment of a serial / parallel conversion circuit according to the present invention. FIG.
In FIG. 4, instead of the inverter 3, the switching circuit 4, the counter 6, and the switching circuit 7 shown in FIG. Is provided. The switching circuit 9 selects the serial data signal SI or the delayed serial data signal SI ′. In this case, the serial data signal SI ′ delayed when the mode signal M is “1” is selected, while the mode signal M
Is "0", the serial data signal SI 'is selected.

Next, the operation of FIG. 1 will be described with reference to FIG.

When the mode signal M = "1", referring to FIG. 2A, the serial data signal SI (= SI
1) is input in synchronization with the rise of the clock signal CLK1. At this time, the switching circuit 9 has selected the flip-flop 8, so that the serial data signal SI is converted into a serial data signal SI 'delayed by half a clock cycle. As a result, the delayed serial data signal S
I ′ is input to the shift register 1 in synchronization with the falling of the clock signal CLK1. That is, the shift register 1 sequentially takes in the serial data D1 to D8 at every rising of the clock signal CLK1. At time t3 when all the serial data D1 to D8 are taken into the shift register 1, the control signal C1, which is the carry signal of the counter 5, rises. As a result, the output of the shift register 1 is stored in the storage register 2, and the parallel data PO is output from the storage register 2. The parallel data PO is continuously output until the next control signal C1 is generated.

When the mode signal M = "0", referring to FIG. 2B, the serial data signal SI (= SI
2) is input in synchronization with the falling of the clock signal CLK1. At this time, the switching circuit 9 outputs the serial data signal SI
Therefore, also in this case, the shift register 1 sequentially takes in the serial data D1 'to D8' every time the clock signal CLK1 rises. At time t4 when all the serial data D1 'to D8' are taken into the shift register 1, the control signal C1, which is the carry signal of the counter 5, rises. As a result, shift register 1
Is stored in the storage register 2 and the parallel data P
O is output from the storage register 2. The parallel data PO is continuously output until the next control signal C1 is generated.

As described above, according to the first embodiment of the present invention, the serial data signal SI1 is also changed to the serial data signal S1.
I2 is also input to the shift register 1 in the same phase. Accordingly, the shift register 1 has one type of clock signal, and the storage register 2 has one type of control signal.

FIG. 3 is a block circuit diagram showing a second embodiment of the serial / parallel conversion circuit according to the present invention. In FIG. 3, the switching circuit 1 is replaced with the switching circuit 9 in FIG.
0, an OR circuit 11 is provided. The switching circuit 10 operates similarly to the switching circuit 9 in FIG. That is, the serial data signal SI is sent to the flip-flop 8 or sent directly to the OR circuit 11. In this case, when the mode signal M is "1", the serial data signal SI is sent to the flip-flop 8, and when the mode signal M is "0", the serial data signal SI is sent directly to the OR circuit 11. Is done. Therefore, the shift register 1, the storage register 2, and the counter 5 in FIG. 3 perform the same operations as those in FIG.

In the above-described embodiment, the first serial data signal SI1 is delayed by the flip-flop 8, but the second serial data signal SI2 may be delayed by the flip-flop 8. In this case, the parallel data from the storage register 2 is shifted by one clock between the two serial data signals SI1 and SI2. The switching circuits 9 and 10 shown in FIGS.
Can be configured similarly to the circuit shown in FIG.

[0019]

As described above, according to the present invention, two types of serial data signals that differ by a half cycle of the clock are input to the shift register in the same phase, so that the clock signal of the shift register and the serial signal of the storage register The circuit configuration for generating the control signal can be simplified, and the circuit scale of the serial / parallel conversion circuit can be reduced. Also, the parallel data output from the storage register can be made in phase between the two types of serial data signals. As a result, a circuit for performing data processing in the subsequent stage can be simplified.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of a serial / parallel conversion circuit according to the present invention.

FIG. 2 is a timing chart showing an operation of the circuit of FIG. 1;

FIG. 3 is a block circuit diagram showing a second embodiment of the serial / parallel conversion circuit according to the present invention.

FIG. 4 is a block circuit diagram showing a conventional serial / parallel conversion circuit.

FIG. 5 is a circuit diagram showing an example of the switching circuit of FIG. 4;

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 4;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 shift register 2 storage register 3 inverter 4 switching circuit 5, 6 counter 7 switching circuit 8 flip-flop 9, 10 switching circuit 11 OR circuit

Claims (6)

(57) [Claims] 1. A serial data signal (SI) including a first serial data signal (SI1) changing at the rising edge of a clock signal (CLK1) and a second serial data signal (SI2) changing at a falling edge of the clock signal. ) For a half cycle of the clock signal, a switching circuit (9) for selecting one of the serial data signal and the delayed serial data signal, and an output of the switching circuit for the clock. A shift register (1) that takes in the rising or falling edge of the signal; and a control signal (C) when the rising or falling edge of the clock signal is counted and the counted value reaches a predetermined value.
A serial / parallel conversion circuit comprising: a counter (5) for generating 1); and a register (2) for storing a parallel output of the shift register based on the control signal. 2. The switching circuit selects the serial data signal when the serial data signal is the first serial data signal, and selects the delay when the serial data signal is the second serial data signal. 2. The serial / parallel conversion circuit according to claim 1, wherein the selected serial data signal is selected. 3. The selection circuit selects the delayed serial data signal when the serial data signal is the first serial data signal, and selects the delayed serial data signal when the serial data signal is the second serial data signal. 2. The serial / parallel conversion circuit according to claim 1, wherein said serial data signal is selected. 4. A serial data signal (SI) including a first serial data signal (SI1) changing at a rising edge of a clock signal (CLK1) and a second serial data signal (SI2) changing at a falling edge of the clock signal. ) First
A switching circuit (10) for switching between the output of the clock signal and a second output; a delay circuit (8) for delaying the first output of the switching circuit by a half cycle of the clock signal; An OR circuit (11) for passing the output of the delay circuit; a shift register (1) for receiving the output of the OR circuit in response to the rising or falling of the clock signal; and a rising or falling edge of the clock signal. A serial counter comprising: a counter (5) for counting and generating a control signal when the counted value reaches a predetermined value; and a register (2) for storing a parallel output of the shift register based on the control signal. / Parallel conversion circuit. 5. The switching circuit selects the first output when the serial data signal is the first serial data signal, and selects the first output when the serial data signal is the second serial data signal. The serial / parallel conversion circuit according to claim 4, wherein the output of the serial / parallel converter is selected. 6. The switching circuit selects the second output when the serial data signal is the first serial data signal, and selects the second output when the serial data signal is the second serial data signal. The serial / parallel conversion circuit according to claim 4, wherein the first output is selected.