JPH03267820A - High speed digital counter - Google Patents

Abstract

PURPOSE:To attain count without malfunction even to a high speed clock by providing a frequency divider applying 1/N frequency division to an input clock, and outputting N series of frequency division signals whose phases are deviated by one clock each, N sets of counters counting respectively N series of frequency division signals from the frequency divider and an adder summing up the count of the N sets of counters. CONSTITUTION:An input clock is subject to 1/N frequency division by a frequency divider 31 to form N series of frequency division signals whose phases are deviated by one clock each and they are counted by separate counters 32-1-32-N and the counts of the counters 32-1-32-N are added by an adder 33 and a count result being the output of the device is outputted. In such a case, the speed of the frequency division signal by the counters 32-1-32-N is 1/N of the input clock, then malfunction due to a delayed carry is prevented. Thus, count is implemented without malfunction even against a high speed clock.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to enable high-speed digital counters that are used, for example, to measure the phase difference between two signals, to perform counting without malfunctioning even with high-speed clocks. A frequency divider that divides the clock by N and outputs divided signals of 9N series with a phase shift of 1 clock, and divides the divided signals of the N series of the frequency divider into N series of the frequency divider [31]. counter, and an adder for summing the count values of the N counters.

[Industrial application field]

The present invention relates to high speed digital counters.

Digital counters are used in a variety of applications.

For example, when trying to measure the phase difference between two signals A and B using an input clock, count the input clock using a digital counter only during the period corresponding to the phase difference, and use the counted value to correspond to the phase difference. I'm letting you do it. On the other hand, as communication speeds increase, input clocks tend to become faster.
Therefore, there is a need for a high-speed digital counter that can count high-speed clocks.

[Conventional technology]

Conventionally, when a value to be measured is large, a digital counter is used by connecting a plurality of counters in series.

[Problem to be solved by the invention]

However, in the method of vertically connecting a plurality of counters, the number of connected stages increases as the value to be measured becomes larger. In order to perform counting with such a digital counter having a vertically connected configuration, the counter at the lower stage in the counter array sequentially increases the carry signal to the counter at the upper stage. Therefore, as the number of connected stages of the counter increases, the delay time caused by this carry operation increases, and the delay of this carry cannot catch up with the high speed clock, causing the problem that the digital counter does not function properly.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a high-speed digital counter that can count even with high-speed clocks without malfunctioning.

[Means to solve the problem]

FIGS. 1 to 3 are explanatory diagrams of the principles of the present invention, respectively.

As one form of the high-speed digital counter according to the present invention, as shown in FIG. 3, frequency division, and N series frequency division signals of W31 are respectively applied to the N series counter 32 (1) of the frequency divider [31].
) to 32@, and an adder 33 for summing the count values of N counters 32(1) to 32@.

As shown in FIG. 12, the high-speed digital counter according to the present invention measures the phase difference between two signals A and B using an input clock, and divides the input clock by N. A frequency divider 31 that outputs N series of frequency divided signals whose phase is shifted by one clock, and N counters 32 that respectively receive the N series of frequency divided signals of the frequency divider 31 (
1) ~ 32@ and N over the period of the phase difference between the two signals
a gate generation circuit 34 that generates a gate signal that enables the N counters 32(1) to 32■; an adder 33 that totals the count values of the N counters 32(1) to 32@; An adder 35 shifts and sums the relative phases of signals A and B, and the total value of the adder 33 is compared with a predetermined set value, and when the total value is close to this set value, the phase shift circuit 35 shifts the two The comparator circuit 36 includes a comparison circuit 36 that controls the phase shift of at least one of the signals, and a correction circuit 37 that corrects the total value from the adder 33 by the phase shifted by the phase shift circuit 35.

As another form of the high-speed digital counter according to the present invention, as shown in FIG.
(N is an integer and a multiplication value of 2 with I as a power exponent) A frequency divider 30 that divides the frequency and outputs N series frequency divided signals whose phases are shifted by one clock, and A counter 38 that counts one series of frequency-divided signals and generates bits higher than the power exponent I in the count result value, and N of the frequency divider 30.
It also includes an exclusive OR circuit 39 that generates bits below the exponent in the count output value by exclusive ORing a series of frequency-divided signals.

[Effect]

In the embodiment shown in FIG. 1, the frequency of the input clock is divided by N by the frequency divider 31 to create N series of frequency-divided signals, which are each counted by separate counters 32(1) to 320. (1) The count value of ~320 is added to the adder 3.
3 and outputs the count result value which is the device output. As a result, the speed of the frequency-divided signals in each of the counters 32(1) to 320 becomes 1/N of the input clock, thereby preventing malfunctions due to carry delays.

In the configuration shown in FIG. 2, when the phases of two signals A and B become close, it can be detected by the comparison result by the comparator circuit 36, and the phase approach value is determined by separating the close phases by the phase shift circuit 35. The correction circuit 37 prevents malfunctions and corrects the count value for the separated phase.

In the embodiment shown in FIG. 3, the upper bits of the count result value are generated by a counter 39 that counts one series of frequency-divided signals, and the remaining lower bits are generated by an exclusive OR circuit 39 that generates the exclusive OR of the frequency-divided signals. This reduces the number of counters and adders required.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings. In addition,
Throughout the drawings below, circuits with the same reference numbers represent circuits with the same function.

A high speed digital counter as an embodiment of the present invention is shown in FIG. Further, a time chart of signals of each part of this high-speed digital counter is shown in FIG. This high-speed digital counter is commonly used in a circuit that measures the phase difference between signal A and signal B using high-speed clock HCLK.

In FIG. 2, frequency divider 1 uses high-speed clock HCLK
(Figure 5 (a)) is divided into 4 to create four divided clocks CLK1 to CLK4 whose phases are shifted by each high-speed clock (
This is a circuit that outputs fe) to (h)) in Fig. 5.

The four counters 2(1) to 2■ are circuits that respectively count the frequency division counters CLK1 to CLK4 from the frequency divider 1, and the count values are output to the adder 3. The adder 3 adds up the count values from these counters 2(1) to 2■, and calculates the output value of the high-speed digital counter (hereinafter referred to as
(referred to as the count result value).

The JK flipflop 4 is a circuit that generates a gate signal Q (Fig. 5(d)) having a length corresponding to the phase difference between the signals A and B (Fig. 5(bl and (C)). Q
is input as an enable signal to each counter 2(1) to 2■.

The operation of this example circuit will be explained below.

Frequency divider 1 divides the frequency of the high-speed clock HCLK by 4, and generates four divided clocks CLK whose phases are shifted by one high-speed clock.
1 to CLK4, and each counter 2 (1) to 2 is enabled for the period of the gate signal Q (corresponding to the phase difference between the outputs A and B) from the JK frimbflop 4. The frequency-divided clocks CLK1 to CLK4 inputted to (1) to 2) are counted, respectively.

The count values of each counter 2(1) to 2■ are added to the adder 3.
This total value is the same as the number of high-speed clocks HCLKO input during the period of the gate signal Q, and therefore the phase difference between outputs A and B can be measured with high-speed clock accuracy.

This makes it possible to prevent malfunctions caused by delays in the carry of counter columns, which occur in conventional digital counters with a vertically connected configuration.

Another embodiment of the invention is shown in FIG. In this embodiment, the gate signals input to each counter 2(1) to 2■ are
Divided clock C input to each counter 2(1) to 2■
It is designed to synchronize with the phase of LK1 to CLK4, and JK flip-flops 4(1) to 4■ are provided corresponding to each counter 2(1) to 2■, and each JK flip-flop 4(1) to 4■ The divided clocks CLK1-CLK4 from the frequency divider 1 are respectively input as clock inputs to the counters 1, thereby generating gate signals Q(1)-Q2 for each counter 2(1)-22.

Yet another embodiment of the invention is shown in FIG.

This embodiment circuit is an improvement of the above two embodiment circuits.

That is, in the above-described embodiment circuit, if the phase difference between signals A and B approaches, malfunction may occur. For example, FIG. 7 shows a time chart when the phase difference between signals A and B approaches each other in the circuit of the embodiment shown in FIG. in this case,
The gate signals Q■ and Q■ generated during the period when signals A and B were whistled together (the phase where the start pulse and end pulse overlap and the count result value is close to the maximum) reversed the previous state. Since the counters 2 and 2 will be output, the operation of the counters 2 and 2 will be in an undefined state, and therefore the adder 3
The total value of becomes unreliable. Therefore, when the signals A and B are close in phase, the circuits of the two embodiments described above cannot be used.

The embodiment circuit shown in FIG. 8 solves this problem. This embodiment circuit has additional circuits added to the embodiment circuit shown in FIG. 5, and includes a delay element 5 that delays and shifts the signal A by a certain phase, and selects either the signal A or the signal A via the delay element 5. A selector 6 is provided, and using the signal *A selected by this selector 6, each JK flip-flop 4 (1)
~4■ are used to generate gate signals Q(1) to Q■.

Further, on the output side of the adder 3, a comparator 7 that compares the total value of the adder 3 with a predetermined setting value, a selector 9 that selects the correction value C or O, and a selector 9 that compares the total value of the adder 3 with a predetermined setting value. An adder 8 is provided to add the output values of the selectors 6 and 9, and the selectors 6 and 9 are connected in accordance with the comparison result of the comparator 7.

The operation of this example circuit will be explained below.

During normal operation, selectors 6 and 9 both select the input (2) side. Therefore, the operation in this case is the same as that described in the previous embodiment circuit.

Assume now that the signal A and the signal B are in overlapping phase as shown in FIG. In this case, since the signal A and the signal B are periodic signals, the true phase difference at that time is near 0 or near the maximum value. Here, let M be the true count result value when the circuit counts without malfunction at the maximum phase difference.

Due to the phase approach of signals A and B, four counters 2 (1) ~
When one of 2 is disabled, the count output value from adder 3 is 3M/4, and when two are disabled, it is 2M/4, when three is M/4, and when four is 0. becomes. In this way, the circuit is N
If the counter is composed of 2 counters, there is a possibility that any of the counters 2(1) to 2■ may be stopped in the phase approach state, and therefore there is a possibility that the output from the adder 3 The total value is iM/N (where i is 1 to (N-1)).

Utilizing this property, when the total value of the adder 3 approaches these values, it can be inferred that there is a possibility that erroneous counting is occurring.

This judgment is made by the comparator 7. That is, the above-mentioned iM/N is set as a comparison setting value in the comparator 7, and when the output value of the adder 3 becomes close to these values,
A switching signal is output to selectors 6 and 9.

As a result, the selectors 6 and 9 are switched to select the input (2) side. Therefore, the signal A is delayed by a certain phase and is input to each of the JK flip-flops 7 (4(1) to 4). As a result, the lengths of the gate signals Q(1) to Q■ become shorter by the phase thereof.

As a result of shifting the phase of signal A in this way, if the output value of adder 3 becomes M- (the number of high-speed clocks corresponding to the delay phase), the current phase states of signals A and B are as described above. It can be determined that the output of the adder 3 before the shift is incorrect. In that case, the adder 8 adds the correction value C from the selector 9 to the total value of the adder 3 after shifting the phase of the signal A, and outputs this as the true count result value. Here, a value corresponding to the number of high-speed clocks CLKO corresponding to the phase shifted by the delay element 5 is selected as the correction value C.

On the other hand, as a result of the comparison by the comparator 7, even if the output value from the adder 3 is close to the comparison setting value, if it is the true count value during normal operation, the phase of the signal A is changed to the delay element 5. As a result of the delay, the total value output from adder 3 is (total value of addition a3 before shifting) - (count value for delay phase difference). In this case, comparator 7 This is determined, the selectors 6 and 9 are returned to the original input I side, the phase of the signal A is returned to the original, and the count result value is calculated.

In the embodiment circuit of FIG. 8, the phase of the signal A side is delayed when the phases of the signals A and B approach, but of course, the phase of the signal B may be delayed instead of the signal A. good. In this case, as a result of delaying signal B, adder 3
If the count value corresponding to the delayed phase difference is output from , it is determined that the phase state shown in FIG.
(output value) + (count value for the shifted phase), it is determined that normal operation is occurring.

Yet another embodiment of the invention is shown in FIG.

This embodiment circuit uses a hardware circuit to determine whether the phases of signals A and B approach each other in the embodiment circuit shown in FIG. ) 10 by software processing. In this embodiment, the sum value from adder 3 is input to microprocessor 10, where signal A
Processing such as determining the appropriateness of the phases of and B, adding the correction value C to the total value of the adder 3, and issuing a switching command to the selector 6 are performed by software.

In all of the embodiment circuits described above, N systems of divided clocks from an N frequency divider are counted by separate counters, but in this case, N counters are required.
Further, an adder is required to add up the count values of these counters, and therefore, as the number of N increases, the hardware scale becomes extremely large.

Still another embodiment of the present invention that solves such problems is the first embodiment.
As shown in Figure 0. In FIG. 10, divider 1 to 4
Among the frequency-divided clocks CLKI-CLK4 of the system, the frequency-divided clock CLK 4 is guided to the vertically connected circuit of counters 11 and 12, and the remaining frequency-divided clocks CLK 1 to CLK3 are fed to two-frequency dividers 13 (1) to 13, respectively. ■It leads to.

These counters 11 and 12.2 frequency dividers 13(1) to 13
The output of (1) is outputted via the launch circuit 14, and the divided signals (1) to (2) of the frequency dividers 13 (1) to 13 (2) and the counter 1
The lowest pin LSB of the count value of 1 (this is equal to the 2 frequency divider number ■ of the frequency divided clock CLK4) is guided to the exclusive OR circuit 15■.
The output signal (2) is the first bit (lowest pinpoint LSB) of the count result value. Also, the lowest bin of the 2 frequency divider 13■ and the counter 11! -LSB means exclusive OR circuit 15
As a result of (2), the output signal of the exclusive OR circuit 15 (2) is taken as the second bit of the count result value. Further, the count values of the counters 11 and 12 are set to the third to eighth bits of the count result value.

Generally speaking, how to select the toughness of the exclusive OR circuits 15■ and 15■ is to select the number N by which the high-speed clock HCLK is divided so that the number N by which the high-speed clock HCLK is divided is set to a value N = 2, where i is the exponent. For example, the exclusive OR circuit 15■ for obtaining the 1st bit of the count output value of the digital counter is 2XS" (L, S-1 to S'-"
) is selected as the input.

Here, for focusing where k>i, the output of the 2' column may be used.

For example, in the case of FIG. 10 described above, the exclusive OR circuit 15■ takes the exclusive OR of the frequency divided signals (1) to ■, and the exclusive OR circuit 15■ calculates the exclusive OR of the frequency divided signals (1) to ■. The exclusive OR of is taken.

A time chart of signals of each part of this embodiment circuit is shown in FIG. Here, the clock CLK is set by the gate signal.
The timing is set so that the count starts from 1.

As can be seen from FIG. 11, counters 11 and 12
As the bits lower than the third bit of the count result value generated by
The second bit (LSB) is obtained by taking the exclusive OR of the frequency-divided signals (1) to (■) using the exclusive OR circuit 15■. I can do it.

In this way, choose N so that the makku multiplication value N=21,
The bits higher than the power exponent i in the count output value can be obtained from the output of a counter that counts one of the frequency-divided signals, and the bits below the power index i can be obtained from the exclusive OR of the frequency-divided signals. By reducing the number of counters and adders, the hardware scale and power consumption can be reduced.

The embodiment shown in FIG. 10 is for the case of N-22, but the embodiment circuit in the case where the power index i is 1 (N=21=2) is shown in FIG. If (N=2
3=8) are shown in FIG. 13, respectively.

As shown in the figure, in the former case, the output signal of the frequency divider 13 and the L of the counter 11 are input to the exclusive OR 15, which outputs the first bin (LSB) of the count result value.
SB is selected.

In the latter case, the output signals of the frequency dividers 13 (1) to 13 (1) and the LSB of the counter 11 are input to the exclusive OR circuit 15 (15) which outputs the first bit of the count result value.
is selected and the exclusive OR circuit 15 outputs the second pinpoint.
The output signals of the frequency dividers 13■, 13■, 13■ and the LSB of the counter 11 are selected as the inputs of the frequency divider 13■, and the LSB of the counter 11 is selected as the input of the The LSB of 13■ and Kanuta 11 is selected.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a high-speed digital counter that can count without malfunctioning even with a high-speed clock.

Furthermore, by adopting the configuration as shown in FIG. 8 or 9, when measuring the phase difference between signals A and B, malfunctions can be prevented even when signals A and B approach each other.

In addition, by configuring the configuration as shown in FIG. 10, FIG. 12, or FIG. 13, the hardware scale can be reduced.
The device can be made smaller and consume less power.

[Brief explanation of drawings]

1, 2, and 3 are diagrams each explaining the principle of the present invention, FIG. 4 is a block diagram showing a high-speed digital counter as an embodiment of the present invention, and FIG. 5 is the embodiment shown in FIG. 6 is a block diagram showing another embodiment of the present invention; FIG. 7 is a time chart of signals of each part for explaining the problems of the circuit of the embodiment shown in FIG. 8; The figure is a block diagram showing still another embodiment of the present invention that is an improvement on the circuit of the embodiment shown in FIG. 6, and FIG. 9 shows still another embodiment of the present invention having the same function as the circuit of the embodiment shown in FIG. 8. 10 is a block diagram showing still another embodiment of the present invention that aims to reduce the hardware scale; FIG. 11 is a time chart of signals of each part of the circuit of the embodiment shown in FIG. 10; , and FIG. 13 are block diagrams showing still other embodiments of the present invention, each of which aims to reduce the hardware scale. In the figure, 1-frequency divider 2(1) to 2■, 11.12--counter 3.8--
- Adder 4.4 (1) ~ 4 ■ - JK flip-flop 5 - Delay element 6.9... Selector 7 - Comparator 10 - Microprocessor 13 (1) ~ 13 ■ -2 Frequency divider 14 - latch circuit

Claims (1)

[Claims] 1. A frequency divider [31] that divides an input clock by N and outputs N series of divided signals whose phase is shifted by one clock, and N series of the frequency divider [31]. N counters [32(1) to 32(n)] that respectively count the frequency-divided signals of 33] A high-speed digital counter comprising: 2. A high-speed digital counter that measures the phase difference between two signals [A, B] using an input clock, which divides the input clock by N and outputs N series of divided signals whose phase is shifted by one clock. N counters [32(1) to 32(n)] that count the N series of divided signals of the frequency divider [31], respectively, and the positions of the two signals. a gate generation circuit [34] that generates a gate signal that enables the N counters [32(1) to 32(n)] over a period of phase difference; and the N counters [32(1) to 32]. (n)], a phase shift circuit [35] that shifts the relative phase of the two signals [A, B], and a total value of the adder [33]. a comparison circuit [36] that compares the total value with a predetermined set value and controls the phase shift circuit [35] to shift the phase of at least one of the two signals when the total value is close to the set value; a correction circuit [3] that corrects the total value from the adder [33] by the phase shifted by the phase shift circuit [35];
7] A high-speed digital counter comprising: 3. Frequency divider that divides the input clock by N (N is an integer and is a power of 2 with 1 as the exponent) and outputs N series of frequency divided signals whose phase is shifted by 1 clock [30 ]; a counter [38] that counts one series of the frequency-divided signals of the frequency divider [30] and generates bits higher than the power exponent 1 in the count result value; and the frequency divider [30]. A high-speed digital counter comprising an exclusive OR circuit [39] that generates bits less than or equal to the exponent in the count output value by exclusive OR of N series of frequency-divided signals.