JP2014099238A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a counter circuit capable of rightly counting a high frequency signal in which hazard or the like may easily occur.SOLUTION: A counter circuit comprises: a frequency divider circuit 100 for generating frequency-divided clocks LCLKE and LCLKO, of which phases are different from each other, on the basis of a clock signal LCLK; a first counter 210 for counting the frequency-divided clock LCLKE; a second counter 220 for taking in a count value of the first counter 210 synchronously to the frequency-divided clock LCLKO; and a selector circuit 230 for exclusively selecting count values of the first and second counters 210 and 220. Relationship between the count values of the first and second counters 210 and 220 is kept constant at all the time, so that even if hazard occurs, only the count values are jumped and the count values do not become unstable.

Description

  The present invention relates to a counter circuit, and more particularly to a counter circuit suitable for counting clock signals that are likely to cause hazards. The present invention also relates to a latency counter, and more particularly to a latency counter that counts the latency of internal commands in a synchronous memory. Furthermore, the present invention relates to a semiconductor memory device including such a latency counter and a data processing system including such a semiconductor memory device.

  A synchronous memory represented by a synchronous dynamic random access memory (DRAM) is widely used as a main memory of a personal computer. Since the synchronous memory inputs and outputs data in synchronization with the clock signal supplied from the controller, it is possible to increase the data transfer rate by using a faster clock.

  However, even in a synchronous DRAM, the DRAM core is only an analog operation, and it is necessary to amplify a very weak charge by a sense operation. For this reason, the time from when the read command is issued until the first data is output cannot be shortened. After a predetermined delay time has elapsed since the read command was issued, the time is first synchronized with the external clock. Is output.

  This delay time is generally called “CAS latency” and is set to an integral multiple of the clock period. For example, if the CAS latency is 5 (CL = 5), after the read command is taken in synchronization with the external clock, the first data is outputted in synchronization with the external clock after 5 cycles. That is, the first data is output after 5 clocks. Such a counter that counts the latency is called a “latency counter”.

  As a latency counter, a circuit described in Patent Document 1 proposed by the present inventor is known. The latency counter described in Patent Document 1 includes a ripple counter that outputs a count value in a binary format and a point shift type FIFO circuit, and an input gate and an output of the point shift type FIFO circuit according to the count value of the ripple counter Control the gate. Here, the ripple counter is used as the counter circuit in consideration of the fact that a hazard is likely to occur in the clock signal to be counted.

  That is, a DLL (Delay Locked Loop) circuit is used in a general DRAM, and data input / output is performed in synchronization with an output clock generated by the DLL circuit. The DLL circuit always operates in the normal mode. However, when entering the power down mode or the like, the DLL circuit stops operating to reduce power consumption. For this reason, when returning from the power-down mode to the normal mode, the output clock may be temporarily unstable and a hazard may be output.

  When a hazard occurs in the output clock, for example, when a ring counter in which a shift register is circularly connected is used, the count value may become indefinite. In other words, in the ring counter, it is necessary that one register is latched in the active level, but the active level is latched in two or more registers due to a hazard, or the active level is not latched in any register. A condition may occur. When the ring counter enters such a state, the count value becomes indefinite and the latency counter becomes inoperable.

  Such a problem can be solved by using a ripple counter that performs a count operation in a binary format. That is, in the ripple counter, since there is no state where the count value is indefinite, even if the count value jumps illegally due to a hazard, the count value can be used as it is. For this reason, the latency counter of Patent Document 1 uses a ripple counter as a counter circuit.

  In addition, as a document related to the latency counter, a circuit described in Patent Document 2 is known.

JP 2008-47267 A JP 2007-115351 A

  As described above, using a ripple counter as a counter circuit used for a latency counter is extremely effective as a countermeasure against hazards. However, since the change in the count value of the ripple counter is delayed as the upper bits, if the frequency of the clock signal is very high, the count value may not be output in time for the operation of the FIFO circuit.

  Such a problem occurs not only in a counter circuit for a latency counter but also in a counter circuit that needs to count high-frequency signals that are likely to cause hazards.

  Accordingly, an object of the present invention is to provide a counter circuit capable of correctly counting high-frequency signals that are likely to cause hazards and the like.

  Another object of the present invention is to provide an improved counter circuit suitable for use in a latency counter and a latency counter including the same.

  Still another object of the present invention is to provide a semiconductor memory device including the above-described latency counter, and a data processing system using such a semiconductor memory device.

  A counter circuit according to the present invention counts a first frequency-divided clock and a frequency-dividing circuit that generates a plurality of frequency-divided clocks composed of at least first and second frequency-divided clocks having different phases based on a clock signal. A first counter that performs synchronization, a second counter that captures the count value of the first counter in synchronization with the second frequency-divided clock, and a selection that exclusively selects the count values of the first and second counters And a circuit.

  The type of the first counter is not particularly limited, but it is preferable to use a counter that outputs a count value in a binary format, for example, a ripple counter. When a ripple counter is used, there is a problem that when the increment or decrement is performed, the higher bit is delayed in the change. However, in the present invention, the count operation is performed based on the divided clock obtained by dividing the clock signal, not the clock signal itself. Therefore, it is possible to sufficiently absorb the delay of the upper bits.

  In addition, since the second counter generates the count value by taking in the count value of the first counter, the relationship between the count value of the first counter and the count value of the second counter is always constant. To be kept. That is, even if the count value of the first counter jumps due to a hazard or the like, the count value of the second counter also jumps in conjunction with this. For this reason, it is possible to always output a correct count value by exclusively selecting the count values of the first and second counters by the selection circuit.

  A latency counter according to the present invention is a latency counter that counts the latency of an internal command in synchronization with a clock signal, and includes the counter circuit described above and a point shift type FIFO circuit including a plurality of latch circuits. The shift-type FIFO circuit captures an internal command in one of the plurality of latch circuits based on the count value of the counter circuit, and captures the internal command in one of the plurality of latch circuits based on the count value of the counter circuit. It is characterized by outputting a command.

  According to this, even when the frequency of the clock signal is high and a hazard or the like is likely to occur, the latency of the internal command can be correctly counted.

  The point shift type FIFO circuit included in the latency counter according to the present invention includes an input selection circuit that supplies an internal command to any one of a plurality of signal paths based on a count value of the counter circuit, and a plurality of predetermined number of A shift circuit that supplies an internal command to a predetermined latch circuit based on the correspondence relationship between the signal path and the plurality of latch circuits, and an internal that is captured in one of the plurality of latch circuits based on the count value of the counter circuit It is preferable to provide an output selection circuit for outputting a command.

  According to this, since the shift circuit only needs to operate when an internal command is issued, power consumption can be reduced compared to when the shift circuit is operated regardless of whether or not an internal command is issued. It becomes possible.

  A point shift FIFO circuit included in a latency counter according to the present invention includes a first wired OR circuit that combines outputs of a plurality of latch circuits belonging to a first group among a plurality of latch circuits, and a plurality of latch circuits. Among them, the second wired-or circuit that combines the outputs of the plurality of latch circuits belonging to the second group, the gate circuit that combines the outputs of at least the first and second wired-or circuits, and the count value of the counter circuit Based on this, it is preferable to include first and second reset circuits for resetting the first and second wired OR circuits, respectively.

  According to this, the output load is reduced as compared with the case where all the outputs of the plurality of latch circuits included in the point shift type FIFO circuit are wired OR connected. For this reason, it is possible to ensure high signal quality.

  The latency counter according to the present invention supplies an internal command to the point shift type FIFO circuit relatively quickly when in the first operation mode, and sends the internal command to the point shift type FIFO when in the second operation mode. It is preferable to further include a mode switching circuit that supplies the circuit relatively slowly.

  According to this, for example, when the DLL circuit is not operating, by setting the second operation mode, it is possible to secure a sufficient margin for fetching internal commands.

  A semiconductor memory device according to the present invention includes the above-described latency counter. Furthermore, a data processing system according to the present invention is characterized in that the semiconductor memory device and the data processor described above are connected to each other by a system bus.

  As described above, according to the present invention, the count operation is performed based on the divided clock obtained by dividing the internal clock itself, not the internal clock itself. Therefore, even when the clock frequency is high, the operation margin is sufficient. Can be secured.

  In addition, since the second counter generates the count value by taking in the count value of the first counter, the relationship between the count value of the first counter and the count value of the second counter is always constant. To be kept. For this reason, even when the count value of the first counter jumps, it is possible to always output a correct count value.

  Therefore, when the counter circuit according to the present invention is used for the latency counter, the latency of the internal command can be correctly counted even when the frequency of the clock signal is high and a hazard or the like is likely to occur.

1 is a block diagram showing an overall configuration of a semiconductor memory device 10 according to a preferred embodiment of the present invention. FIG. 6 is a circuit diagram of a latency counter 55 according to a preferred embodiment of the present invention. 4 is a timing chart for explaining the operation of the frequency dividing circuit 100. FIG. 5 is a timing chart for explaining the operation of the counter circuit 200. FIG. 3 is a circuit diagram of a shift circuit 320. FIG. 3 is a schematic diagram for explaining the function of a shift circuit 320. FIG. FIG. 6 is a circuit diagram of a latch circuit 330-0 and an output gate 340-0. FIG. 6 is a timing chart for explaining the operation of the latency counter 55, showing the operation in the DLL on mode. FIG. 6 is a timing chart for explaining the operation of the latency counter 55, showing the operation in the DLL off mode. 1 is a block diagram illustrating a configuration of a data processing system 500 according to a preferred embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device 10 according to a preferred embodiment of the present invention.

  The semiconductor memory device 10 according to the present embodiment is a synchronous DRAM, and as external terminals, clock terminals 11a and 11b, command terminals 12a to 12e, address terminals 13, data input / output terminals 14, data strobe terminals 15a and 15b, and power supply terminals. 16a and 16b are provided.

  The clock terminals 11 a and 11 b are terminals to which clock signals CK and / CK are respectively supplied. The supplied clock signals CK and / CK are supplied to the clock input circuit 21. In this specification, a signal having “/” at the beginning of a signal name means an inverted signal of the corresponding signal. Therefore, the clock signals CK and / CK are complementary signals. The output of the clock input circuit 21 is supplied to the timing generation circuit 22 and the DLL circuit 23. The timing generation circuit 22 plays a role of generating an internal clock ICLK and supplying it to various internal circuits excluding data output circuits. The DLL circuit 23 generates an output clock LCLK and supplies it to a data output circuit.

  The output clock LCLK generated by the DLL circuit 23 is a signal whose phase is controlled with respect to the clock signals CK and / CK, and the phase of the read data DQ (and the data strobe signals DQS and / QDS) is the clock signals CK, / CK. The phase is slightly advanced with respect to the clock signals CK and / CK so as to coincide with the phase of CK.

  Whether or not the DLL circuit 23 can be used is selected according to the contents set in the mode register 56. That is, when the “DLL on mode” is set in the mode register 56, the DLL circuit 23 is in use, and the output clock LCLK is phase-controlled with respect to the clock signals CK and / CK. On the other hand, when the “DLL OFF mode” is set in the mode register 56, the DLL circuit 23 is not used, and the phase of the output clock LCLK is not controlled with respect to the clock signals CK and / CK. Therefore, in the DLL off mode, the output clock LCLK is a signal delayed in phase from the clock signal CK. Control of the DLL circuit 23 by the mode register 56 is performed by a mode signal M.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals are supplied to the command input circuit 31. These command signals supplied to the command input circuit 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals in synchronization with the internal clock ICLK. The generated internal command is supplied to the row control circuit 51, the column control circuit 52, the read control circuit 53, the write control circuit 54, the latency counter 55, and the mode register 56. Of the various internal commands ICMD, the read command MDRDT is supplied to at least the latency counter 55.

  The latency counter 55 is a circuit that delays the read command MDRDT so that read data is output after a preset CAS latency has elapsed since the read command MDRDT was issued. Here, the read command MDRDT is a signal synchronized with the internal clock ICLK, while the output control signal DRC that is the output of the latency counter 55 needs to be synchronized with the output clock LCLK. Therefore, the latency counter 55 also plays a role of transferring the clock to be synchronized from the internal clock ICLK to the output clock LCLK. Details of the latency counter 55 will be described later.

  The address terminal 13 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the address input circuit 41. The output of the address input circuit 41 is supplied to the address latch circuit 42. The address latch circuit 42 is a circuit that latches the address signal ADD in synchronization with the internal clock ICLK. Of the address signal ADD latched by the address latch circuit 42, the row address is supplied to the row-related relief circuit 61, and the column address is supplied to the column-related relief circuit 62. The row address generated by the refresh counter 63 is also supplied to the row relief circuit 61. Further, when the entry is made in the mode register set, the address signal ADD is supplied to the mode register 56.

  The row-related relief circuit 61 is a circuit that, when a row address indicating a defective word line is supplied, rescues the row address by performing alternative access to a redundant word line instead of the original word line. . The operation of the row-related relief circuit 61 is controlled by the row-related control circuit 51, and its output is supplied to the row decoder 71. The row decoder 71 is a circuit that selects one of the word lines WL included in the memory cell array 70. As shown in FIG. 1, in the memory cell array 70, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections. Each bit line BL is connected to a corresponding sense amplifier 73.

  When a column address indicating a defective bit line is supplied, the column-related repair circuit 62 is a circuit that repairs the column address by performing alternative access to a redundant bit line instead of the original bit line. . The operation of the column system relief circuit 62 is controlled by the column system control circuit 52, and the output is supplied to the column decoder 72. The column decoder 72 is a circuit that selects any one of the sense amplifiers 73 included in the memory cell array 70.

  The sense amplifier 73 selected by the column decoder 72 is connected to the read amplifier 74 during the read operation, and is connected to the write amplifier 75 during the write operation. The operation of the read amplifier 74 is controlled by the read control circuit 53, and the operation of the write amplifier 75 is controlled by the write control circuit 54.

  The data input / output terminal 14 is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the data output circuit 81 and the data input circuit 82. The data output circuit 81 is connected to the read amplifier 74 via the FIFO circuit 83, whereby a plurality of prefetched read data DQ is burst output from the data input / output terminal 14. In addition, the data input circuit 82 is connected to the write amplifier 75 via the FIFO circuit 84, whereby a plurality of write data DQs burst-input from the data input / output terminal 14 are simultaneously written in the memory cell array 70.

  The data strobe terminals 15a and 15b are terminals for inputting / outputting data strobe signals DQS and / QDS, respectively, and are connected to the data strobe signal output circuit 85 and the data strobe signal input circuit 86.

  As shown in FIG. 1, the data output circuit 81 and the data strobe signal output circuit 85 are supplied with an output clock LCLK generated by the DLL circuit 23 and an output control signal DRC generated by the latency counter 55. The output control signal DRC is also supplied to the FIFO circuit 83.

  The power supply terminals 16 a and 16 b are terminals to which power supply potentials VDD and VSS are supplied, respectively, and are connected to the internal voltage generation circuit 90. The internal voltage generation circuit 90 is a circuit that generates various internal voltages.

  The above is the overall configuration of the semiconductor memory device 10 according to the present embodiment. Next, the latency counter 55 included in the semiconductor memory device 10 will be described.

  FIG. 2 is a circuit diagram of the latency counter 55 according to a preferred embodiment of the present invention.

  As shown in FIG. 2, the latency counter 55 according to the present embodiment performs a counting operation based on the frequency dividing circuit 100 that generates the divided clocks LCLKE and LCLKO based on the output clock LCLK, and the frequency divided clocks LCLKE and LCLKO. A counter circuit 200 is provided, and a point shift FIFO circuit 300 that counts the latency of the read command MDRDT using the count value of the counter circuit 200 is provided. However, in the present specification, the term “counter circuit” may include both the frequency dividing circuit 100 and the counter circuit 200.

  The output clock LCLK is a clock generated by the DLL circuit 23 shown in FIG. During self refresh or power down, the operation of the DLL circuit 23 is stopped to reduce power consumption. Therefore, when returning from the self-refresh mode or the power-down mode, the operation of the DLL circuit 23 resumes. At this time, the output clock LCLK may be temporarily unstable and a hazard may be output.

  Such a hazard generally causes the latency counter to malfunction. However, in the latency counter 55 according to the present embodiment, even if a hazard occurs in the output clock LCLK, the count value only jumps, and the count value does not become unstable and the count operation does not stop.

  Hereinafter, the configuration and operation of each circuit block constituting the latency counter 55 will be described.

  First, the frequency dividing circuit 100 will be described.

  As shown in FIG. 2, the frequency divider circuit 100 receives a latch circuit 101 that performs a latch operation in synchronization with the falling edge of the output clock LCLK, and a frequency division signal LQ output from the output terminal Q of the latch circuit 101. Inverter 102 that is inverted and supplied to input terminal D, AND circuit 103 that takes the logical product of output clock LCLK and frequency-divided signal LQ, and AND that takes the logical product of output clock LCLK and the inverted signal of frequency-divided signal LQ Circuit 104.

  With such a circuit configuration, as shown in FIG. 3, the divided clock LCLKE that is the output of the AND circuit 103 has a waveform that is linked to the even-numbered internal clock LCLK, and the divided clock LCLKO that is the output of the AND circuit 104. Is a waveform linked to the odd-numbered internal clock LCLK. Therefore, the divided clocks LCLKE and LCLKO have an active period (high level period) of 0.5 tCK and an inactive period (low level period) of 1.5 tCK.

  As described above, the frequency dividing circuit according to the present embodiment generates two frequency-divided clocks LCLKE and LCLKO having different phases by dividing the output clock LCLK by two. The generated divided clocks LCLKE and LCLKO are supplied to the counter circuit 200 as shown in FIG. For this reason, the counter circuit 200 operates at half the frequency of the output clock LCLK.

  Next, the counter circuit 200 will be described.

  As shown in FIG. 2, the counter circuit 200 includes a first counter 210 that counts the divided clock LCLKE, and a second counter 220 that captures the count value of the first counter 210 in synchronization with the divided clock LCLKO. And a selection circuit 230 that exclusively selects the count values of the first and second counters 210 and 220.

  As shown in FIG. 2, the first counter 210 includes a 2-bit ripple counter in which ripple flip-flops 211 and 212 are cascade-connected, and a decoder 213 that decodes the output of the ripple counter. The frequency-divided clock LCLKE is supplied to the clock end of the flip-flop 211. Therefore, the output bit B1 of the flip-flop 211 indicates the least significant bit of the binary signal. The output bit B2 of the flip-flop 212 is the most significant bit of the binary signal.

  The output bits B1 and B2 of these flip-flops 211 and 212 are supplied to the decoder 213. However, the change timings of the output bits B1 and B2 are not simultaneous but change from the lower bits. That is, the change of the upper bits is delayed. In this embodiment, the delay circuit 214 is used to eliminate such a difference in change timing. The delay circuit 214 has a delay amount corresponding to one flip-flop. As shown in FIG. 2, the delay circuit 214 is connected between the flip-flop 211 and the decoder 213. Therefore, the output bit B1 of the flip-flop 211 is input to the decoder 213 after being given a delay corresponding to one stage of the flip-flop.

As a result, the change timings of the bits B1 and B2 input to the decoder 213 substantially coincide. The decoder 213 activates any one of four (= 2 ² ) outputs to a high level based on the bits B1 and B2 which are in binary format.

  Although the output of the decoder 213 changes later than the divided clock LCLKE due to the presence of the flip-flops 211 and 212 and the delay circuit 214, in the present embodiment, the first counter 210 is a ripple counter of only 2 bits, Since the delay amount is very small, the skew between the output of the decoder 213 and the divided clock LCLKE hardly causes a problem.

  On the other hand, the second counter 220 includes data latch flip-flops 221 and 222 and a decoder 223 that decodes the outputs of the flip-flops 221 and 222. The frequency-divided clock LCLKO delayed by the delay circuit 224 is supplied to the clock ends of the flip-flops 221 and 222. The data input terminal D of the flip-flop 221 is supplied with the output bit B1 of the flip-flop 211, and the data input terminal D of the flip-flop 222 is supplied with the output bit B2 of the flip-flop 212. With this configuration, the second counter 220 can capture the count value of the first counter 210 in synchronization with the divided clock LCLKO. That is, when the divided clock LCLKO is activated, the count value of the second counter 220 matches the count value of the first counter 210.

  The output bits B3 and B4 of the flip-flops 221 and 222 are supplied to the decoder 223. Since the change timings of these output bits B3 and B4 are simultaneous, no delay circuit or the like is inserted in the signal path of the output bits B3 and B4. However, since the first counter 210 is a ripple-type counter as described above, when the generated output bits B1 and B2 change, a delay corresponding to two flip-flops occurs in total. In order to correctly latch the output bits B1 and B2 having such a delay, the second counter 220 is provided with a delay circuit 224. The delay circuit 224 has a delay amount corresponding to two stages of flip-flops. As shown in FIG. 2, the delay circuit 224 is inserted in the signal path of the divided clock LCLKO.

As a result, the change timing of the output bits B3 and B4 input to the decoder 223 substantially coincides with the change timing of the output bits B1 and B2. The decoder 223 activates any one of the four (= 2 ² ) outputs to a high level based on the bits B3 and B4 which are in binary format.

  The selection circuit 230 includes four AND circuits 230-0, 2, 4, 6 corresponding to the output of the first counter 210 and four AND circuits 230-1, 3, 3, corresponding to the output of the second counter 220. 5 and 7. The corresponding output bits of the first counter 210 are supplied to one input terminal of the AND circuits 230-0, 2, 4, 6 and the divided clock LCLKE is supplied to the other input terminal in common. . The corresponding output bits of the second counter 220 are supplied to one input terminal of each of the AND circuits 230-1, 3, 5, and 7, and the divided clock LCLKO is supplied to the other input terminal in common. Is done.

  With this configuration, the output of the first counter 210 and the output of the second counter 220 are alternately selected, and the selected count value is supplied to the point shift type FIFO circuit 300. The count value of the counter circuit 200 is used as the output gate control signals COT0 to COT7.

  FIG. 4 is a timing chart for explaining the operation of the counter circuit 200.

  As shown in FIG. 4, the output bits B1 and B2 that are the count values of the first counter 210 are incremented in synchronization with the divided clock LCLKE, and the output bits B3 and B4 that are the count values of the second counter 220 are obtained. Increments in synchronization with the divided clock LCLKO. However, these increment operations are not performed independently of each other, but the count value of the first counter 210 is taken in as the count value of the second counter 220, so that the count value of the second counter 220 is the first count value. It follows the count value of the counter 210. Therefore, when the count value of the first counter 210 jumps due to a hazard or the like, the count value of the second counter 220 also jumps to the same value. Thus, the count value of the first counter 210 and the count value of the second counter 220 are always incremented in a correlated state.

  The count value generated in this way is selected by the selection circuit 230. That is, the count value of the first counter 210 is selected during the period when the frequency-divided clock LCLKE is high level, and the count value of the second counter 220 is selected during the period when the frequency-divided clock LCLKO is high level. . As a result, the count value of the counter circuit 200 is incremented in synchronization with the output clock LCLK. That is, the output gate control signals COT0 to COT7 are activated in this order.

  When the count value of the first counter 210 jumps due to a hazard or the like, the activated output gate control signals COT0 to COT7 change unexpectedly. However, since the first and second counters 210 and 220 output count values in binary format, a plurality of output gate control signals COT0 to COT7 are activated simultaneously, or any of the output gate control signals COT0 to COT7 is activated. The count value jumps to the last. In addition, since a hazard occurs when returning from the power-down mode, the read command MDRDT is not stored in the point shift FIFO circuit 300 described later.

  Therefore, even when the count value jumps due to a hazard or the like, the counter circuit 200 can automatically recover and perform normal operation as it is. This is because when the point shift type FIFO circuit 300 starts operation, the count value itself of the counter circuit 200 is meaningless, and correct operation can be performed if the count value changes sequentially.

  Next, the point shift type FIFO circuit 300 will be described.

  As shown in FIG. 2, the point shift type FIFO circuit 300 includes an input selection circuit 310, a shift circuit 320, latch circuits 330-0 to 330-7, an output selection circuit 340, and a synthesis circuit 350. Yes.

  The input selection circuit 310 includes eight AND circuits 310-0 to 310-7. In the AND circuits 310-0 to 310-7, the read command MDRDT is commonly input to one input terminal, and the output gate control signals COT0 to COT7 delayed by the delay circuit 390 are input to the other input terminal. .

  Thus, when the read command MDRDT is activated, the read command MDRDT is supplied to any one of the signal paths 311-0 to 311-7 based on the count value of the counter circuit 200. For example, when the read command MDRDT is supplied at the timing when the output gate control signal COT0 is activated, the read command MDRDT is supplied only to the signal path 311-0, and the other signal paths 311-1 to 311- 7 is not supplied with the read command MDRDT. Here, the signal paths 311-0 to 311-7 are signal paths to which the output signals of the AND circuits 310-0 to 310-7 are respectively supplied.

  These signal paths 311-0 to 311-7 are connected to the input terminal of the shift circuit 320. The shift circuit 320 is a circuit that supplies a read command MDRDT to a predetermined latch circuit based on the correspondence between the predetermined signal paths 311-0 to 311-7 and the latch circuits 330-0 to 330-7. .

  FIG. 5 is a circuit diagram of the shift circuit 320.

  As shown in FIG. 5, the shift circuit 320 includes eight multiplexers 320-0 to 320-7. The multiplexers 320-0 to 320-7 are all connected to the signal paths 311-0 to 311-7, and when the read command MDRDT is supplied onto the predetermined signal paths 311-0 to 311-7. The input gate control signals CIT0 to CIT7, which are outputs, are activated to a high level.

  The multiplexers 320-0 to 320-7 all have different signal paths 311-0 to 311-7 to which the input gate control signals CIT0 to CIT7 are set to the high level when the read command MDRDT is supplied. The designation is performed by the latency setting signal CL.

  FIG. 6 is a schematic diagram for explaining the function of the shift circuit 320.

  The outer ring 311 shown in FIG. 6 shows signal paths 311-0 to 311-7, and the inner ring CIT shows input gate control signals CIT0 to CIT7. The outer ring 311 can be regarded as a logical product of the output gate control signals COT0 to COT7 and the read command MDRDT. This means that the signals and signal paths having the same scale on the rings 311 and CIT are the corresponding signals and signal paths.

  More specifically, FIG. 6A shows an example in which the difference between the signal paths 311-0 to 311-7 and the input gate control signals CIT0 to CIT7 is set to “0”. In this case, when the read command MDRDT is supplied to the signal path 311-0, the corresponding input gate control signal CIT0 becomes high level, and when the read command MDRDT is supplied to the signal path 311-2, this is handled. The input gate control signal CIT2 to be turned to the high level. That is, assuming that the signal path 311 -k (k = 0 to 7) and the input gate control signal CITj (j = 0 to 7) correspond to each other, the state is j = k.

  On the other hand, FIG. 6B shows an example in which the difference between the signal paths 311-0 to 311-7 and the input gate control signals CIT0 to CIT7 is set to “7”. This is an image obtained by rotating the inner ring CIT counterclockwise by 7 scales. In this case, when the read command MDRDT is supplied to the signal path 311-0, the corresponding input gate control signal CIT7 becomes high level, and when the read command MDRDT is supplied to the signal path 311-3, this is handled. The input gate control signal CIT2 to be turned to the high level. That is, j−k = 7 or −1.

  The difference can be set to any of 0 to 7, and in the set state, the correspondence between the signal path and the input gate control signal is fixed. As described above, the shift circuit 320 shifts the read command MDRDT on the signal paths 311-0 to 311-7 to generate the input gate control signals CIT0 to CIT7. Such a difference is determined based on the required CAS latency.

  As described above, in this embodiment, since the input selection circuit 310 is arranged in the preceding stage of the shift circuit 320, only one of the multiplexers 320-0 to 320-7 is activated when the read command MDRDT is activated. Works. For this reason, it becomes possible to reduce power consumption compared with the case where all multiplexers are operated regardless of whether the read command MDRDT is activated.

  Input gate control signals CIT0 to CIT7 generated by the shift circuit 320 are supplied to the latch circuits 330-0 to 330-7, respectively. Output gates 340-0 to 340-7 constituting the output selection circuit 340 are connected to the subsequent stage of the latch circuits 330-0 to 330-7, respectively.

  FIG. 7 is a circuit diagram of the latch circuit 330-0 and the output gate 340-0. The other latch circuits 330-1 to 330-7 and output gates 340-1 to 340-7 have the same circuit configuration as that shown in FIG.

  As shown in FIG. 7, the latch circuit 330-0 is set when the input gate control signal CIT0 changes from low level to high level, and is reset when the output gate control signal COT0 changes from high level to low level. A (set / reset type) latch circuit 331 is included. In the set state of the SR type latch circuit 331, the logic level “1” is latched, and the read command MDRDT is held. The SR latch circuit 331 is reset by the reset circuit 332. A reset signal RST can be input to the reset circuit 332. When the reset signal RST is activated, all the latch circuits 330-0 to 330-7 are forcibly reset.

  The output gate 340-0 outputs the logic level latched by the SR-type latch circuit 331 during the period when the output gate control signal COT0 is at the high level. During the period when the output gate control signal COT0 is at a low level, the output is in a high impedance state. The outputs of the output gates 340-0 to 340-7 are supplied to the synthesis circuit 350.

  As shown in FIG. 2, the synthesis circuit 350 includes a wired OR circuit 351 that synthesizes outputs from the output gates 340-0 to 340-3, and a wired OR that synthesizes the outputs from the output gates 340-4 to 340-7. A circuit 352 and an OR gate circuit 353 for synthesizing the outputs of the wired OR circuits 351 and 352 are included. The output of the OR gate circuit 353 is used as the output control signal DRC.

  As described above, in this embodiment, the outputs from the eight latch circuits 330-0 to 330-7 are grouped into two groups and wired or connected to each other, and the obtained wired or outputs are output by the logic gate circuit. It is further synthesized. With this configuration, the output load of the output gates 340-0 to 340-7 is reduced as compared with the case where the outputs from all the latch circuits 330-0 to 330-7 are collectively wired-or connected. For this reason, it is possible to improve the signal quality of the output control signal DRC.

  The synthesis circuit 350 includes reset circuits 354 and 355 that reset the wired OR circuits 351 and 352, respectively. The reset circuit 354 resets the wired OR circuit 351 in response to the output gate control signal COT4, and the reset circuit 355 resets the wired OR circuit 352 in response to the output gate control signal COT0. The reset circuits 354 and 355 are each composed of an N-channel MOS transistor, and output gate control signals COT4 and 0 are supplied to the gates, respectively. All the sources are connected to the ground potential (VSS). Therefore, when the output gate control signal COT4 is activated, the reset circuit 354 is turned on, and the wired OR circuit 351 is reset to a low level. Similarly, when the output gate control signal COT0 is activated, the reset circuit 355 is turned on, and the wired OR circuit 352 is reset to a low level.

  As described above, the output gate control signals COT0 to COT7 are sequentially activated in this order by the counter circuit 200. Therefore, the output gate control signal COT4 is activated immediately after the activation of the output gate control signals COT0 to COT3 is finished, and the output control signal DRC is not output from the wired OR circuit 351 for a while. . If the reset circuit 354 is turned on at such timing, a sufficient period is secured until the output gate control signals COT0 to COT3 are activated next time, so that the wired OR circuit 351 can be surely reset. It becomes possible. The same applies to the reset circuit 355. Also, latch circuits 351a and 352a are connected to the wired OR circuits 351 and 352, respectively. Thereby, the logic level of the period when all the corresponding output gates (340-0 to 340-3 or 340-4 to 340-7) are in the high impedance state is maintained.

  As shown in FIG. 2, the latency counter 55 according to the present embodiment further includes a mode switching circuit 400.

  The mode switching circuit 400 includes a delay circuit 401 that delays the read command MDRDT, and a multiplexer 402 that selects one of the non-delayed read command MDRDT and the delayed read command MDRDT based on the mode signal. Yes.

  The multiplexer 402 selects the read command MDRDT that has not been delayed in the operation mode (DLL on mode) in which the DLL circuit 23 is used. Thereby, the read command MDRDT is supplied to the point shift type FIFO circuit 300 at high speed. On the other hand, when the operation mode does not use the DLL circuit 23 (DLL off mode), the multiplexer 402 selects the read command MDRDT delayed by the delay circuit 401. As a result, the read command MDRDT is supplied to the point shift FIFO circuit 300 later than in the DLL on mode.

  The delay amount of the delay circuit 401 is preferably set to a delay amount corresponding to the delay of the output clock LCLK generated with respect to the external clock signal CK when the DLL circuit 23 is not operating. According to this, even when the output clock LCLK is delayed with respect to the clock signal CK due to the DLL off mode, it is possible to ensure the same operation margin as in the DLL on mode.

  The above is the configuration of the latency counter 55 according to the present embodiment. Next, the operation of the latency counter 55 according to the present embodiment will be described.

  FIG. 8 is a timing chart for explaining the operation of the latency counter 55 according to the present embodiment, and shows the operation in the DLL on mode (latency = 7). As described above, in the DLL on mode, the read command MDRDT is supplied to the point shift FIFO circuit 300 at high speed.

  FIG. 8 shows an example in which the read command RD is issued in synchronization with the edge 0 of the external clock signal CK. As shown in FIG. 8, it takes a predetermined time from when the read command RD is issued until the internal read command MDRDT is generated. The read command MDRDT is held in any of the eight latch circuits 330-0 to 330-7 included in the point shift type FIFO circuit 300 based on the output of the counter circuit 200. This example shows a state in which the AND gate 310-7 is selected by the output of the delay circuit 390 at the timing when the read command MDRDT is generated. Accordingly, only the input gate control signal CIT7 among the input gate control signals CIT0 to CIT7 is activated, and the read command MDRDT is stored in the latch circuit 330-7.

  The read command MDRDT stored in the latch circuit 330-7 is held in the latch circuit 330-7 until the output gate control signal COT7 is selected by the increment of the counter circuit 200. When the output gate control signal COT7 is selected, the output gate 340-7 is opened and the output control signal DRC is activated. The output control signal DRC is synchronized with the output clock LCLK, and the read data DQ is actually output using this.

  Thereafter, when the self-refresh mode or the power-down mode is entered, the DLL circuit 23 shown in FIG. 1 stops. When returning to normal operation, a hazard may occur in the output clock LCLK, which may cause the count value of the counter circuit 200 to jump.

  However, in the latency counter 55 according to the present embodiment, the count value itself is meaningless, and no problem occurs if it is correctly incremented (or decremented) during normal operation. That is, the count value itself does not cause an error, and the next operation can be executed as it is even if the count value changes due to a hazard. As described above, according to the latency counter 55 according to the present embodiment, it is possible to prevent an error due to the hazard of the output clock LCLK.

  FIG. 9 is a timing chart for explaining the operation of the latency counter 55 according to the present embodiment, and shows the operation in the DLL off mode (latency = 6). As described above, in the DLL off mode, the read command MDRDT is delayed and supplied to the point shift type FIFO circuit 300.

  As shown in FIG. 9, in the DLL off mode, since the output clock LCLK is not phase-controlled with respect to the external clock signal CK, a predetermined delay occurs with respect to the clock signal CK. Such a delay is offset by delaying the supply of the read command MDRDT by the delay circuit 401. As a result, the same operation margin as in the DLL on mode can be secured.

  As described above, according to the latency counter 55 according to the present embodiment, since the count operation is performed in synchronization with the divided clocks LCLKE and LCLKO obtained by dividing the output clock LCLK by 2, the output clock LCLK Even when the frequency is high, a sufficient operation margin of the counter circuit 200 can be secured.

  Since the counter circuit 200 is divided into the first counter 210 and the second counter 220, the number of bits of the ripple counter included in the first counter 210 is reduced. As a result, the delay generated in the ripple counter is reduced, and as a result, the frequency-divided clocks LCLKE and LCLKO can be directly supplied to the selection circuit 230. That is, when the delay of the ripple counter is large, it is necessary to input the divided clocks LCLKE and LCLKO to the selection circuit 230 after delaying them to some extent in order to achieve proper synchronization. In this case, it is necessary to resynchronize the read command MDRDT with the output clock LCLK by providing a resynchronization circuit for recovering the delay. Such a resynchronization circuit can cause a reduction in command transfer margin when the clock frequency is high. However, in the present embodiment, such a resynchronization circuit is unnecessary, and as a result, a sufficient transfer margin can be ensured even when the clock frequency is high.

  In addition, the first counter 210 counts the divided clock LCLKE in a binary format, while the second counter 220 captures the count value of the first counter 210 in synchronization with the divided clock LCLKO. The count value of the first counter 210 and the count value of the second counter 220 do not deviate. Therefore, the read command MDRDT latched based on the count value of the first counter 210 can be output based on the count value of the second counter 220. Of course, the reverse is also possible. This means that the point-shift FIFO circuit 300 is not affected by the frequency division even though the count operation is performed in synchronization with the frequency-divided clocks LCLKE and LCLKO.

  That is, if the count value of the first counter 210 and the count value of the second counter 220 are irrelevant, the read command MDRDT latched based on the count value of the first counter 210 is the first counter 210. It is essential to output based on the count value. Similarly, the read command MDRDT latched based on the count value of the second counter 220 must be output based on the count value of the second counter 220. In this case, the number of latencies that can be set in the point shift type FIFO circuit 300 is only an even number, and in order to set the latency to an odd number, it is necessary to add a latency adding circuit or the like. However, in this embodiment, since the count value of the first counter 210 and the count value of the second counter 220 are linked, there is no such restriction, and a latency adding circuit or the like is added. Thus, the latency can be set to an arbitrary value.

  In addition, in the present embodiment, since the first counter 210 is a ripple counter, it is possible to prevent errors due to the hazard of the output clock LCLK as described above.

  In the present embodiment, the input selection circuit 310 is provided in the preceding stage of the shift circuit 320 so that the shift circuit 320 is operated only when the read command MDRDT is supplied. Regardless, the power consumption can be reduced compared to the case where the shift circuit is always operated.

  Further, in the present embodiment, the outputs of the output gates 340-0 to 340-7 are grouped into two groups, and wired or connected to each other, and the obtained wired or outputs are further synthesized by the logic gate circuit. For this reason, the output load is reduced as compared with the case where all the outputs are combined and wired or connected. As a result, the signal quality of the output control signal DRC can be improved.

  Furthermore, in this embodiment, by using the mode switching circuit 400, the supply of the read command MDRDT is delayed in the DLL off mode from that in the DLL on mode, so that the output clock LCLK is an external clock. Even when it is delayed with respect to the signal CK, it is possible to secure a sufficient margin for the read command MDRDT in the same manner as in the DLL on mode.

  FIG. 10 is a block diagram showing a configuration of a data processing system 500 using the semiconductor memory device 10 according to a preferred embodiment of the present invention.

  A data processing system 500 shown in FIG. 10 has a configuration in which a data processor 520 and the semiconductor memory device (DRAM) 10 according to the present embodiment are connected to each other via a system bus 510. Examples of the data processor 520 include, but are not limited to, a microprocessor (MPU), a digital signal processor (DSP), and the like. In FIG. 10, for simplicity, the data processor 520 and the DRAM 530 are connected via the system bus 510, but they may be connected via a local bus without passing through the system bus 510.

  In FIG. 10, only one set of system buses 510 is illustrated for simplicity, but may be provided serially or in parallel via a connector or the like as necessary. In the memory system data processing system shown in FIG. 10, the storage device 540, the I / O device 550, and the ROM 560 are connected to the system bus 510, but these are not necessarily essential components.

  Examples of the storage device 540 include a hard disk drive, an optical disk drive, and a flash memory. Examples of the I / O device 550 include a display device such as a liquid crystal display and an input device such as a keyboard and a mouse. Further, the I / O device 550 may be only one of the input device and the output device. Furthermore, although each component shown in FIG. 10 is drawn one by one for simplicity, the present invention is not limited to this, and a plurality of one or two or more components may be provided.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above embodiment, the output clock LCLK is divided by two using the frequency divider circuit 100, but the frequency division number is not limited to this in the present invention. Therefore, when the output clock LCLK is faster, the output clock LCLK is divided by 4 and, like the second counter 220, the third and fourth counters interlocked with the first counter 210 are set. Use it.

  In the above embodiment, the first counter 210 includes a ripple counter, but the present invention is not limited to this.

  Furthermore, in the above embodiment, the counter circuit 200 is used as a part of the latency counter 55, but the application of the counter circuit according to the present invention is not limited to this.

  Furthermore, in the present invention, the configuration of the point shift type FIFO circuit 300 is arbitrary, and is not limited to the configuration shown in the above embodiment. In the present invention, it is not essential to provide the mode switching circuit 400.

  Further, in the above embodiment, the output of the output gates 340-0 to 340-7 is received by the wired OR circuits 351 and 352 divided into two, but the number of divisions of the wired OR circuit is not limited to this. It may be divided into three or more, or may not be divided.

  In the above embodiment, the wired OR circuit 351 is reset in response to the output gate control signal COT4, and the wired OR circuit 352 is reset in response to the output gate control signal COT0. However, the wired OR circuits 351 and 352 are reset. The timing for resetting is not limited to this. Therefore, it is sufficient for the wired OR circuit 351 to be reset in response to the count value of the counter circuit 200 indicating the latch circuit corresponding to the wired OR circuit 352. Similarly, for the wired OR circuit 352, the counter It is only necessary to reset in response to the count value of the circuit 200 indicating the latch circuit corresponding to the wired OR circuit 351.

10 Semiconductor memory device (DRAM)
11a, 11b Clock terminals 12a-12e Command terminal 13 Address terminal 14 Data input / output terminals 15a, 15b Data strobe terminals 16a, 16b Power supply terminal 21 Clock input circuit 22 Timing generation circuit 23 DLL circuit 31 Command input circuit 32 Command decoder 41 Address input Circuit 42 Address latch circuit 51 Row system control circuit 52 Column system control circuit 53 Read control circuit 54 Write control circuit 55 Latency counter 56 Mode register 61 Row system repair circuit 62 Column system repair circuit 63 Refresh counter 70 Memory cell array 71 Row decoder 72 Column Decoder 73 Sense amplifier 74 Read amplifier 75 Write amplifier 81 Data output circuit 82 Data input circuit 83, 84 FIFO circuit 85 Data strobe signal output Circuit 86 Data strobe signal input circuit 90 Internal voltage generation circuit 100 Frequency dividing circuit 101 Latch circuit 102 Inverter 103, 104 AND circuit 200 Counter circuit 210 First counter 211, 212, 221, 222 Flip-flops 213, 223 Decoders 214, 224 Delay circuit 220 Second counter 230 Selection circuit 230-0 to 230-7 AND circuit 300 Point shift type FIFO circuit 310 Input selection circuit 310-0 to 310-7 AND circuit 311-1 to 311-7 Signal path 320 Shift circuit 320-0 to 320-7 Multiplexer 330-0 to 330-7 Latch circuit 331 SR type latch circuit 332 Reset circuit 340 Output selection circuit 340-0 to 340-7 Output gate 350 Synthesis circuit 351, 352 Wired A circuit 351a, 352a Latch circuit 353 Logic gate circuit 354, 355 Reset circuit 390 Delay circuit 400 Mode switching circuit 401 Delay circuit 402 Multiplexer 500 Data processing system 510 System bus 520 Data processor 540 Storage device 550 I / O device 560 ROM

Claims (1)

A first counter for counting a first clock signal;
A second counter that captures a count value of the first counter in synchronization with a second clock signal having a phase different from that of the first clock signal;
A first decoder that generates a first decode signal by decoding a count value of the first counter;
A second decoder for generating a second decoded signal by decoding a count value of the second counter;
And a selection circuit that is controlled based on one of the first and second decode signals.

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