JP4518377B2 - DLL circuit - Google Patents

Description

  The present invention relates to a DLL (Delay Locked Loop) circuit capable of delaying an input clock by exactly one period.

  As shown in FIG. 9, the conventional DLL circuit includes a variable delay circuit 1, a control circuit 2 composed of a logic circuit that controls the delay amount of the variable delay circuit 1, an input clock CLK 1, and feedback from the variable delay circuit 1. It comprises a phase comparator 3 that compares the phase of the clock CLK2 and outputs the comparison result to the control circuit 2 (see, for example, Patent Documents 1 and 2).

  In this DLL circuit, the delay amount of the variable delay circuit 1 is increased or decreased by the control circuit 2 in accordance with the result of phase comparison between the input clock CLK1 and the feedback clock CLK2, and the phases of both clocks CLK1 and CLK2 are aligned in the locked state. . If the delay amount of the variable delay circuit 1 is increased from the minimum state, when the delay amount becomes one cycle of the input clock CLK1, both clocks CLK1, CLK2 are obtained as shown in FIG. Are aligned, and the DLL circuit is locked.

Thus, when the phases are aligned and locked, the delay control signal S1 of the control circuit 2 that controls the variable delay circuit 1 shows a value for one period of the input clock CLK1. Therefore, by using another variable delay circuit having the same configuration as the variable delay circuit 1 and the control signal S1, a signal based on the delay amount for one cycle of the input clock CLK1 is generated in another circuit block. be able to. For example, a four-phase clock (0/90/180/270 degrees) can be generated by dividing a delay amount for one cycle into four and obtaining a delay amount for a quarter cycle.
Japanese Patent Laid-Open No. 10-285016 Japanese Patent Laid-Open No. 11-088153

  However, in the conventional DLL circuit, the case where the delay amount of the variable delay circuit 1 is for one cycle of the input clock CLK1 (FIG. 10 (a)) and the case of two cycles (FIG. 10 (b)) are distinguished. I can't. That is, lock in both cases. For this reason, when the delay amount of the variable delay circuit 1 is two cycles of the clock CLK1, the delay control signal S1 indicating the two cycles of the clock is output to the other circuit blocks described above, and the four-phase clock described above. In the case of generating the 4-phase clock, the 4-phase clock having the phase relationship of 0/180/360/540 degrees is erroneously output, which should be generated with the phase relationship of 0/90/180/270 degrees. To do. This is because the delay amount between 0-90 degrees should be a quarter cycle, but it is erroneously a delay amount of 2/4 cycles.

  Such a phenomenon is shown in FIG. 10C when the phase comparator 3 malfunctions due to large noise on the input clock CLK1 or when the frequency of the input clock CLK1 changes twice from a certain point. Happens when.

  An object of the present invention is to provide a DLL circuit that solves the above-described problem and can obtain a delay control signal for an accurate period of an input clock.

The invention according to claim 1, comprising a variable delay circuit control circuit and the phase comparator, the delay of the variable delay circuit by the control circuit detects a phase difference between two clock input to the phase comparator A DLL circuit for controlling the amount includes a tooth missing clock generating circuit for generating two tooth missing clocks having a phase difference corresponding to one cycle of the input clock from the input clock, the phase of the two tooth missing clocks being The advanced tooth missing clock is delayed by the variable delay circuit and then input to one input terminal of the phase comparator, the phase delayed tooth missing clock is input to the other input terminal of the phase comparator, and and DLL circuit control signal of the control circuit, characterized in that the delay amount in the variable delay circuit is in so that a locked state when indicating the first period delay of the input clock .
According to a second aspect of the present invention, the DLL circuit according to the first aspect further comprises selection means for selecting the two missing tooth clocks or the input clock output from the missing tooth clock generating circuit , the selecting means comprising: The input clock is delayed by the variable delay circuit in one selected state and then input to one input terminal of the phase comparator and directly input to the other input terminal of the phase comparator, and the other selected state Of the two missing tooth clocks, the delayed tooth missing clock having the advanced phase is delayed by the variable delay circuit and then input to one input terminal of the phase comparator, and the missing tooth missing clock having the phase delayed is selected. The DLL circuit is characterized in that it is inputted to the other input terminal of the phase comparator.
According to a third aspect of the present invention, in the DLL circuit according to the second aspect, the selection means is always in the one selected state, and switches to the other selected state when substantially in the locked state. The DLL circuit is characterized by the above .

According to the present invention, while the delays using two toothless clock having a phase difference generated from the input clock, a toothless clock advanced of the phase of the variable delay circuit of the phase comparator input to the input terminal, since the delayed toothless clock phase to the other input terminal, in the case where the variable delay circuit is locked at a delay of one cycle, when the two cycles without locking The delay amount for two cycles is not detected by mistake. Further, by making it possible to select the case of using the case with the original input clock using two toothless clock this, whether the delay is one cycle of accurately input clock Can be verified.

  In the present invention, frequency-divided clocks CLK3 and CLK4 generated by dividing the input clock CLK1 by 2 are generated, the frequency-divided clock CLK3 is input to the variable delay circuit 1, and the frequency-divided clock CLK4 is input to the phase comparator 3 at the same time. The clock CLK3 input to 1 is delayed there and input to the phase comparator 3 as the feedback clock CLK5. At this time, if the phase of the divided clock CLK3 is advanced by one cycle of the input clock CLK1 relative to the divided clock CLK4, the phase comparator 3 indicates that the delay amount of the variable delay circuit 1 is one cycle of the input clock CLK1. At this time, it is determined that the phases of the divided clock CLK4 and the feedback clock CLK5 are aligned, and the lock is applied. However, when the delay amount is 2 cycles, the phases are not aligned, that is, they are shifted by 180 degrees. to decide. FIG. 1 shows a timing chart of the operation in this case. FIG. 1A shows the case where the delay amount of the variable delay circuit 1 is one cycle of the input clock CLK1, and FIG. 1B shows the case of two cycles. In the example of FIG. 1, CLK3 and CLK4 are in an inverted relationship, and the lock is set when the waveforms of CLK5 and CLK4 are the same. It doesn't matter. From the above, the delay control signal S1 output from the control circuit 2 when the DLL circuit is locked always indicates one cycle.

  FIG. 2 is a block diagram of the DLL circuit according to the first embodiment of the present invention. The variable delay circuit 1 is formed by, for example, cascading a plurality of delay elements having the same delay amount, and the delay amount is determined by how many delay elements are used. The control circuit 2 is composed of a counter, for example, and determines the delay amount of the variable delay circuit 1 based on the count value. The phase comparator 3 is composed of a D flip-flop, for example, and outputs “1” when the feedback clock CLK5 is advanced in phase with respect to the divided clock CLK4 and outputs “0” when delayed, every time the divided clock CLK4 rises. Output. Accordingly, when the phase of the feedback clock CLK5 is advanced, the count value of the counter of the control circuit 2 is increased, the number of delay elements of the variable delay circuit 1 is increased, and the delay amount is increased. Reference numeral 4 denotes a D flip-flop (frequency divider), which divides the input clock CLK1 by two and inputs it to the phase comparator 3 and the variable delay circuit 1. The frequency-divided clock CLK3 input to the variable delay circuit 1 has an inverted relationship with the frequency-divided clock CLK4 input to the phase comparator 3, and apparently advances in phase by one period of the input clock CLK1.

  In this DLL circuit, when the clock CLK3 input to the variable delay circuit 1 is delayed by one cycle of the input clock CLK1 (1/2 cycle of the divided clock CLK3) to become the feedback clock CLK5, Although the phase is the same as that of the divided clock CLK4, when it is delayed by two periods (one period of the divided clock CLK3) and becomes the feedback clock CLK5, it has a phase difference of 180 degrees and the DLL circuit is locked. There is no.

  However, in the DLL circuit of the first embodiment, even when the delay amount of the variable delay circuit 1 is shifted by three cycles of the input clock CLK1, the locked state is entered and cannot be distinguished from the case of shifting by one cycle. Therefore, in the second embodiment, a divided clock obtained by dividing the input clock CLK1 by 4 is used.

  FIG. 3 is a block diagram of the DLL circuit according to the second embodiment. Here, two D flip-flops (frequency dividers) 5 and 6 divide the input clock CLK1 by 4 to generate frequency-divided clocks CLK6 and CLK7. Input to the phase comparator 3. Note that the phase of the divided clock CLK6 is advanced by one cycle of the input clock CLK1 relative to the divided clock CLK7.

  When the frequency-divided clocks CLK6 and CLK7 are used in this manner, as shown in the timing charts of FIGS. 4A to 4C, the variable delay circuit 1 is locked when the delay amount of the input clock CLK1 is one cycle. However, it is not locked when 2 cycles or 3 cycles. As described above, the frequency divider can increase the identifiable delay amount by increasing the value for dividing the input clock CLK1 as necessary.

  FIG. 5 is a block diagram of a DLL circuit according to the third embodiment of the present invention. Here, the input clock CLK1 and the divided clocks CLK3 and CLK4 obtained by dividing the input clock CLK1 are used, and the clocks are switched by the selectors (selection means) 7 and 8.

  Here, (1) in a normal operation, the DLL circuits are operated by controlling the selectors 7 and 8 so that the input clock CLK1 is used as it is. (2) When the phase difference between the clocks CLK1 and CLK2 is sufficiently small in the phase comparator 3 using the input clock CLK1, that is, when the phase is almost locked, the selectors 7 and 8 are switched, and the divided clock CLK3 , CLK4, if the delay amount of the variable delay circuit 1 is equal to two periods of the input clock CLK1, the phase comparator 3 detects it and the lock state is released.

  Therefore, if (1) → (2) → (1) is repeated at an appropriate timing such as in the almost locked state as described above, the current delay amount of the variable delay circuit 1 is equal to one cycle of the input clock CLK1 or 2 The period can be verified. Note that the same verification can be performed by using the quarter-frequency clocks CLK6 and CLK7 described in the second embodiment. In the case where only the frequency-divided clocks CLK3, CLK4 or CLK6, CLK7 described in the first and second embodiments are used, the number of comparisons of the phase comparator 3 is reduced by the divided frequency. Therefore, the decrease in the number of comparisons can be suppressed to some extent, which contributes to improvement in locking accuracy and reduction in time required for locking.

  FIG. 6 is a block diagram of a DLL circuit according to the fourth embodiment of the present invention. In this example, the input clock CLK1 is inputted, the two missing clocks CLK9 and CLK10 are generated by the missing clock generation circuit 9, and this and the input clock CLK1 are switched by the selectors 7 and 8. The tooth missing clock CLK9 is a clock advanced by one cycle of the input clock CLK1 with respect to the clock CLK10. In this DLL circuit, as shown in FIG. 7, the phase of the clock CLK10 and the clock CLK11 are the same when the delay amount of the variable delay circuit 1 is one cycle of the input clock CLK1, but two cycles, three cycles, four cycles. Does not match in minutes.

  As shown in FIG. 8, the tooth missing clock generation circuit 9 creates two quadrant clocks CLKa and CLKb whose phases are shifted by 90 degrees from the input clock CLK1, and takes the AND of the clock CLK1 and the clock CLKa. The clock CLK10 can be generated by taking the AND of the clock CLK1 and the clock CLKb.

  If the delay control signal S1 obtained by the DLL circuit of the present invention is used, the input clock CLK1 can be accurately obtained by using the same variable delay circuit as the variable delay circuit 1 in addition to generating the four-phase clock described above. It is also possible to generate a clock that is phase-shifted by a predetermined amount. Further, the implementation of the present invention is not limited to the above-described embodiments, and various modifications can be made.

5 is a timing chart of the operation of the DLL circuit for explaining the principle of the present invention. FIG. 2 is a block diagram of a DLL circuit according to the first embodiment that realizes the timing chart of FIG. 1. 6 is a block diagram of a DLL circuit according to Embodiment 2. FIG. 6 is a timing chart of the operation of the DLL circuit according to the second embodiment. FIG. 10 is a block diagram of a DLL circuit according to a third embodiment. FIG. 10 is a block diagram of a DLL circuit according to a fourth embodiment. 10 is a timing chart of the operation of the DLL circuit according to the fourth embodiment. 10 is a timing chart for explaining generation of a missing tooth clock according to a fourth embodiment. It is a block diagram of a conventional DLL circuit. It is a timing chart of operation of a conventional DLL circuit.

Explanation of symbols

1: Variable delay circuit 2: Control circuit 3: Phase comparator 4-6: D flip-flop (frequency divider)
7, 8: Selector (selection means)
9: Tooth drop clock generation circuit

Claims (3)

Comprising a variable delay circuit control circuit and the phase comparator, the DLL circuit controls the delay amount of said variable delay circuit by the control circuit detects a phase difference between two clock input to the phase comparator,
A tooth missing clock generating circuit that generates two tooth missing clocks having a phase difference corresponding to one cycle of the input clock from the input clock, and the variable number of the tooth missing clocks having advanced phases among the two tooth missing clocks is provided. Delayed by a delay circuit and then input to one input terminal of the phase comparator, a delayed tooth missing clock is input to the other input terminal of the phase comparator, and the control signal of the control circuit is variable. DLL circuit, wherein the delay amount in the delay circuit is a so that a locked state when referring to one period of the delay of the input clock. The DLL circuit according to claim 1,
Selecting means for selecting the two missing tooth clocks or the input clock output from the missing tooth clock generation circuit ;
The selection means delays the input clock in one selected state by the variable delay circuit and then inputs it to one input terminal of the phase comparator and directly inputs it to the other input terminal of the phase comparator, the causes input delayed of the phase to one input terminal of the phase comparator the two toothless the phase of advanced toothless clock of the clock from delaying by the variable delay circuit on the other selected A DLL circuit, wherein a tooth missing clock is input to the other input terminal of the phase comparator. The DLL circuit according to claim 2,
The DLL circuit according to claim 1, wherein the selection means is normally in the one selected state and is switched to the other selected state when almost in the locked state.

Images