JP3562321B2 - Clock signal switching device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock signal switching device for selectively outputting a clock signal and one of a 1/2 frequency-divided clock signal obtained by dividing the clock signal by 1/2 based on a logic state of a selection signal. It is.
[0002]
[Prior art]
As the clock signal switching device, a device that selectively outputs either the original clock signal or a 1/2 frequency-divided clock signal obtained by dividing the original clock signal by 1/2 based on the logic state of the selection signal. Are known.
[0003]
FIG. 3 is a block diagram of a conventional clock signal switching device. FIG. 4 is a timing chart showing the basic operation of the clock signal switching device 100. The clock signal switching device 100 includes a D-type flip-flop 110 and a selector 120. The selector 120 includes two AND circuits 121 and 122 and an OR circuit 123 to which output signals T10 and T11 of the AND circuits 121 and 122 are input.
[0004]
The original clock signal CLK input from the outside is input to the clock input terminal CK of the D-type flip-flop 110 and is divided by １ ／ in the D-type flip-flop 110. That is, the non-inverting output terminal Q of the D-type flip-flop 110 outputs a 1/2 frequency-divided clock signal CLK (1/2) obtained by dividing the original clock signal CLK by 1/2.
[0005]
In the selector 120, the original clock signal CLK and the selection signal SEL are calculated by the AND circuit 122. In the selector 120, the AND circuit 121 calculates an inverted signal of the 周 frequency-divided clock signal CLK (1/2) output from the D-type flip-flop 110 and the selection signal SEL. Output signals T10 and T11 of the AND circuits 121 and 122 are calculated by the OR circuit 123 and output as an output signal OUT. Here, when the logic state of the selection signal SEL is held at a high level, the original clock signal CLK is output as the output signal T11 of the AND circuit 122. On the other hand, the 1/2 frequency-divided clock signal CLK (1/2) input to the AND circuit 121 is not output as the output signal T10. Therefore, the original clock signal CLK is output from the OR circuit 123.
[0006]
On the other hand, when the logic state of the selection signal SEL switches to the low level state, the AND circuit 122 closes and the AND circuit 121 opens. Therefore, only the 1/2 frequency-divided clock signal CLK (1/2) output from the AND circuit 121 is output via the OR circuit 123.
[0007]
As described above, the clock signal switching device 100 selectively outputs one of the original clock signal CLK and the 1/2 frequency-divided clock signal CLK (1/2) based on the logic state of the selection signal SEL. .
[0008]
[Problems to be solved by the invention]
Here, switching of the selection signal SEL may not coincide with rising and falling of the original clock signal CLK. In this case, pulse-like noise, that is, a so-called hazard may be generated in the output clock signal.
[0009]
For example, as shown in FIG. 4, when the logic state of the selection signal SEL switches from a high level to a low level at a time point t100 before the original clock signal CLK that has risen at the time point t90 falls, at the timing of this switching. , The clock signal output from the OR circuit 123 is switched. With this switching, the logical state of the original clock signal CLK output from the OR circuit 123 is forcibly shifted from a high level to a low level. As a result, a hazard 130 occurs in the output signal OUT. The hazard 130 causes malfunction of the electronic device.
[0010]
In view of the above, an object of the present invention is to provide a clock signal switching device that switches and outputs a clock signal and a 1/2 frequency-divided clock signal of the clock signal based on the logical state of the selection signal. An object of the present invention is to propose a configuration capable of preventing occurrence of a hazard at the time of switching.
[0011]
[Means for Solving the Problems]
In order to solve the above problem, the present invention selectively selects a clock signal and one of a 1/2 frequency-divided clock signal obtained by dividing the clock signal by 1/2 based on the logic state of a selection signal. The following configuration is adopted in the clock signal switching device to output.
[0012]
A frequency dividing circuit for generating a first 1/2 frequency-divided clock signal by dividing the original clock signal by 1/2, and a synchronization circuit for synchronizing the inversion point of the logic level of the selection signal with the original clock signal Only when the output signal of the synchronizing circuit is in one of the logical states, based on the first 1/2 frequency-divided clock signal, the phase with the 1/2 frequency-divided clock signal is 90 degrees. A clock signal generation circuit for generating a shifted second 1/2 frequency-divided clock signal; and a logic circuit for outputting an exclusive OR of the first and second 1/2 frequency-divided clock signals as a clock signal. Configuration.
[0013]
In the clock signal switching device of the present invention, the phases of the first and second 1/2 frequency-divided clock signals are mutually shifted by 90 degrees. Therefore, when the second 1/2 frequency-divided clock signal is being output from the clock signal generation circuit, the clock signal output from the logic circuit has the same frequency as the original clock signal. On the other hand, when the second 1/2 frequency-divided clock signal is not output from the clock signal generation circuit, the clock signal output from the logic circuit is a 1/2 frequency-divided clock signal (the first 1/2 frequency-divided clock signal). Clock signal).
[0014]
In the clock signal switching device of the present invention, switching of the clock signal output from the logic circuit is performed by the clock signal generation circuit based on the logic state of the output signal of the synchronization circuit. This is performed depending on whether or not to output a signal.
[0015]
Here, the output signal of the synchronization circuit is a signal obtained by synchronizing the inversion point of the logic level of the selection signal with the original clock signal. On the other hand, the second 1/2 frequency-divided clock signal is a signal generated based on the first 1/2 frequency-divided clock signal. Since the first 1/2 frequency-divided clock signal is a signal generated based on the original clock signal, the second 1/2 frequency-divided clock signal is also synchronized with the original clock signal, similarly to the output signal. Signal. As described above, since the output signal of the synchronization circuit and the second 1/2 frequency-divided clock signal are both signals synchronized with the original clock signal, the second signal is synchronized with the change of the logic state of the output signal. During the period when the logic state of the 1/2 frequency-divided clock signal is held at the high level, the logic state is not forcibly shifted to the low level. As a result, clock signals can be switched without generating a hazard.
[0016]
The synchronization circuit may be a D-type flip-flop. When a D-type flip-flop is used, the selection signal is input to its data input terminal, and the original clock signal is input to the clock input terminal. The synchronized selection signal can be output.
[0017]
Here, a circuit that generates the first 1/2 frequency-divided clock signal based on the rising or falling timing of the original clock signal can be adopted as the frequency dividing circuit. As the clock signal generation circuit, a circuit including an AND circuit and a D-type flip-flop can be employed.
[0018]
In the case of such a clock signal generation circuit, the first 1/2 frequency-divided clock signal and the synchronized selection signal are input to the AND circuit. When the output signal of the AND circuit is input to the data input terminal of the D-type flip-flop and the inverted signal of the original clock signal is input to the clock input terminal, the second output signal is input from the non-inverted output terminal. / 2 frequency-divided clock signal can be output.
[0019]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a clock signal switching device to which the present invention is applied will be described with reference to the drawings. FIG. 1 is a block diagram of the clock signal switching device, and FIG. 2 is a timing chart showing the basic operation of the clock signal switching device. In the timing chart of FIG. 2, the rise and fall of the signal are illustrated in consideration of the signal propagation delay in each circuit.
[0020]
The clock signal switching device 1 selects one of the original clock signal CLK1 and a ク ロ ッ ク frequency-divided clock signal CLK (１ ／) obtained by dividing the original clock signal CLK1 by 応 じ according to the logic state of the selection signal SEL. This device selectively outputs such signals.
[0021]
The clock signal switching device 1 divides a frequency of an externally input original clock signal CLK by を to generate a first 分 frequency-divided clock signal Q1, and an externally input signal. The synchronization circuit 3 for synchronizing the inversion point of the logic level of the selection signal SEL with the original clock signal CLK, and the first 1 only when the output signal Q2 of the synchronization circuit 3 is in one of the logic states. A clock signal generating circuit 4 for generating a second 1/2 frequency-divided signal Q3 having a phase which is 90 degrees different from the 1/2 frequency-divided clock signal Q1 based on the 1/2 frequency-divided clock signal Q1, And a logic circuit (EX-OR circuit) 5 for outputting an exclusive OR of the 1/2 frequency-divided clock signals Q1 and Q2 as an output signal OUT.
[0022]
The frequency dividing circuit 2 and the synchronizing circuit 3 are each composed of a single D-type flip-flop (DF / F1, DF / F2). The clock signal generation circuit 4 includes an AND circuit 6 and a D flip-flop 7 (DF / F3).
[0023]
In the clock signal switching device 1, of the original clock signal CLK and the selection signal SEL input from the outside, the original clock signal CLK is input to the clock input terminal CK1 of the D-type flip-flop 2 which is a frequency dividing circuit. In the D-type flip-flop 2, the inverted output terminal / Q1 and the data input terminal D1 are bypassed. Therefore, the logical state of the signal Q1 output from the non-inverting output terminal Q1 changes from a low level to a high level or from a high level to a low level at the rising timing of the original clock signal CLK. In other words, the non-inverting output terminal Q1 of the D-type flip-flop 2 outputs the first 1/2 frequency-divided clock signal Q1 obtained by dividing the original clock signal CLK by 1/2. Here, the original clock signal CLK input to the clock signal switching device 1 is also input to the clock input terminal CK2 of the D-type flip-flop 3, which is a synchronization circuit. Further, an inverted signal of the original clock signal CLK is input to the clock input terminal / CK3 of the D-type flip-flop 7 of the clock signal generation circuit 4. The selection signal SEL is input to the data input terminal D2 of the D-type flip-flop 3.
[0024]
In the following, a description will be given assuming that the logic state of the selection signal SEL is held at a high level until time t1, and thereafter is held at a low level. In the D-type flip-flop 3, the logic state of the signal Q2 output from the non-inverting output terminal Q2 is determined only by the logic state of the selection signal SEL at the rising timing of the original clock signal CLK. Therefore, the output signal Q2 from the non-inverting output terminal Q2 is kept at a high level until the original clock signal CLK first rises after the time t1, and shifts to a low level based on the timing of the rise. (Time t2). As a result, an output signal Q2 in which the inversion point of the logic level of the selection signal SEL is synchronized with the original clock signal CLK is output from the non-inversion output terminal Q2.
[0025]
The first 1/2 frequency-divided clock signal Q1 and the output signal Q2 output from the non-inverting output terminals Q1 and Q2 of the D-type flip-flops 2 and 3 are input to an AND circuit 6, and their logical product is calculated. It is output as an output signal T1. This output signal T1 becomes the first 1/2 frequency-divided clock signal Q1 when the logic state of the output signal Q2 is at the high level, and is held at the low level state when it is at the low level. .
[0026]
The output signal T1 of the AND circuit 6 is input to the data input terminal D3 of the D-type flip-flop 7. An inverted signal of the original clock signal CLK is input to a clock input terminal / CK3 of the D-type flip-flop 7. Therefore, in the D-type flip-flop 7, depending on the rising timing of the inverted signal of the original clock signal CLK, that is, the logic state of the output signal T1 input to the data input terminal D3 at the falling timing of the original clock signal CLK. The logic state of signal Q3 output from normal output terminal Q3 is determined.
[0027]
Accordingly, the logic state of the signal Q3 output from the non-inversion output terminal Q3 of the D-type flip-flop 7 is as follows. The output signal T1 is synchronized with the inversion of the logic level of the output signal Q2, and until the logic state of the output signal T1 is held at the low level, the output signal T1 changes to the high level in accordance with the falling timing of the original clock signal CLK. From low to high or from low to high. As a result, a 1/2 frequency-divided clock signal (second 1/2 frequency-divided clock signal) Q3 is output from the non-inverting output terminal Q3. After the output signal T1 is synchronized with the inversion of the logic level of the output signal Q2 and the logic state of the output signal T1 is held at a low level, the logic state of the signal Q3 output from the non-inverting output terminal Q3 becomes Held at a low level. In other words, only when the logic state of the output signal Q2 of the D-type flip-flop 3, which is the synchronization circuit, is at a high level, the output from the non-inverting output terminal Q3 of the D-type flip-flop 7 is equal to the second half. The cycle clock signal Q3 is output.
[0028]
The first 1/2 frequency-divided clock signal Q1 and the second 1/2 frequency-divided clock signal Q3 from the D-type flip-flop 7 are output via the logic circuit 5.
[0029]
Here, since the second 1/2 frequency-divided clock signal Q3 is synchronized with the falling timing of the original clock signal CLK, the first 1/2 frequency synchronized with the rising timing of the original clock signal CLK. The phase of the divided clock signal Q1 is shifted from that of the divided clock signal Q1 by 90 degrees.
[0030]
Therefore, when the second 1/2 frequency-divided clock signal Q3 is output from the non-inverting output terminal Q3 of the D flip-flop 7, the logic circuit 5 outputs a clock signal having the same frequency as the original clock signal CLK1. You. On the other hand, when the state of the non-inverting output terminal Q3 of the D flip-flop 7 is held at a low level, the 1/2 frequency-divided clock signal CLK (1/2) (the first 1/2 frequency-divided clock signal Q1) ) Is output.
[0031]
As described above, in the clock signal switching device 1, the selection signal SEL input from the outside is converted into the output signal Q2 synchronized with the original clock signal CLK by the D flip-flop 3, which is a synchronization circuit. The output signal Q2 determines the presence or absence of the output of the second 1/2 frequency-divided clock signal Q3 based on the logic state. On the other hand, since the second 1/2 frequency-divided clock signal Q3 is a signal generated based on the first 1/2 frequency-divided clock signal Q1, it is a signal synchronized with the original clock signal CLK. As described above, since the second 1/2 frequency-divided clock signal Q3 and the output signal Q2 are both synchronized with the original clock signal CLK, the logic state of the second 1/2 frequency-divided clock signal Q3 is high. , Its logic state is not forced to a low level. Therefore, the output signal OUT can be switched to any one of the clock signal having the same frequency as the clock signal CLK1 and the 1/2 frequency-divided clock signal CLK2 without generating pulse-like noise.
[0032]
【The invention's effect】
As described above, in the clock signal switching device of the present invention, the first and second 1/2 frequency-divided clock signals having phases different from each other by 90 degrees are generated, and exclusive OR is performed on them. A clock signal having the same frequency as the clock signal is output. Further, the output of the second 1/2 frequency-divided clock signal is stopped, thereby outputting the 1/2 frequency-divided clock signal. The output of the second 1/2 frequency-divided clock signal is stopped using a selection signal synchronized with the original clock signal. In this way, the output signal can be switched to the clock signal or its 1/2 frequency-divided clock signal without causing a hazard.
[Brief description of the drawings]
FIG. 1 is a block diagram of a clock signal switching device to which the present invention is applied.
FIG. 2 is a timing chart showing a basic operation of the clock signal switching device of FIG. 1;
FIG. 3 is a block diagram of a conventional clock signal switching device.
FIG. 4 is a timing chart showing a basic operation of the clock signal switching device of FIG. 3;
[Explanation of symbols]
1 clock signal switching device 2 D-type flip-flop (frequency divider)
3D flip-flop (synchronization circuit)
4 Clock signal generation circuit 5 Logic circuit 6 AND circuit 7 D-type flip-flop Q1 First 1/2 frequency-divided clock signal Q2 Second 1/2 frequency-divided clock signal SEL Selection signal CLK Original clock signal CLK1 Original clock signal CLK2 1/2 frequency-divided clock signal

Claims (3)

A clock signal switching device for selectively outputting a clock signal and one of a 1/2 frequency-divided clock signal obtained by dividing the clock signal by 1/2 based on a logic state of a selection signal,
A frequency dividing circuit for dividing the original clock signal by 1/2 to generate a first 1/2 frequency-divided clock signal;
A synchronization circuit for synchronizing the inversion point of the logic level of the selection signal with the original clock signal,
Only when the output signal of the synchronization circuit is in one of the logic states, the phase is shifted by 90 degrees from the 1/2 frequency-divided clock signal based on the first 1/2 frequency-divided clock signal. A clock signal generation circuit for generating a second 1/2 frequency-divided clock signal;
A logic circuit that outputs an exclusive OR of the first and second 1/2 frequency-divided clock signals as a clock signal. In claim 1,
The synchronization circuit includes a D-type flip-flop. The selection signal is input to a data input terminal of the D-type flip-flop, the original clock signal is input to a clock input terminal, and a logic output is output from a non-inversion output terminal. A clock signal switching device, wherein the selection signal whose level inversion point is synchronized with the original clock signal is output. In claim 2,
The frequency divider circuit generates the first 1/2 frequency-divided clock signal based on the rising or falling timing of the original clock signal;
The clock signal generation circuit includes an AND circuit and a D-type flip-flop,
The AND circuit receives the first 1/2 frequency-divided clock signal and the synchronized selection signal,
An output signal of the AND circuit is input to a data input terminal of the D-type flip-flop, an inverted signal of the original clock signal is input to a clock input terminal of the D-type flip-flop. A clock signal switching device for outputting a 1/2 frequency-divided clock signal.

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