JP2005236549A - Clock signal switching circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock signal switching circuit capable of switching a clock signal surely by eliminating collision of a clock signals before/after switching or missing of the clock signal. <P>SOLUTION: The clock signal switching circuit comprises a frequency division circuit 1, a synchronization circuit 2 and a clock selection circuit 3, wherein the clock selection circuit 3 comprises a first clock enabler 31, a second clock enabler 32 and an OR circuit 33. The first clock enabler 31 has a clock enable terminal E being fed with a second clock switching signal, and a clock input terminal CK being fed with a frequency division clock XI/2. The second clock enabler 32 has a clock enable terminal E being fed with a first clock switching signal, and a clock input terminal CK being fed with a clock signal XI. A clock signal selected by the first clock enabler 31 or the second clock enabler 32 is outputted through the OR circuit 33. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a clock signal switching circuit that switches a clock signal without generating a whisker-like pulsed clock.

As a conventional clock signal switching circuit, there is a circuit that switches a clock signal using a multiplexer or the like.
In addition, there is a clock signal switching circuit having a synchronization circuit that generates a selection signal of a selection circuit that selects either a master clock or a clock obtained by dividing the master clock in synchronization with the master clock (for example, Patent Document 1).
JP-A-63-232615

Such a conventional clock signal switching circuit is accompanied by the following disadvantages. In the former clock signal switching circuit, a whisker-like pulsed clock is generated at the time of clock signal switching due to the skew and circuit configuration of each clock signal. There was a problem that generation of a clock could not be avoided.
In the latter clock signal switching circuit, since one of the two clocks CLK0 and CLK1 is selected by a single selection signal synchronized with the rising edge of the master clock, the selected clock CLK has a whisker shape. There has been a problem that a pulse-shaped clock may be generated.

  The present invention has been made in view of such circumstances, and eliminates the collision and clock omission of the clock signal before switching and the clock signal after switching, and generates a whisker-like pulse clock at the time of clock signal switching. It is an object of the present invention to provide a clock signal switching circuit that can prevent the above-described problem and reliably switch the clock signal.

  In order to achieve the above object, a clock signal switching circuit according to the present invention generates a frequency-divided clock signal based on a master clock signal and an asynchronous control signal generated by the frequency-divided circuit. And a clock switching signal corresponding to the selected clock signal to be selected including the master clock signal and the divided clock signal is generated based on the synchronized control signal. A synchronization circuit; and a clock selection circuit that selects and outputs the selection target clock signal based on the clock switching signal, and the clock selection circuit includes the clock at a timing when the state of the selection target clock signal changes. A clock enable that controls the output of the clock signal to be selected based on a latch operation that holds the state of the switching signal. Characterized in that it comprises a.

  According to the present invention, collision between a clock signal before switching and a clock signal after switching and clock omission are eliminated, generation of a whisker-like pulsed clock at the time of clock signal switching is prevented, and clock signals are switched reliably. Therefore, there is an effect that it is possible to provide a clock signal switching circuit that can be used.

  An object of the present invention is to provide a clock signal switching circuit capable of preventing a collision of a clock signal before switching and a clock signal after switching and a clock omission, preventing generation of a whisker-like pulsed clock, and switching the clock signal reliably. The frequency-divided clock signal is generated by the frequency divider circuit based on the master clock signal, and the asynchronous control signal is synchronized by the frequency-divided clock signal generated by the frequency divider circuit by the synchronization circuit, Based on the synchronized control signal, a clock switching signal corresponding to the selection target clock signal including the master clock signal and the divided clock signal is generated, and a clock selection circuit converts the selection target clock signal to the clock This was realized by selecting and outputting based on the switching signal. At this time, the clock enabler of the clock selection circuit controls the output of the selection target clock signal based on a latch operation that holds the state of the clock switching signal at the timing when the state of the selection target clock signal changes. .

FIG. 1 is a block diagram showing the configuration of the clock signal switching circuit of the first embodiment. This clock signal switching circuit receives an asynchronous control signal Sel and a clock signal XI, and also has a control signal obtained by synchronizing the asynchronous control signal Sel with a 1 / 2n (for example, n = 1) divided clock of the clock signal XI. And a plurality of clock switching signals are generated. Then, either the 1 / 2n frequency-divided clock or the clock signal XI is selected by each generated clock switching signal.
This clock signal switching circuit includes a frequency dividing circuit 1, a synchronizing circuit 2, and a clock selecting circuit 3. The frequency dividing circuit 1 is a circuit that divides the clock signal XI by 1 / 2n (for example, n = 1) and generates a 1 / 2n frequency-divided clock of the clock signal XI. The synchronization circuit 2 synchronizes the asynchronous control signal Sel with the 1 / 2n frequency-divided clock generated by the frequency-dividing circuit 1, and sends the asynchronous control signal Sel to the 1 / 2n-frequency-divided clock generated by the frequency-dividing circuit 1. A synchronized control signal is generated, and a plurality of clock switching signals corresponding to the selected clock signal to be selected including the clock signal XI and the 1 / 2n divided clock signal are generated based on the control signal. Circuit. The clock selection circuit 3 is a circuit that selects either the clock signal XI or the ½n frequency-divided clock generated by the frequency divider 1 based on the clock switching signal generated by the synchronization circuit 2.

  FIG. 2 is a logic circuit diagram showing a logic circuit configuration of the frequency dividing circuit 1, the synchronizing circuit 2 and the clock selecting circuit 3 of the clock signal switching circuit according to the first embodiment. In FIG. 2, the same or corresponding parts as those in FIG. The frequency dividing circuit 1 includes a D flip-flop 11 and an inverter circuit 12, and a clock signal XI is supplied to a clock input terminal CK of the D flip-flop 11. The input terminal of the inverter circuit 12 is connected to the output terminal Q of the D flip-flop 11, and the output terminal of the inverter circuit 12 is connected to the data input terminal D of the D flip-flop 11.

  The synchronization circuit 2 includes a first D flip-flop 21, a second D flip-flop 22, a third D flip-flop 23, and a combinational circuit 24 that constitute a shift register. The clock input terminals CK of the first D flip-flop 21, the second D flip-flop 22, and the third D flip-flop 23 constituting the shift register are commonly connected. The commonly connected clock input terminals CK are connected to the output terminal Q of the D flip-flop 11 of the frequency divider circuit 1. Further, the asynchronous control signal Sel is input to the data input terminal D of the first D flip-flop 21. The combinational circuit 24 is connected to the output terminal Q of the second D flip-flop 22 and the output terminal Q of the third D flip-flop 23 that constitute the shift register. The combinational circuit 24 has a clock switching signal output terminal (not shown) that outputs the first clock switching signal Sel delay 1 and the second clock switching signal Sel delay 2 respectively.

  The clock selection circuit 3 includes a first clock enabler 31, a second clock enabler 32, and an OR circuit 33. The clock enable terminal E of the first clock enabler 31 is connected to the clock switching signal output terminal that outputs the second clock switching signal Sel delay 2 of the combinational circuit 24. The clock input terminal CK of the first clock enabler 31 is connected to the output terminal Q of the D flip-flop 11 of the frequency divider circuit 1. The output terminal of the first clock enabler 31 is connected to one input terminal of the OR circuit 33.

  The clock enable terminal E of the second clock enabler 32 is connected to the clock switching signal output terminal that outputs the first clock switching signal Sel delay 1 of the combinational circuit 24. The clock signal XI is supplied to the clock input terminal CK of the second clock enabler 32. The output terminal of the second clock enabler 32 is connected to the other input terminal of the OR circuit 33. A clock signal switched by the first clock enabler 31 or the second clock enabler 32 is output from the output terminal of the OR circuit 33.

  FIG. 3 is a logic circuit diagram showing the configuration of the first clock enabler 31 and the second clock enabler 32. As shown in FIG. 3, the first clock enabler 31 and the second clock enabler 32 include a latch circuit (flip-flop circuit) 301 and an AND circuit (gate circuit) 302. The latch circuit 301 includes a clock enable terminal D (E), a clock input terminal GN (CK) that is a low active input terminal, an output terminal Q, and an output terminal QN, and operates according to the truth table shown in FIG. The clock switching signal output terminal of the combinational circuit 24 is connected to the clock enable terminal D (E), the second clock switching signal Sel delay 2 is input to the first clock enabler 31, and the second The clock enabler 32 is configured to receive the first clock switching signal Sel delay 1. Further, the 1 / 2n frequency-divided clock of the clock signal XI output from the output terminal Q of the D flip-flop 11 of the frequency divider 1 is input to the clock input terminal GN (CK) of the first clock enabler 31, or The clock signal XI is input to the clock input terminal GN (CK) of the second clock enabler 32. One input terminal of the AND circuit 302 is connected to the output terminal Q of the latch circuit 301, and the other input terminal is connected to the clock input terminal GN (CK) of the latch circuit 301.

Next, the operation will be described.
FIG. 4 is a truth table showing the operation of the latch circuit of the clock enabler used in the clock signal switching circuit. FIG. 5 is a timing chart showing the operation of the clock signal switching circuit. FIG. 6 is a timing chart showing the operation of the clock enabler. The operation will be described below with reference to these timing charts, the truth table shown in FIG. 4, and the logic circuit diagrams shown in FIGS.
First, the clock signal XI shown in FIG. 5B is supplied to the clock input terminal CK of the D flip-flop 11 of the frequency dividing circuit 1 shown in FIG. As a result, from the output terminal Q of the D flip-flop 11 of the frequency dividing circuit 1, the frequency-divided clock XI / 2 shown in FIG. This is supplied to the clock input terminals CK of the first D flip-flop 21, the second D flip-flop 22 and the third D flip-flop 23 that constitute the shift register of the circuit 2. On the other hand, the asynchronous control signal Sel shown in FIG. 5A is supplied to the data input terminal D of the first D flip-flop 21 constituting the shift register. The asynchronous control signal Sel is not synchronized with the clock signal XI. The first D flip-flop 21 of the shift register transmits the asynchronous control signal Sel from the data input terminal D to the divided clock XI / 2 in synchronization with the rising edge of 2 and in synchronization with the rising edge of the fifth divided clock XI / 2 according to the pulse width of the asynchronous control signal Sel and the rising timing of the divided clock XI / 2. A control signal Sel (1d) shown in FIG. 4 (D) having a pulse width corresponding to four periods of the divided clock XI / 2, which is at the “Low” level, is generated and output from the output terminal Q. Further, the second D flip-flop 22 of the shift register synchronizes the output of the output terminal Q of the first D flip-flop 21 with the rising edge of the divided clock XI / 2 from the data input terminal D. From the output terminal Q, the control signal Sel (2d) shown in FIG. 5E, which is delayed by one cycle of the divided clock XI / 2 from the control signal Sel (1d), is output. The third D flip-flop 23 of the shift register synchronizes the output of the output terminal Q of the second D flip-flop 22 with the rising edge of the divided clock XI / 2 from the data input terminal D. From the output terminal Q, the control signal Sel (3d) shown in FIG. 5F, which is delayed by one cycle of the divided clock XI / 2 from the control signal Sel (2d), is output.

  FIG. 5G shows the first clock switching signal Sel Delay 1 generated by the combinational circuit 24 of the synchronization circuit 2 based on the control signal Sel (2d) and the control signal Sel (3d). FIG. 6H shows the second clock switching signal Sel Delay 2 generated by the combinational circuit 24 in the same manner. As shown in FIG. 5, the first clock switching signal Sel Delay 1 and the second clock switching signal Sel Delay 2 are “Low” for one cycle of the divided clock XI / 2 or two cycles of the clock signal XI. Generated and output at level intervals. The combinational circuit 24 of the synchronization circuit 2 is based on the control signal Sel (2d) and the control signal Sel (3d), and the first clock switching signal Sel Delay 1 shown in FIG. The logic configuration is such that the second clock switching signal Sel Delay 2 shown in FIG.

  The second clock switching signal Sel Delay 2 is supplied to the latch data input terminal D (E) of the first clock enabler 31, and the latch data input terminal D (E) of the second clock enabler 32 is supplied to the latch data input terminal D (E). The first clock switching signal Sel Delay 1 is supplied. The frequency-divided clock XI / 2 is supplied to the clock input terminal GN (CK) of the first clock enabler 31, and the clock signal is supplied to the clock input terminal GN (CK) of the second clock enabler 32. XI is supplied.

  As is apparent from the truth table of the clock enabler shown in FIG. 4 and the timing chart of the clock enabler shown in FIG. 6, the clock enabler is configured so that the clock signal supplied to the clock input terminal GN (CK) is at the “Low” level. The signal applied to the latch data input terminal D (E) is latched at the moment of changing to the “High” level, that is, at the timing of the rising edge of the clock signal, and latched to the output terminal Q after a predetermined delay time. A signal is output, and the latched signal is continuously output to the output terminal Q while the clock signal is at the “High” level. Then, the signal applied to the latch data input terminal D (E) is transferred to a predetermined delay time d at the moment when the clock signal changes from “High” level to “Low” level, that is, at the timing of the falling edge of the clock signal. To output to the output terminal Q as it is.

  The delay time d is a delay time included in the latch circuit 301 shown in FIG. 3. In the clock enabler, the latch w is latched as necessary so that the output w2 of the latch circuit 301 is delayed from the clock signal CK (w3). A delay can be given to the output signal from the output terminal Q of the circuit 301.

  The signal applied to the latch data input terminal D (E) is a clock switching signal. This clock switching signal is a signal obtained by synchronizing the asynchronous control signal Sel with the divided clock XI / 2. Therefore, this clock switching signal is usually compared with the rising and falling timings of the divided clock XI / 2 generated by the dividing circuit 1 or the clock signal XI supplied to the dividing circuit 1. Therefore, a delay occurs due to the passage through the logic circuit of the synchronization circuit 2. D1 and D2 shown in the timing chart of FIG. 6 indicate delay times due to the clock switching signal being generated by the synchronization circuit 2. In the clock enabler, since the change of the signal (clock switching signal) applied to the latch data input terminal D (E) is performed in the “High” level section of the clock signal, the clock signal is the clock signal XI or the divided signal. In any of the peripheral clocks XI / 2, this condition is satisfied in the clock switching signal by the delay times D1 and D2. The output w2 of the latch circuit 301 is delayed by a half cycle of the clock signal as compared with the rising timing of the signal applied to the latch data input terminal D (E). Since the delay time d is given, the clock enabler output ECK, which is the logical product of the output w2 of the latch circuit 302 and the clock signal CK (signal W3), is reliable for one cycle of the clock signal when the clock is switched by the clock switching signal. As shown in the timing chart of FIG. 6, the output is an ECK with one clock missing.

  As a result, as shown in the waveform diagram of FIG. 5 (l), the current clock signal is switched from the clock signal XI to the divided clock XI / 2 by the second clock switching signal Sel Delay 2. This is the same when switching to the clock signal XI by the first clock switching signal Sel Delay 1 or vice versa, but the divided clock XI / 2 after switching is the second clock switching signal Sel Delay. This is a signal from which one clock immediately after 2 is given. In addition, when switching to the clock signal XI by the opposite first clock switching signal Sel Delay 1, the clock signal XI after switching is one immediately after the first clock switching signal Sel Delay 1 is given. Minute clock is missing.

  Therefore, according to the first embodiment, the collision between the clock signal before the switching and the clock signal after the switching is eliminated, and the generation of the whisker-like pulsed clock that may occur at the switching of the clock signal is eliminated, thereby reliably. There is an effect that a clock signal switching circuit capable of switching the clock signal can be provided.

FIG. 7 is a block diagram showing an example of the electronic circuit of the second embodiment. This electronic circuit has a function of switching clock signals having different repetition frequencies as required by the clock signal switching circuit described in the first embodiment. Many types of electronic circuits can be assumed, but when used in a device that monitors power supply capacity, switching to a clock signal with a low frequency according to the capacity of the power supply being monitored can reduce power consumption. Can be suppressed.
Also, in the case of a device equipped with a temperature detection circuit, when an abnormal temperature is reached, the signal from the temperature detection circuit is used as a clock switching signal, and the frequency of the operation clock is reduced to suppress heat generation and power consumption. It is also possible.

  In FIG. 7, the electronic circuit using the clock signal switching circuit includes the clock signal switching circuit 51, the clock management and clock buffer 52, the plurality of synchronization circuits 54, and the control circuit group 55 described in the first embodiment. In the control circuit group 55, a selection signal for switching the clock signal is generated and output to the clock signal switching circuit 51. This selection signal corresponds to the asynchronous control signal Sel shown in FIGS.

  When an appropriate control signal is added when the CPU, MPU, and state control circuit of the control circuit group 55 issues a clock switching request, the operation clock of the entire electronic circuit can be switched from the processing device.

It is a block diagram which shows the structure of the clock signal switching circuit of Example 1 of this invention. FIG. 3 is a logic circuit diagram illustrating a logic circuit configuration of a frequency divider circuit, a synchronization circuit, and a clock selection circuit of the clock signal switching circuit according to the first embodiment of the present invention. It is a logic circuit diagram which shows the structure of the clock enabler of the clock signal switching circuit of Example 1 of this invention. It is a truth table which shows operation | movement of the latch circuit of the clock enabler used for the clock signal switching circuit of Example 1 of this invention. It is a timing chart which shows operation | movement of the clock signal switching circuit of Example 1 of this invention. It is a timing chart which shows operation | movement of the clock enabler used for the clock signal switching circuit of Example 1 of this invention. It is a block diagram which shows an example of the electronic circuit of this Example 2 using the clock signal switching circuit of Example 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Frequency divider, 2 ... Synchronization circuit, 3 ... Clock selection circuit, 31 ... 1st clock enabler, 32 ... 2nd clock enabler, 301 ... Latch circuit (flip-flop circuit), 302: AND circuit (gate circuit).

Claims (3)

A frequency dividing circuit for generating the divided clock signal based on the master clock signal;
Asynchronous control signal is synchronized with the divided clock signal generated by the divider circuit, and based on the synchronized control signal, a selection including the master clock signal and the divided clock signal is selected. A synchronization circuit for generating a clock switching signal corresponding to the target clock signal;
A clock selection circuit that selects and outputs the selection target clock signal based on the clock switching signal;
The clock selection circuit includes:
A clock comprising a clock enabler that controls the output of the selection target clock signal based on a latch operation that holds the state of the clock switching signal at a timing when the state of the selection target clock signal changes. Signal switching circuit.   The clock enabler holds the state of the clock switching signal at a timing when the state of the selection target clock signal changes from the first level to the second level, outputs the held state, and the selection target clock signal A flip-flop circuit that outputs the state of the clock switching signal at the timing when the state of the signal changes from the second level to the first level, and based on the output of the flip-flop circuit, outputs the clock signal to be selected 2. The clock signal switching circuit according to claim 1, further comprising a gate circuit for control. 3. The clock signal switching circuit according to claim 2, wherein the clock switching signal supplied to the clock enabler changes when the selection target clock signal is in the second level state.

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