KR20040031532A - Asynchronous glitchless digital multiplexer with power saving mode - Google Patents

Abstract

PURPOSE: An asynchronous digital multiplexer having a power saving mode for generating an output signal without a glitch is provided to perform a low-power high-speed switching operation by generating the output signal without the glitch in the power saving mode. CONSTITUTION: An asynchronous digital multiplexer having a power saving mode for generating an output signal without a glitch includes an edge detection circuit(10), a selection synchronization circuit(30), a clock signal synchronization circuit(50), and a power saving mode selection circuit(70). The edge detection circuit(10) receives a data selection signal, detects an edge, and generates the first control signal. The selection synchronization circuit(30) receives the data signal, the first clock input signal, and the second clock input signal and selects one of the first clock input signal and the second clock input signal according to the second control signal. The clock signal synchronization circuit(50) receives the first control signal and an output signal of the selection synchronization circuit, synchronizes the first control signal with the selected clock input signal, and generates the second control signal. The power saving mode selection circuit(70) receives the second control signal, an output signal of the clock signal synchronization circuit, and a power-down signal and an output clock signal.

Description

ASYNCHRONOUS GLITCHLESS DIGITAL MULTIPLEXER WITH POWER SAVING MODE}

TECHNICAL FIELD The present invention relates to an asynchronous digital multiplexer, and more particularly, to an asynchronous digital multiplexer which has a power saving mode and does not cause glitches on the output.

May occur when the asynchronous signal is selected in a microprocessor, a digital signal processor (DSP), or the like.

Digital multiplexers are devices having two or more input data, one or more selection signals, and one output, and are used for various purposes in the field of electronics.

One feature of the digital multiplexer is that once the selection signal changes, the output begins to reflect the newly selected input data as soon as the selection signal propagates through internal logic. If the selected input data are asynchronous with each other, the output pulse width may be narrower than the pulse width of the input data having the narrowest pulse width. This is called glitch. Pulses lower than the minimum pulse width can cause the system to malfunction, so this glitch poses a significant problem for digital systems. Thus, there is a need for glitch-free switching between asynchronous digital inputs into the multiplexer. Asynchronous digital multiplexers without glitch are disclosed in US Pat. No. 5,231,636.

On the other hand, it is necessary to minimize the power consumed for low power high speed switching. Accordingly, there is a need for a digital multiplexer having a power saving mode for synchronizing the clock switched output with the power control signal.

The asynchronous digital multiplexer according to the present invention is synchronously outputted under the control of an output clock signal from which glitch has been removed and a signal having a logical sum with the power down signal in a power saving mode.

It is an object of the present invention to provide an asynchronous digital multiplexer that has a power saving mode and does not cause glitch on the output.

1 is a diagram illustrating an embodiment of an asynchronous digital multiplexer having a power saving mode according to the present invention.

2 is a view illustrating in detail the edge detection circuit of FIG.

FIG. 3 is a timing diagram illustrating waveforms of respective parts of the circuit of FIG. 1 illustrating a process of removing glitches. FIG.

4 is a timing diagram showing waveforms of respective parts of the circuit of FIG. 1 for explaining a power saving mode.

<Description of the symbols for the main parts of the drawings>

10: edge detection circuit 30: selective synchronization circuit

50: clock signal synchronization circuit 70: saving mode selection circuit

An asynchronous digital multiplexer according to the present invention receives an edge selection circuit for receiving a data selection signal and detecting an edge to generate a first control signal, the data selection signal, a first clock input signal, and a second clock input signal. And a selection synchronization circuit for selecting one of the first clock input signal and the second clock input signal under the control of a second control signal, receiving an output signal of the first control signal and the selection synchronization circuit, and receiving the data selection signal. And a clock signal synchronizing circuit for synchronizing the selected clock input signal and generating a second control signal, and an economy mode selection for receiving an output signal and a power down signal of the second control signal and the selection synchronizing circuit and generating an output clock signal. It is characterized by including a circuit.

The economy mode selection circuit receives the output signal and the power down signal of the selection synchronization circuit, receives the fourth D-FF and the second control signal and the power down signal to generate a synchronized power down signal, and performs a logical sum. An OR circuit for generating an output enable signal, and a latch circuit for receiving and latching an output signal of the selection synchronization circuit to a D input terminal under the control of the output enable signal and generating the output clock signal. do.

Hereinafter, an asynchronous digital multiplexer according to the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating an embodiment of an asynchronous digital multiplexer having a power saving mode according to the present invention. The asynchronous digital multiplexer of FIG. 1 receives the data select signal SEL, detects an edge, and detects an edge to generate a first control signal EDO, a data select signal SEL, and a first clock. A selection for receiving the input signal CLK1 and the second clock input signal CLK2 and selecting one of the first clock input signal CLK1 and the second clock input signal CLK2 under the control of the second control signal CSO. Receives an output signal SSO of the synchronization circuit 30, the first control signal EDO and the selection synchronization circuit 30, synchronizes the data selection signal SEL and the clock signal, and controls the second control signal CSO. Receives the clock signal synchronizing circuit 50 and the output signal SSO and the power down signal PWM of the second control signal CSO and the selection synchronizing circuit 30 and outputs the output clock signal CLKO. The economy mode selection circuit 70 which produces | generates is provided.

The selection synchronizing circuit 30 receives a data selection signal SEL and generates a latch circuit 34 for generating a multiplexer input selection signal MIS under the control of the second control signal CSO, and the first clock input signal CLK1. ) And a second clock input signal CLK2, and under the control of the multiplexer input selection signal MIS, one of the two signals is selected to generate the output signal SSO of the selection synchronization circuit 30. ).

The clock signal synchronizing circuit 50 has a D input terminal to which the power supply voltage VDD is applied and a clear terminal CLR to which the inverted second control signal CSOB is applied, and under the control of the first control signal EDO A latch circuit 52 for latching and outputting the " 1 " state VDD of the input terminal, receives the output of the latch circuit 52 and the output signal SSO of the selection synchronization circuit 30, and generates an output delayed one cycle. Receive the output of the first D-FF (D-FF) 54, the output of the first D-FF 54 and the output signal SSO of the selection synchronization circuit 30, and generate an output delayed by one period. And a third D-FF (56) for receiving the output of the second D-FF (56) and the output signal (SSO) of the selection synchronization circuit (30) and generating an output delayed one cycle ( 58).

The economy mode selection circuit 70 receives the output signal SSO and the power down signal PWD of the selection synchronization circuit 30 and generates a fourth D-FF 72 for generating a synchronized power down signal PWDS; OR circuit 74 for receiving the second control signal CSO and the power down signal PWMS and performing a logical OR to generate an output enable signal OEN, and a D input terminal under the control of the output enable signal OEN. And a latch circuit 76 for receiving and latching the output signal SSO of the row select synchronization circuit 30 and generating the output clock signal CLKO.

2 is a view illustrating in detail the edge detection circuit of FIG. The edge detection circuit of FIG. 2 receives a delay circuit 12 that receives the data selection signal SEL and delays a predetermined time, and receives an output signal of the data selection signal SEL and the delay circuit 12 and performs an exclusive nonlogical sum. An XNOR (Exclusive NOR) 14 circuit is provided.

FIG. 3 is a timing diagram showing waveforms of each part of the circuit of FIG. 1 showing a process of removing glitch, and FIG. 4 is a timing diagram showing waveforms of each part of the circuit of FIG. 1 for explaining a power saving mode.

Hereinafter, an operation of the asynchronous digital multiplexer according to the present invention will be described with reference to FIGS. 1 to 4.

The edge detection circuit 10 is composed of an XNOR 14 and a delay circuit 12. When the data selection signal SEL is generated, the edge detection circuit 10 synchronizes the clock only with respect to a signal inputted with a time difference, and performs a clock for a predetermined time. It stops.

In the selection synchronizing circuit 30, the multiplexer 32 is selected from the two clock input signals CLK1 and CLK2 by the multiplexer input selection signal MIS generated by the latch circuit 34 when the synchronized selection signal is input. Choose one.

When the data selection signal SEL is detected, the clock signal synchronizing circuit 50 synchronizes the data selection signal SEL with a clock input signal currently output, and then generates a second control signal CSO. By controlling the multiplexer 32 and resynchronizing with the newly selected clock input signal, the noise canceled output can be selected. Here, the reason for using three flip-flops for synchronization is to convert an unstable signal into a stable signal.

In the economy mode selection circuit 70, the power down signal PWM is output in synchronization with the clock signal from which the noise is removed.

FIG. 3 is a timing diagram illustrating waveforms of respective parts of the circuit of FIG. 1 showing a process of removing glitches, wherein the power down signal PWM is in a state of "0". An asynchronous digital multiplexer having a power saving mode according to the present invention shown in FIG. Signal CLK2 is selected. When the second clock input signal CLK2 is selected, the data detection signal SEL is detected by the edge detection circuit 10 to bring the second control signal CSO to a "1" state. The clock signal is delayed by one cycle by the flip-flops 54, 56, 58. The second control signal CSO initializes the latch circuit 52 and simultaneously enables the latch circuit 34 of the selection synchronization circuit 30 so that the second clock input signal CLK1 to the second clock input signal CLK2 are performed. Low clock change occurs. As can be seen in FIG. 3, the second control signal CSO is in a " 1 " state, and the output signal SSO of the selection synchronization circuit 30 is converted from the first clock input signal CLK1 to the second clock input signal ( CLK2). However, since a glitch may occur at the moment when the first clock input signal CLK1 is changed from the second clock input signal CLK2, the output enable signal OEN of the economy mode selection circuit 70 may be prevented. The latch circuit 76 to which is applied is used.

FIG. 4 is a timing diagram showing waveforms of respective parts of the circuit of FIG. 1 for explaining the power saving mode, and the data selection signal SEL and the first control signal EDO are in a "1" state, and the power down signal ( PWD) is coming out. When the power down signal PWM is in the " 1 " state, it can be seen that the output enable signal OEN is maintained in the " 1 " state and the output clock signal CLKO is maintained in the " 1 " state.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the asynchronous digital multiplexer according to the present invention has a power saving mode and does not generate glitch at the output, and thus can be applied to a low power high speed switching system.

Claims (5)

An edge detection circuit for receiving a data selection signal and detecting an edge to generate a first control signal; A selection synchronization circuit that receives the data selection signal, the first clock input signal and the second clock input signal and selects one of the first clock input signal and the second clock input signal under the control of a second control signal; A clock signal synchronization circuit for receiving the first control signal and the output signal of the selection synchronization circuit, synchronizing the data selection signal with the selected clock input signal, and generating a second control signal; And And an economy mode selection circuit for receiving the second control signal, the output signal of the selection synchronization circuit and a power down signal, and generating an output clock signal. The method of claim 1, wherein the edge detection circuit A delay circuit for receiving the data selection signal and delaying a predetermined time; And And an XNOR circuit for receiving the data selection signal and the output signal of the delay circuit and performing an exclusive illogical sum. The method of claim 1, wherein the selection synchronization circuit A latch circuit for receiving the data selection signal and generating a multiplexer input selection signal under control of the second control signal; And And a multiplexer for receiving the first clock input signal and the second clock input signal and selecting one of the two signals under the control of the multiplexer input selection signal to generate a selection synchronization circuit output signal. Multiplexer. The method of claim 1, wherein the clock signal synchronization circuit A latch circuit having a D input terminal to which a power supply voltage is applied and a clear terminal to which the second control signal inverted is applied, and latching and outputting a "1" state of the D input terminal under the control of the first control signal; A first D-FF for receiving the output of the latch circuit and the output signal of the selection synchronization circuit and generating an output delayed by one period; A second D-FF receiving the output of the first D-FF and the output signal of the selection synchronization circuit and generating an output delayed by one period; And And a third D-FF for receiving the output of the second D-FF and the output signal of the selection synchronization circuit and generating a one-cycle delayed output. The method of claim 1, wherein the saving mode selection circuit A fourth D-FF receiving the output signal and the power down signal of the selection synchronization circuit and generating a synchronized power down signal; An OR circuit for receiving the second control signal and the power down signal and performing a logical sum to generate an output enable signal; And And a latch circuit for receiving and latching an output signal of the selection synchronization circuit to a D input terminal under the control of the output enable signal and generating the output clock signal.