KR100294343B1 - Data input buffer of ddr(double data rate) synchronous dram - Google Patents

Abstract

PURPOSE: A data input buffer of a DDR(Double Data Rate) synchronous DRAM is provided, which enables a high speed operation, by lengthening a timing margin of a strobing signal. CONSTITUTION: A rising data input buffer(20) inputs data inputted through an input buffer(10) by synchronizing it to a rising edge of a clock, and a falling data input buffer(30) inputs data inputted through the input buffer by synchronizing it to a falling edge of the clock. A signal delay part(40) delays an output of the rising data input buffer to synchronize the output to the falling edge of the clock. A switch circuit part(50) switches even and odd data from the signal delay part and the falling data input buffer to an even data input/output buffer and an odd data input/output buffer, according to a control signal(SO_SEB). An even data input/output buffer(60) transfers the even data switched from the switch circuit part to a global input/output line, and an odd data input/output buffer(70) transfers the odd data switched from the switch circuit part to the global input/output line.

Description

Data Synchronization Buffer of DI Synchronous DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a synchronous DRAM (DRAM), and more particularly to a data input buffer that receives data during a write operation of a digital synchronous DRAM. Strobing, consisting of a buffer and a falling data input buffer, and synchronizing two data from the two data input buffers, passing from the data input buffer to the global input / output line. The present invention relates to a data input buffer of a digital synchronous DRAM that increases the timing margin of a signal to enable high-speed operation.

In general, the buffer structure for the write operation of the digital synchronous DRAM comprises: an even data input buffer 2 for inputting even data among data input through the input buffer 1; An odd data input buffer (3) for inputting odd data among data input through the input buffer (1); A switch circuit section (4) for switching on / off in accordance with an even or odd number of data input from the even data input buffer (2) or the odd data input buffer (3); An even data input / output buffer (5) carrying the even data switched from the switch circuit section (4) to a global input / output line; And an odd data input / output buffer 6 which carries odd data switched from the switch circuit section 4 to a global input / output line.

However, the write structure of the DI synchronous DRAM configured as described above uses an even data input buffer 2 and an odd data input buffer 3 in which the data input buffer is determined according to whether the data is even or odd. Write structure using the even and odd data directly from the data input / output buffers 5 and 6 that carry the output of the data input buffer 1 to a global input / output line. Has the following problems:

That is, when the write command is continuously entered and the continuous write command is changed from even data to odd data or from odd data to even data, the signal coming into the input of the data input / output buffers 5 and 6 is normally Ramen only changes once per clock.

However, in FIG. 2, only half a clock is changed.

Here, the minimum pulse width of dinstb, which is a signal strobing data in the data input / output buffers 5 and 6, is assumed to be 2 nanosecs (ns) as shown in Fig. 2D. If the margin between the data input to the even data input / output buffer 60 and the odd data input / output buffer 70 and the dinstb signal is 1 ns, the minimum size of the half clock is about 3 ns.

However, since the duty clock of the external clock is 0.45tCLK as shown in FIG. 2A, a value of 3ns corresponds to 0.45tCLK.

1) Considering 0.45tCLK is 3ns, the maximum frequency is 150MHz

2) If 0.45tCLK is 3.5ns, the maximum frequency is 128MHz

Becomes

In addition, even_dinclk or odd data input buffer 3, which is a signal generated by the even data input buffer 2 to synchronize data with a clock, in order to strobe data from the even data input buffer 2 and the odd data input buffer 3, One of the odd_dinclk signals created to synchronize the data to the clock must be 0.45tCLK, so it is difficult to find a margin for the time it takes to precharge the data input buffer and guarantee the waveform of the pulse. There is a problem that it is difficult to limit the implementation of high-speed operation.

Accordingly, the present invention was devised to solve the above-mentioned problems. The data input buffer for receiving data during a write operation of a digital synchronous DRAM is falling with a rising data input buffer. By configuring a data input buffer and synchronizing two data from the two data input buffers, the timing margin of the strobing signal passed from the data input buffer to the global input / output line is increased. The aim is to provide a data input buffer of a digital synchronous DRAM that enables high-speed operation.

1 is a block diagram showing a buffer structure for a write operation of a general digital synchronous DRAM,

2a to 2d are pulse timing diagrams of FIG.

3 is a block diagram showing a data input buffer structure of a DL synchronous DRAM according to the present invention;

4A to 4H are pulse timing diagrams for FIG.

* Explanation of symbols for main parts of the drawings

10: input buffer 20: rising data input buffer

30: polling data input buffer 40: signal delay unit

50: switch circuit 60: even data input / output buffer

70: odd data input / output buffer

In order to achieve the object as described above, the present invention, a rising data input buffer 20 for inputting data input through the input buffer 10 in synchronization with the rising edge of the clock; A polling data input buffer 30 for inputting data input through the input buffer 10 in synchronization with a polling edge of a clock; A signal delay unit (40) for delaying a predetermined time in order to synchronize the output of the rising data input buffer (20) with a falling edge of a clock; Switching the even and odd data output from the signal delay unit 40 and the polling data input buffer 30 to the even / output buffer and the odd data into the input / output buffer according to the control signal SO_SEB. Switch circuit section 50; An even data input / output buffer 60 for transferring the even data switched from the switch circuit unit to the global input / output line; And an odd data input / output buffer 70 for transferring the odd data switched from the switch circuit unit to the global input / output line.

The operation principle according to the present invention will be described in detail as follows.

In the DDR Synchronous DRAM (DDR SDRAM), a single data strobing signal (dinstb) must be displayed to obtain two pieces of even data and two pieces of odd data. ) And the time at which the data strobing signal dinstb floats to the odd data input / output buffer 70 is the second data as shown in (a) of FIG. This is when data enters the falling data input buffer 30 as shown in (d).

Therefore, data entering the rising data input buffer 20 is actually passed to the global input / output line at the same time as the data input to the polling data input buffer 30 after half a clock, which means that the data input is an even data ( It does not matter whether it starts with even data or odd data.

Therefore, no problem occurs even if the output r1 of the rising data input buffer 20 as shown in FIG.

Synchronizing the output r1 of the rising data input buffer 20 with the clock signal rising_dinclk and the output f2 of the polling data input buffer 30 with the clock as shown in FIG. The falling_dinclk signal, which is a signal created for the purpose, is a clock generated by sensing a rising edge and a falling edge of the data strobe signal DS, respectively.

Here, the data strobe signal DS is accurately synchronized with a clock.

Accordingly, the output r1 of the rising data input buffer 20 is exactly synchronized with the rising edge of the clock as shown in FIG. 4B, and the output f2 of the polling data input buffer 30 is shown in FIG. This is exactly synchronized to the falling edge of the clock.

At this time, as shown in (c) of FIG. 4, the signal delay unit 40 delays the signal r1 output from the rising data input buffer 20 and converts the delayed signal r2 according to the falling_dinclk input of the clock. Output in synchronization with the falling edge.

In this case, the data width of the data strobe signal dinstb increases from 0.45tCLK to almost 1CLK.

As described in detail above, the present invention comprises a data input buffer that receives data during a write operation of a digital synchronous DRAM, comprising a rising data input buffer and a falling data input buffer. By synchronizing the two data coming from the input buffer, you can increase the timing margin of the strobing signal that passes data from the data input / output buffer to the global input / output lines to enable high-speed operation. It can be effective.

Preferred embodiments of the present invention are disclosed for purposes of illustration, and those skilled in the art will be able to make various modifications, changes, additions, and the like within the spirit and scope of the present invention, and such modifications and changes should be regarded as belonging to the following claims. something to do.

Claims (6)

A rising data input buffer configured to input data input through the input buffer in synchronization with the rising edge of the clock; A polling data input buffer configured to input data input through the input buffer in synchronization with a polling edge of a clock; A signal delay unit configured to delay a predetermined time to synchronize an output of the rising data input buffer to a falling edge of a clock; A switch circuit unit for switching even and odd data output from the signal delay unit and the polling data input buffer to an even data input / output buffer and an odd data input / output buffer according to a control signal; An even data input / output buffer configured to carry even data switched from the switch circuit unit to a global input / output line; And An odd data input / output buffer configured to carry odd data switched from the switch circuit unit to a global input / output line; Data input buffer of the DL synchronous DRAM. The method of claim 1, The input buffer is A data input buffer of a digital synchronous DRAM, which is output to a rising data input buffer or a falling data input buffer irrespective of an even / odd number of input data. The method of claim 1, The signal rising_dinclk generated to synchronize the output r1 of the rising data input buffer with the rising edge of the clock is A data input buffer of a digital synchronous DRAM, which is a clock signal generated by detecting a rising edge of a data strobe signal DS. The method of claim 1, The signal falling_dinclk generated to synchronize the output f2 of the polling data input buffer with the falling edge of the clock, A data input buffer of a digital synchronous DRAM, wherein the clock signal is generated by detecting a falling edge of the data strobe signal DS. The method according to claim 3 or 4, The data strobe signal DS, A data input buffer of a digital synchronous DRAM, which is synchronized with a clock accurately. The method of claim 1, The signal r2 output from the signal delay unit is And an output signal (r1) from the rising data input buffer is output in synchronization with a falling data input clock (falling_dinclk).