KR100336790B1 - Address decoding circuit for semiconductor memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection circuit. In the related art, a count address (caddress) is transmitted by the rising edge of the first clock (YCLK1), and the address is raised by the rising edge of the Y address enable signal (YAE). Since the comparison unit starts the address comparison operation, the Y decode enable signal YSE, which enables the Y decoder, is delayed by a delay compared to the Y address enable signal YEA, so that the address selection signal ( YSi) or the redundancy address selection signal RYSi is delayed. Accordingly, the present invention speeds up the count address (caddress) by adjusting the address and command setup time, and compares it in an asynchronous manner in the address comparison unit, thereby speeding up the timing of generation of the Y decode enable signal (YSE). Since the Y decoder or the RYS driver is enabled at the rising edge of the Y address enable signal YAE, it is possible to perform a faster decoding operation than the conventional method.

Description

ADDRESS DECODING CIRCUIT FOR SEMICONDUCTOR MEMORY

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory. In particular, a semiconductor memory which speeds up the Y address in the memory by using address setup timing to eliminate the decoding operation delay caused by the conventional redundancy address comparison can speed up the Y address decoding operation. To an address decoding circuit.

1 is a block diagram showing a configuration of a conventional Y address decoding circuit, comprising: a clock buffer 10 for receiving and buffering an external clock CLK and outputting an internal clock iCLK as shown therein; A Y address buffer 30 for buffering and outputting an external address in synchronization with the internal clock iCLK; A Y clock generator 20 for receiving a command and interpreting the same to generate clock signals YCLK1 and YCLK2 synchronized to the internal clock iCLK; A Y address buffer 30 that receives an external address and buffers the external address to output an iaddress; A Y address enable generation unit (40) for outputting a Y address enable signal (YAE) by the clocks (YCLK1, YCLK2); A Y address counter (50) for counting and outputting an internal address (iaddress) by the clocks YCLK1 and YCLK2; An address comparator 60 which determines whether the count address caddress is a redundant repair address while the Y address enable signal YAE is logic high; A Y decoder 70 which performs a decoding operation by a count address (caddress); When the result of the determination of the address comparison unit 60 is a redundancy repair address, the RYS driver 80 outputs a redundancy address. The command decoder 90, which is omitted, is a command input from an external memory SDRAM. ), And the operation of the prior art configured as described above will now be described with reference to the timing diagram of FIG.

Based on the rising edge of the clock CLK in FIG. 2, as shown in (e) and (g), an external command such as read or write and an external address hold the up time tCS and tDS. It is input while satisfying the times tCH and tDH.

At this time, the external clock CLK is output as the internal clock signal iCLK delayed through the clock buffer 10 and applied to the Y clock generator 20 and the Y address buffer 30.

The Y clock generator 20 interprets the command to generate clock signals YCLK1 and YCLK2 synchronized to the internal clock iCLK when the command is read or written.

The first clock YCLK1 only occurs at the first clock of the read or write command, after which it does not occur.

The second clock YCLK2 is continuously generated during the burst period from the next clock after the first clock YCLK1 occurs.

At this time, the control of the burst length is determined by the mode register up before the read or write command, and the control signal is applied to the Y clock generator 20.

The internal address (iaddress) is delayed and delivered by the external address (Y address buffer 30), and the internal clock (iCLK) is latched in the Y address buffer 30 during the interval where the internal clock (iCLK) is logic high. The latched address is held until this logic low.

As shown in (e) to (i) of FIG.

The first and second clocks YCLK1 and YCLK2 and the internal address iaddress are transferred to the Y address counter 50 to generate a count address caddress which is a counted address.

The count address caddress is enabled by the rising edges of the first and second clocks YCLK1 and YCLK2. The count address caddress is enabled by the rising edges of the first clock YCLK1 as shown in FIGS. iaddress is transferred to the count address caddress and maintained for one clock period and counted to the next address by the rising edge of the second clock YCLK2.

The Y address enable generation unit 40 is adjusted to be later than the enable time of the count address (caddress) after logically cutting the first and second clocks YCLK1 and YCLK2 as shown in FIG. 2 (i) (j). Output the signal YAE.

The generated count address (caddress) and the Y address enable signal (YAE) are transmitted to the address comparison unit 60, and the count address (caddress) is a redundant repair address while the Y address enable signal (YAE) is logic high. It is determined whether or not.

If the count address caddress is not a repair address, the Y decode enable signal YSE is generated as a logic high pulse, and the redundancy Y decode enable signal RYSEi keeps a logic low.

The Y decode enable signal YSE is transmitted to the Y decoder 70 to enable the decoding operation by the count address caddress, and the final output YSi (i = 0 to n) is selected as the high pulse.

If the count address (caddress) is a repair address, the Y decode enable signal YSE remains at a logic low, and the redundancy Y decode enable signal RYSEi becomes a logic high and is transferred to the RYS driver 80. The redundancy address selection signal RYSi (i = 0 to m) is selected as a high pulse in synchronization with the delayed signal YAED of the Y address enable signal YAE as much as the address comparison operation performs the address comparison operation. .

3 is a block diagram showing the detailed configuration of the Y address counter 50, and FIG. 4 is a block diagram showing the detailed configuration of each counter CE (i) in FIG.

At this time, the Y address counter 50 of FIG. 3 is connected to the plurality of counters CE (i) in parallel and receives and processes the carry output from the carry generation unit 51, which is similar to a general operation. It will be omitted.

Next, FIGS. 5 and 6 show detailed configurations of the latches LT1, LT2, and LT3 constituting the counter CE (i) in FIG. 4. .

First, when a command (read or write) is input from the outside of the memory, it is decoded by the command decoder 90 to generate a low to high pulse.

In this case, the command is inputted before the clock CLK, which is called a setup time. The internal clock iCLK is a clock generated by the external clock CLK through the clock buffer 10, and the first and second clocks YCLK1, YCLK2 is generated in synchronization with the internal clock iCLK.

At this time, an external address is also input in advance of the clock CLK, which must also be preceded to satisfy the setup time.

Next, the internal address (iaddress) is an address whose external address is input through the Y address buffer 30 and controlled by the internal clock iCLK so as to cause the internal clock iCLK to transition from low to high. It is latched in the address buffer 30 to maintain a valid address until the moment when the internal clock iCLK transitions from high to low.

The generated internal address (iaddress) and the first and second clocks YCLK1 and YCLK2 are transferred to the internal counter CE (i) of the Y address counter 50. Accordingly, the internal address iaddress and the first and second clocks YCLK1 and YCLK2 are transmitted to the internal counter CE (i). As soon as one clock YCLK1 transitions from low to high, the input internal address (iaddress) is latched to the upper latch (LT1) and transferred to the count address (caddress) through the latch (LT3). caddress is maintained until the second clock YCLK2 transitions from low to high.

Here, the signals input and output to the counter are input and output through the counter input and output terminals (Cin, Cout).

Next, when the second clock YCLK2 transitions from low to high in a cycle, the signal G or GB of the latch LT3 selected by the input signal Cin generated by the counting operation is latched in the lower latch LT2. At the same time, it is transferred to the count address caddress through the latch LT3.

The count address output at this time is an address counted in the memory.

Therefore, the count address caddress is output at the moment when the first and second clocks YCLK1 and YCLK2 transition from low to high. In the operation of the memory SDRAM, the Y address enable signal YAE must follow the count address caddress.

Only when the time margin shown in the timing diagram of FIG. 2 is satisfied, the selection signal YS of the address to be selected can be enabled.

That is, the speed of the count address caddress is the speed of the address selection signal YS and affects the performance of the memory (SDRAM) speed.

However, in the above conventional technique, the count address caddress is transmitted by the rising edge of the first clock YCLK1, and the address comparison operation is started in the address comparison section by the rising edge of the Y address enable signal YAE. Therefore, the Y decode enable signal YSE, which enables the Y decoder, is delayed by a delay compared to the Y address enable signal YAE by a delay that is required to perform the comparison operation. Thus, the address selection signal YSi or the redundancy address selection signal ( There was a problem that the selection of RYSi) is delayed.

Accordingly, the present invention was created to solve the above-mentioned conventional problem, and eliminates the decoding operation delay caused by the redundancy address comparison, that is, by adjusting the address and command setup time to adjust the count address (caddress). It is an object of the present invention to provide an address decoding circuit of a semiconductor memory that speeds up a Y address decoding operation.

1 is a block diagram showing the configuration of a conventional Y address decoding circuit.

2 is an operation timing diagram in FIG. 1;

3 is a block diagram showing a detailed configuration of a Y address counter in FIG.

4 is a block diagram showing a detailed configuration of each counter circuit in FIG.

FIG. 5 is a detailed circuit diagram of the latch 1 (LT1, LT2) constituting the counter circuit in FIG.

FIG. 6 is a detailed circuit diagram of latch 2 LT3 constituting a counter circuit in FIG.

7 is a block diagram showing a configuration of a Y address decoding circuit according to the present invention;

8 is an operation timing diagram in FIG.

9 is a block diagram showing a detailed configuration of each counter circuit applied to the Y address counter of FIG.

*** Description of the symbols for the main parts of the drawings ***

100: Y address counter 200: count address output section

LT10: latch SW10: switching part

The present invention for achieving the above object is a command decoder for decoding and outputting an external command; A clock buffer which buffers the external clock CLK and outputs the internal clock iCLK; A Y clock generator which receives a command and generates clock signals YCLK1 and YCLK2 synchronized with the internal clock iCLK; A Y address buffer that buffers an external address and outputs an internal address; A Y address enable generation unit for outputting a Y address enable signal (YAE) by the clocks YCLK1 and YCLK2; An address comparison section that determines whether the count address (caddress) is a redundant repair address; A Y decoder for performing a decoding operation by the count address; A semiconductor memory including a RYS driver for outputting a redundancy address when a result of a redundancy repair address is determined as the result of the address comparator, wherein a command (RWC), a clock signal (YCLK1, YCLK2) output from an instruction decoder, and an internal address are received. And a Y address counter for selectively outputting a count address.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 7, the present invention is different from the prior art in that the present invention is designed to speed up the count address (caddress) output from the Y address counter 100 and output from the Y enable enable unit 40. FIG. The Y address enable signal YAE is applied to the address comparison unit 60 and the RYS driver 80 without being delayed.

In order to speed up the count address (caddress) in this manner, it is possible to improve the configuration of each counter CE (i) constituting the Y address counter 100 as shown in FIG.

That is, the command RWC output from the command decoder 90 is input to the counter CE (i) as shown in FIG. 4, and the Y address pass signal YAPS is output by the first clock YCLK1. It is achieved by further comprising a count address output unit 200 for selecting any one of the output of the latch (LT1 or LT2) to output to the count address (caddress).

That is, the operation of the above configuration will be described. Once the Y address path selection signal YAPS is logic high, the switch s1 is turned on in FIG. 9, so that the output G1 of the latch 1 LT1 is counted. Is output.

Next, when the Y address path select signal YAPS goes low, the switch s2 in FIG. 9 is turned on so as to change the path so that the output G2 of the latch 1 LT2 is outputted to the count address.

Accordingly, as illustrated in FIG. 8, the internal address iaddress is transferred during the low period of the first and second clocks YCLK1 and YCLK2, and the first and second clocks YCLK1 and YCLK2 are respectively transferred. Since the latch is performed during the high-in period, the Y address setup time can be used faster than before.

An operation feature of the present invention configured as described above is to output an internal address (iaddress) as a count address (caddress) during a period in which the first clock (YCLK1) is a logic low, and internally while the first clock (YCLK1) is logic high. The address (iaddress) is latched and output as a count address (caddress).

Accordingly, the count address (caddress) is directly transmitted to the address comparison unit 60 and the Y decoder 70, the address comparison operation asynchronously occurs in the address comparison unit 60, the Y decode enable signal (YSE) Alternatively, a redundancy Y decode enable signal RYSEi is generated.

The Y decode enable signal YSE and the redundancy Y decode enable signal RYSEi generated as described above are transmitted to the RYS driver 80 before the Y address enable signal YAE.

Accordingly, the RYS driver 80 is enabled at the rising edge of the Y address enable signal YAE to output the address selection signal YSi or the redundancy address selection signal RYSi.

In other words, the signal RWC generated by the command setup in the command decoder unit 90 is applied to the counter CE (i) inside the Y address counter 100 according to the present invention so that each latch LT1, LT2 Selects output signals G1 and G2 and outputs them to a count address caddress.

The output signals G1 and G2 are selected by the Y address path selection signal YAPS, and output a signal G1 when the logic is high, and output the signal G2 when the logic is low.

At this time, the Y address path select signal YAPS is generated when the command signal RWC passes through the latch LT1, and the first clock YCLK1 is in a logic low state. The Y address pass select signal YAPS is latched to maintain logic high until the first clock YCLK1 transitions from logic high to logic low again.

While the Y address path selection signal YAPS is logic high, the previously input internal address iaddress is output as the signal G1 through the upper latch LT1 and then transferred to the count address caddress. You can quickly determine the count address (caddress). That is, the enable time of the count address caddress is the moment when the Y address pass select signal YAPS transitions from a logic low to a logic high.

On the other hand, when the first clock YCLK1 transitions high from a logic low, the signal G1 is applied to the input terminal D1 of the latch LT3 and output to the output terminals G and GB.

Here, the output terminal G becomes the output Cout of the counter CE (i), becomes an input Cin by the carry of the counter, and selectively controls the signal output from the output terminals G and GB.

Accordingly, when the signal of the output terminals G and GB of the latch LT3 is input to the input terminal D of the lower latch LT2 and the first clock YCLK1 transitions from logic high to logic low, the latch LT3 is external. Block the input and keep it current.

The lower latch LT2 outputs a signal of the output terminals G and GB transmitted from the latch LT3 through the output terminal G2 while the latch path is turned on while the second clock YCLK2 is logic low. When the clock YCLK2 transitions from a logic low to a logic high, the upper latch LT1 again latches a signal of the output terminal G2 and maintains it until the second clock YCLK2 transitions back to a logic low.

The signal of the output terminal G2 thus transferred is transferred to the count address caddress at the time when the Y address pass select signal YAPS transitions from logic high to logic low, which is an address counted inside the memory SDRAM.

In other words, the transfer time of the counting address in the prior art is the high transition time of the second clock YCLK2, and the transfer time of the counting address of the present technology is the logical low transition time of the Y address path selection signal YAPS. The point has become faster.

As described above, in the address decoding circuit of the semiconductor memory of the present invention, the count address (caddress) is faster than that of the conventional method and asynchronously compared by the address comparison unit, so that the timing of generating the Y decode enable signal YSE is generated. This becomes faster and finally enables the Y decoder or the RYS driver at the rising edge of the Y address enable signal YAE, so that a faster decoding operation can be performed than in the conventional method.

Claims (3)

A command decoder for decoding and outputting an external command; A clock buffer which buffers the external clock CLK and outputs the internal clock iCLK; A Y clock generator which receives a command and generates clock signals YCLK1 and YCLK2 synchronized with the internal clock iCLK; A Y address buffer that buffers an external address and outputs an internal address; A Y address enable generation unit for outputting a Y address enable signal (YAE) by the clocks YCLK1 and YCLK2; An address comparison section that determines whether the count address (caddress) is a redundant repair address; A Y decoder for performing a decoding operation by the count address; A semiconductor memory including a RYS driver for outputting a redundancy address when a result of a redundancy repair address is determined as the result of the address comparison unit. And an Y address counter for selectively outputting a count address. The Y address counter is a command output from a command decoder to a counter circuit configured to receive and process a carry output from the carry generation unit 51 by connecting a plurality of counters CE (i) in parallel. A count address output that receives the RWC, outputs the Y address pass signal YAPS by the first clock YCLK1, selects one of the outputs of the latch LT1 or LT2, and outputs the count address caddress. An address decoding circuit of a semiconductor memory, characterized in that it further comprises a section. The counter of claim 2, wherein the count address output unit receives a command (RWC) output from the command decoder to receive any one of the latches (LT1, LT2) output (G1, G2) of the counter circuit by the first clock (YCLK1). A latch LT10 for outputting a Y address path select signal YAPS for selecting and outputting to a count address; And a switching unit (SW10) for switching by the Y address path selection signal (YAPS) to output the output signals (G1, G2) of the latches (LT1, LT2).