KR0184457B1 - Clock synchronizing circuit of semiconductor memory - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION The invention described in the claims belongs to: a clock synchronization circuit of a semiconductor memory.

2. Technical problem to be solved by the present invention: Provides a clock synchronization circuit of a synchronous semiconductor memory that can improve the racing margin required to prevent malfunction.

3. Summary of the Invention A clock synchronizing circuit of a semiconductor memory having first and second blocking portions connected to each other via a decoder, the clock synchronization circuit comprising: controlling the second blocking portion to be on or off and turning on the first blocking portion; A delay unit for generating a second clock signal to control the state; And a buffer unit coupled between the delay unit and the receiver unit for receiving an input clock and providing a first clock signal for controlling the first block unit to an off state, the buffer unit providing the first block unit and the delay unit.

4. Important use of the invention: clock synchronization circuit of semiconductor memory.

Description

Clock Synchronization Circuit of Semiconductor Memory

1 is a block diagram of a clock synchronizing circuit according to the prior art.

2 is a block diagram of a clock synchronizing circuit according to the present invention.

3 is a detailed circuit diagram of a first blocking part of FIG.

4 is a detailed circuit diagram of a first blocking part of FIG. 2.

5 is an operation timing diagram of signals according to FIGS. 1 and 2.

6 is a simulation waveform diagram respectively obtained from a circuit according to the present invention and the prior art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronizing circuit of a semiconductor memory, and more particularly to a clock synchronizing circuit of a synchronous semiconductor memory capable of improving the racing margin required for preventing malfunction.

In general, in order to prevent a malfunction in a synchronous semiconductor memory requiring ultra-fast operation, the racing margin of the clock synchronization circuit should be excellent. Here, the racing margin means a margin between clock signals generated at the leading latch and the rear latch in the clock synchronization circuit of the semiconductor memory. It is known that the racing margin becomes more difficult as the operation of the semiconductor memory becomes faster. In particular, the racing margin at the negative edge of the clock signal is very important because it has a large effect on the malfunction.

Typically, as a method of securing a racing margin to prevent a malfunction, there are a method using a short pulse and a method in which the time delay between the output latch signals of the first latch and the rear latch is smaller than the delay of the address decoder. However, the method using the short pulse is inferior to the method using the latter time delay due to the problem of considering the pulse fluctuation of the short pulse generator and the difficulty of securing the pulse width at a very high speed.

FIG. 1 is a block diagram of a conventional clock synchronizing circuit applied to a method of making a time delay between the output latch signals of the first latch and the rear latch smaller than the delay of an address decoder to secure a racing margin. Referring to FIG. 1, the clock synchronization circuit includes first and second receivers 100 and 110, first and second blocking units 120 and 160, a decoder 140, a buffer 130, and a delayer 150. have. The first receiver 100 receives the address XAi like the waveform 5f of FIG. 5 and outputs an output signal GTL and the inverted output signal GTLB like the waveform 5g of FIG. 5 after a predetermined time delay. The first blocking unit 120 blocks the output signal GTL and the inverted output signal GTLB in response to the signal K1B such as 5c of FIG. 5 provided from the buffer 130 to provide the signals AIF and AIFB as outputs. The decoder 140 receives this and generates the waveforms 5h and 5i of FIG. 5 as decoding outputs.

The second blocking unit 160 blocks the output of the decoder 140 in response to the signal K2 such as waveform 5d of FIG. 5 provided from the delayer 150 to output the waveforms 5j and k of FIG. The signals OMRD (e) and OMRD (d) are generated as final output signals. Accordingly, it can be seen that FIG. 1 is divided into the blocking clock path and the address decoding path.

In FIG. 1, when the first blocking unit 120 is implemented by ECL logic, the first blocking unit 120 may be configured as 3a of FIG. 3, and may be configured as 3b when implemented by CMOS logic.

In the conventional circuit having the above configuration, the racing margin is a time delay between the signal K1B provided to the first blocking unit 120 and the signal K2 provided to the second blocking unit 160, that is, in FIG. 5. A time delay of the decoder 140 at the rear end of the first blocking unit 120, i.e., τ2 = tau2 'in FIG. In this case, when τ1'τ2 'is reached, the first and second blocking parts 120 and 160 are simultaneously turned on at the negative clock edge so that the signal PA (d) represented by waveform 5i of FIG. 5 transitions from low L to high H. Cause malfunction. As a result, the output signal OMRD (d) of the second blocking unit 160 is provided as a high H pulse, thereby causing racing, that is, malfunction. In normal cases, the logic of the signal OMRD (d) should appear at a low L level.

Therefore, in the conventional circuit, as a method for reducing the time delay τ1 'between the clock signals K1B and K2 to be smaller than the delay τ2' of the address decoder, the delay unit 150 that is responsible for the signal K2 delay for improving the set-up time There is a way to add, there is a burden to always consider the racing margin when adding the delay 150. After all, the limiting factor in improving the speed and setup time of the XAi decoding pass is racing. In addition, since the blocking clock path and the decoding path are different in terms of process variation, it can be seen that τ1 'and τ2' are each changed, so that the racing margin is unstable.

It is therefore an object of the present invention to provide a clock synchronizing circuit of a semiconductor memory which can solve the above-mentioned conventional problems.

Another object of the present invention is to provide a clock synchronizing circuit of a racing free semiconductor memory.

Still another object of the present invention is to provide a clock synchronization circuit and a racing margin securing method of a semiconductor memory capable of effectively controlling speed up and setup time of a decoder.

Another object of the present invention is to provide a clock synchronization circuit and a method of securing a margin of a semiconductor memory capable of preventing a malfunction due to a change in a process.

SUMMARY OF THE INVENTION In order to achieve the above objects, in the present invention, a clock synchronization circuit of a semiconductor memory having first and second blocking units connected to each other via a decoder is provided. The first blocking unit controls the second blocking unit to be in an on or off state. A delay unit for generating a second clock signal for controlling the unit to an on state; And a buffer unit coupled between the delay unit and a receiving unit for receiving an input clock and providing a first clock signal for controlling the first blocking unit to an off state, the buffer unit providing the first blocking unit and the delay unit. Provide a clock synchronization circuit.

Hereinafter, a clock synchronization circuit and a method of securing a racing margin of a semiconductor memory according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings. Like reference numerals in the accompanying drawings should be understood as elements having equivalent functions. In the following description, for example, the description is limited and detailed to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In addition, the basic physical properties and operations of components of well-known semiconductor memory circuits are not described in detail in order not to obscure the present invention.

A block diagram of the clock synchronizing circuit according to the present invention is shown in FIG. 4 is a detailed circuit diagram of the first blocking unit 220 in FIG. 2.

Referring to FIG. 2, a major difference compared to FIG. 1, which is a circuit of the related art, is the configuration and operation of the first blocking unit 220 to determine the hold time. That is, in the prior art, the first blocking unit 120 is turned on / off by the clock signal K1B. However, in the present invention, the off operation of the first blocking unit 220 is performed by the clock signal K1B, and the on operation is the clock signal. Performed by K2B.

Therefore, in the related art, the output signal OMRD (d) of the second blocking unit 160 is provided as a high H pulse, thereby causing a malfunction. Goes low and a normal signal is obtained.

In FIG. 2, the second blocking unit 160 is turned on (K2 = H) / off (K2 = L) according to the high or low level of the signal K2 generated by the delay unit 150, and the first blocking unit The off operation of 220 is determined by the signal K1B (when L) generated in the buffer 130 and the on operation is determined by the signal K2B (high H) of the delayer 150. In this case, since there is no time delay between the signals K2 and K2B as shown in waveforms 5d and 5e of FIG. 5, the first blocking unit 220 is turned on simultaneously with the off operation of the second blocking unit 160. Race free can be implemented. As a result, the delay tau 2 of the decoder 140 of FIG. 2 is always greater than the clock delay t (K2 to K2B). Therefore, even when speeding up the decoder delay or adjusting the delay of K2 (or K2B) to improve the setup time, the race free is realized, and the racing margin is secured by the variation.

In order to accomplish this, FIG. 4 is a detailed circuit diagram of the first blocking unit 220 of the second diagram. In FIG. 4, when the first blocking unit 220 is implemented with ECL logic, the first blocking unit 220 is configured as 4a. When implemented with CMOS logic, the first blocking unit 220 is configured as 4b. In FIG. 4A and FIG. 4B, unlike FIG. 3, it can be seen that the NMOS transistor M2 is further connected to the NMOS transistor M1 in series, and the inverter 11 and the PMOS transistor P2 are further connected. K1B (off-clock) is applied to the gate of the transistor M1, and K2B (on-clock) is applied to the gate of the M2. In FIG. 4, when the first blocking part 220 is turned off, the transistor M1 is turned off because K1B becomes low L before K2B. That is, when OFF, the operation is controlled by K1B. When ON, the M1 and M2 are simultaneously turned on, and the on time is finally determined by the signal K2B. At this time, since the M1 and M2 are turned on, the first blocking part 220 is turned on.

6 shows a simulation waveform diagram respectively obtained from a circuit according to the present invention and the prior art. Here, 6a is in accordance with the present invention, 6b is a waveform diagram according to the prior art. In the conventional circuit, a malfunction similar to the symbol B1 in the sixth b occurs, but in the sixth a race does not occur as in the symbol A1.

Therefore, in the present invention, the above objects are achieved by common use of the signal for turning on / off the second blocking portion as the on / off signal for the first blocking portion.

According to the present invention described above, by providing a clock synchronization circuit of a racing-free semiconductor memory, it is possible to effectively control the speed-up and setup time of the decoder, and also to prevent malfunction due to process changes. There is this.

Claims (3)

A clock synchronization circuit of a semiconductor memory having first and second blocking parts connected to each other via a decoder, comprising: a second clock signal for controlling the second blocking part to be in an on or off state and controlling the first blocking part to be in an on state A delay unit for generating a; And a buffer unit coupled between the delay unit and a receiving unit for receiving an input clock and providing a first clock signal to the first blocking unit and the delay unit to control the first blocking unit in an off state. A clock synchronization circuit of a semiconductor memory having first and second blocking portions connected to each other via a decoder, comprising: a second clock signal for controlling the second blocking portion to be turned off or on and controlling the first blocking portion to be turned off; A delay unit for generating a; And a buffer unit coupled between the delay unit and a receiver for receiving an input clock and generating a first clock signal for controlling the first blocking unit in an on state. The circuit of claim 1, wherein the first blocking unit has an input unit configured to receive the second clock signal.