JP2701717B2 - Pulse synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse synchronizing circuit for synchronizing a pulse synchronized with a first clock to a second pulse, and in particular, a cycle of the second clock is longer than a cycle of the first clock. A pulse synchronization circuit.

[0002]

[Prior art]

[Explanation of Symbols] In the following description, the first clock and the second clock are represented by tn and Tn, respectively.
Further, the cycle of the first clock and the cycle of the second clock are represented by t and T, respectively.

Next, a synchronous circuit and a differentiating circuit will be described.

[Synchronous Circuit] In the present specification, the synchronous circuit means a circuit that synchronizes a change point of an asynchronous input signal with a predetermined clock.

Referring to FIG. 6, a synchronization circuit 20 can be composed of, for example, two D flip-flops 21 and 22 connected in series. The D flip-flops 21 and 22 hold and output the input terminal D at the rising edge of the clock CLK. The details of the D flip-flop and the JK flip-flop to be described later are described in pages 288 to 289 of "Electronic Information and Communication Handbook" (published on March 30, 1988) published by Ohmsha, edited by the Institute of Electronics, Information and Communication Engineers. Is described in

Referring to FIG. 7, A and B, which are the changing points of an input signal 92 asynchronous to a clock 91, are synchronized by a synchronization circuit 20 and output as an output signal 94. Specifically, the rise at A and the fall at B have moved to t3 and t6, respectively. t3 and t6 are timings of the rising edge of the clock 1.

[0007] In C and D of FIG.
The input signal 92 changes at the timing of the rise of “1”. At this time, the intermediate output 93, which is the output of the D flip-flop 21, becomes unstable. However, the unstable change of the intermediate output 93 is caused by the D flip-flop 22
Is absorbed by Therefore, the output signal 94 can maintain a normal waveform.

In the synchronous circuit 20 shown in FIG. 6, since two D flip-flops are connected in series, the output signal 94
Is delayed. This delay is called "synchronization loss". The average value of the synchronization loss in the synchronization circuit 20 of FIG. 6 is about 1.5t.

[Differentiation circuit] In this specification, the differentiation circuit is
This is a circuit for setting the pulse width of a pulse signal having an indefinite length to 1t width, which is one cycle of a clock. Hereinafter, performing this operation is simply referred to as “differentiating”.

Referring to FIG. 8, the differentiating circuit 30 can be composed of, for example, a D flip-flop 31 and an AND circuit 32.

Referring to FIG. 9, input signal 96 is at logic "1" from time t2 to time t5. On the other hand, the output signal 98 of the differentiating circuit 30 is at logic "1" only during 1t between times t2 and t3.

[Prior Art] Referring to FIG. 10, a pulse synchronization circuit using only a synchronization circuit is composed of a synchronization circuit 20 and a differentiation circuit 30.

Referring to FIG. 11, the synchronization circuit 20 includes:
An input pulse 3 synchronized with the first clock 1 and a second clock 2 are input. The synchronization circuit 20 synchronizes the input pulse 3 with the second clock 2 and outputs it as a synchronization output 5. The differentiating circuit 30 sets the pulse width of the synchronous output 5 to one clock and outputs it as an output pulse 6.

However, in the case of FIG. 11, the first clock 1 is shorter than the second clock 2. Therefore, at time t2
The input pulse 3 generated at t3 is not reflected on the synchronous output 5. This is because the second clock 2 does not rise between times t2 and t3.

Referring to FIG. 12, in order to prevent such inconvenience, an extension circuit 50 is provided in the conventional pulse synchronization circuit.

The extension circuit 50 extends the pulse width of the input pulse 3 by a predetermined length. Referring to FIG. 13, the pulse of the extension output 9, which is the output of the extension circuit 50, is output at time t
It lasts between 2 and t4. Then, between the times t2 and t4, the rising timing of the second clock 2 is T
2 is included. Therefore, the synchronization circuit 20 operates at the time T2
, A synchronous output 5 corresponding to the input pulse 3 is output. The differentiating circuit 30 to which the synchronous output 5 has been input outputs an output pulse 6.

Referring to FIG. 14, the pulse synchronizing circuit shown in FIG. 12 includes D flip-flops 21 and 22 forming a synchronizing circuit 20, a D flip-flop 31 and an AND circuit 32 forming a differentiating circuit 30, an extension circuit 50, a D flip-flop 51, a D flip-flop 52 and an OR circuit 53.
The extension circuit 50 has a function of extending the input pulse 3 by 1t.

Referring to FIG. 15, in this case, T = 1.
It is set to 5t. Therefore, the extension output 9 output from the extension circuit 50 is always detected by the synchronization circuit 20.

For example, referring to FIG.
When there is an input pulse 3 during t5, the pulse of the extended output 9 is connected between time 4 and t6. Therefore, the synchronous output 5
Outputs a synchronous output 5 at time T5. The synchronous output 5 is differentiated by the differentiating circuit 30 and output as an output pulse 6.

[0020]

However, in the above-mentioned prior art, if the period of the first clock 1 or the second clock 2 is changed for a performance test, a malfunction may occur. There was a point.

For example, referring to FIG. 16, in this case,
T = 2.5t is set. Therefore, from time t4
The pulse of the extension output 9 generated at t6 is not detected by the synchronization circuit 20. Therefore, the output pulse 6 is not output.
This is beyond the range that the extension circuit 50 can handle,
This is because the period T of the clock 2 has been extended. A similar malfunction occurs when the cycle of the first clock 1 is shortened.

[0022] To solve the problems described above, the pulse synchronization circuit of the present invention, the said first clock inputs the input pulse synchronized with the first clock and the first clock
Synchronize and outputs the held output while holding the input pulse, a holding circuit which is reset by a reset signal, the holding power and the second said holding output second inputs the clock holding circuit outputs of a first synchronization circuit for outputting a synchronous output in synchronization with the clock, the first synchronization circuit is the synchronous output and the second clock input pulse width of the synchronous output the second to the output A differentiating circuit for outputting as an output pulse having a width of one cycle of the clock;
A second synchronization circuit that inputs the synchronization output and the first clock, synchronizes the synchronization output with the first clock, and outputs the same as the reset signal.

[0023]

Next, the present invention will be described with reference to the drawings.

[Configuration of First Embodiment] Referring to FIG. 1, a pulse synchronizing circuit according to a first embodiment of the present invention
A holding circuit 10 for holding the input pulse 3 synchronized with the clock 1 and outputting it as a holding output 4, a synchronizing circuit 20 for synchronizing the holding output 4 with the second clock 2 and outputting the same as a synchronization output 5, and a synchronizing output 5 It has a differentiating circuit 30 for differentiating and outputting as an output pulse 6, and a synchronizing circuit 40 for synchronizing the synchronous output 5 with the first clock 1 and outputting as a reset signal 7. The reset signal 7 output from the synchronization circuit 40 is
The holding circuit 10 is reset.

Referring to FIG. 2, the holding circuit 10 of FIG.
It is composed of a JK flip-flop 11. The JK flip-flop 11 outputs the first clock 1 to the clock terminal,
Input pulse 3 to the J terminal, reset signal 7 to the K terminal,
Enter each. The JK flip-flop 11
Hold output 4 is set to logic "1" at the timing of the rising edge of clock 1. This state is maintained until the reset signal 7 is set to logic "1".

The synchronization circuit 20 comprises D flip-flops 21 and 22 connected in series. Synchronous circuit 2
The configuration and operation of 0 are the same as those of FIG. 6 described above.

The differentiating circuit 30 includes a D flip-flop 31
And an AND circuit 32. The configuration and operation of the differentiating circuit 30 are the same as those in FIG.

The synchronization circuit 40 includes a D flip-flop 41
And a D flip-flop 42. The operation of the synchronization circuit 40 is the same as that of FIG. The reset signal 7, which is the output of the synchronization circuit 40, is connected to the K terminal of the JK flip-flop 11.

[Operation of First Embodiment] Next, the operation of this embodiment will be described with reference to the drawings.

Referring to FIG. 3, at time t1, input pulse 3 goes to logic "1".

At time t2, JK flip-flop 11 holds logic "1" which is the value of input pulse 3,
Output to holding output 4. JK flip-flop 11
Until the logic "1" is input to the K terminal, the logic "1" is output as the hold output 4.

At time T3, the synchronization circuit 20 changes the synchronization output 5 to logic "1". This means that at time t2,
This corresponds to the holding output 4 being set to logic "1". The time corresponding to one clock from time T2 to time T3 is the synchronization loss described above. Since the synchronous output 5 has become logic "1", the differentiating circuit 30 changes the output pulse 6 to logic "1". The synchronous output 5 is supplied to the synchronous circuit 40
Synchronizes with the first clock 1.

At time T4, the differentiating circuit 30 changes the output pulse 6 to logic "0" again. This is because the pulse width of the output pulse 6 has become 1T.

At time t7, the synchronization circuit 40 sets the reset signal to logic "1". This corresponds to the fact that the synchronous output 5 has become logic "1" at the time T3. The time corresponding to one clock from time t6 to time t7 is a synchronization loss.

At time t8, JK flip-flop 11 sets holding output 4 to logic "0". this is,
This is because at time t7, the reset signal 7 is set to logic "1".

At time T6, the synchronization circuit 20 sets the synchronization output 5 to logic "0". This corresponds to the hold output 4 being set to logic “0” at time t8.

At time t13, the periodic circuit 40 sets the reset signal 7 to logic "0". This is the time T
At 6, this corresponds to the synchronization output 5 being set to logic “0”.

As described above, the input pulse 3 having the pulse width t input at the time t1 is converted into the output pulse 6 having the pulse width T output at the time T3. That is, the input pulse 3 synchronized with the first clock 1
Will be synchronized.

In the above embodiment, the JK flip-flop 11 keeps the holding output 4 until the output pulse 6 rises.
Is maintained at the logic "1", so that the output pulse 6 can always be obtained regardless of the period t of the first clock 1 and the period T of the second clock 2.

[Configuration of Second Embodiment] Next, a second embodiment of the present invention will be described with reference to the drawings.

The feature of the present embodiment lies in the configuration of the holding circuit 10, and other configurations are the same as those of the first embodiment.

Referring to FIG. 4, the holding circuit 10 of the pulse synchronization circuit according to the present embodiment includes a JK flip-flop 11,
It comprises a flip-flop 12 and an OR circuit 13.

The D flip-flop 12 inputs the inverted signal of the first clock 1 to the clock terminal and the input pulse 3 to the D terminal.

The OR circuit 13 receives the input pulse 3, the output of the JK flip-flop 11, and the D flip-flop 12
Output and input. The output of the OR circuit 13 is the held output 4. At the timing of t2, the D flip-flop 12 detects the falling of the input pulse 3 and the JK
During the rise of the output of the flip-flop 11, the hold output 4 is prevented from temporarily becoming logic "0".

In the holding circuit 10 configured as described above, the holding output 4 is set to the logic “1” at the rising timing of the input pulse 3.

[Operation of Second Embodiment] Next, the operation of this embodiment will be described with reference to the drawings.

Referring to FIG. 5, at time t1, input pulse 3 becomes logic "1".

At time t2, JK flip-flop 11 holds logic "1" which is the value of input pulse 3,
Output to signal 8. The JK flip-flop 11 outputs the logic “1” as the signal 8 until the logic “1” is input to the K terminal. Further, the OR circuit 13 outputs the signal 8
And the input pulse 3 and the output 83 of the D flip-flop 12 obtained by delaying the input pulse 3 by 1 / 2t, and outputs the result to the holding output 4. Therefore, the hold output 4 is at time t
At the time of = 1, the input pulse 3 becomes the logic "1" at the same time as the logic "1", and outputs the logic "1" to the holding output 4 until the logic "1" is input to the K terminal of the JK flip-flop 11.

At time T2, the synchronization circuit 20 sets the synchronization output 5 to logic "1". This means that at time t1,
This corresponds to the holding output 4 being set to logic "1". The time corresponding to one clock from time T1 to T2 is the above-described synchronization loss. The synchronous output 5 is set to logic "1". Further, the synchronization output 5 is synchronized with the first clock 1 by the synchronization circuit 40.

At time T3, the differentiating circuit 30 changes the output pulse 6 to logic "0" again. This is because the pulse width of the output pulse 6 has become 1T.

At time t5, the synchronization circuit 40 sets the reset signal to logic "1". . This is the time T2
Corresponds to the fact that the synchronous output 5 has become logic "1". The time corresponding to one clock from time t4 to time t5 is a synchronization loss.

At time t6, JK flip-flop 11 sets holding output 4 to logic "0". this is,
This is because the reset signal 7 is set to the logic “1” at the time t5.

At time T5, the synchronization circuit 20 sets the synchronization output 5 to logic "0". This corresponds to the hold output 4 being set to logic “0” at time t6.

At time t11, the synchronization circuit 40 sets the reset signal 7 to logic "0". This is the time T
5 corresponds to the fact that the synchronous output 5 is set to logic "0".

As described above, the input pulse 3 having the pulse width t input at the time t1 is converted into the output pulse 6 having the pulse width T output at the time T2. That is, the output pulse 6 is output 1T earlier than in the first embodiment.

As described above, in this embodiment, the output pulse 6 can be output earlier than in the first embodiment. Therefore, the synchronization loss of the output pulse 6 is reduced.

[0057]

As described above, according to the present invention, since the input pulse 3 is held by the holding circuit 10, the cycle of the first clock 1 and the second clock 2 can be set in any manner. This produces an effect that an output pulse 6 can be obtained.

Further, according to the second embodiment of the present invention,
The effect that the synchronization loss of the output pulse 6 can be reduced can also be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a first embodiment of the present invention.

FIG. 3 is a time chart showing the operation of the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a second embodiment of the present invention.

FIG. 5 is a time chart showing the operation of the second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of a synchronization circuit.

FIG. 7 is a time chart showing the operation of the synchronous circuit.

FIG. 8 is a diagram showing a configuration of a differentiating circuit.

FIG. 9 is a time chart showing the operation of the differentiating circuit.

FIG. 10 is a block diagram of a conventional pulse synchronization circuit.

FIG. 11 is a time chart illustrating the operation of the pulse synchronization circuit of FIG. 10;

FIG. 12 is a block diagram of a conventional pulse synchronization circuit.

FIG. 13 is a time chart showing the operation of the pulse synchronization circuit of FIG.

FIG. 14 is a circuit diagram of the pulse synchronization circuit of FIG. 12;

FIG. 15 is a time chart illustrating the operation of the pulse synchronization circuit of FIG. 14;

FIG. 16 is a time chart illustrating the operation of the pulse synchronization circuit of FIG. 14;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st clock 2 2nd clock 3 Input pulse 4 Holding output 5 Synchronization output 6 Output pulse 7 Reset signal 8 Signal 9 Extension output 10 Holding circuit 11 JK flip-flop 12 D flip-flop 13 OR circuit 20 Synchronization circuit 21 D flip-flop 22 D flip-flop 30 Differentiating circuit 31 D flip-flop 32 AND circuit 40 Synchronous circuit 41 D flip-flop 42 D flip-flop 50 Extension circuit 51 D flip-flop 52 D flip-flop 53 OR circuit 91 Clock 92 Input signal 93 Intermediate output 94 Output Signal 95 Clock 96 Input signal 97 Intermediate output 98 Output signal

Claims (8)

(57) [Claims] 1. A first clock and inputs the input pulse synchronized to the first clock synchronized with the first clock
And outputs the held output while holding the input pulse, a holding circuit which is reset by a reset signal, the holding power and the second said holding output second inputs the clock holding circuit outputs a first synchronization circuit for outputting as a synchronous output in synchronization with the clock, the synchronization output and the second output from the first synchronization circuit
Of a differentiating circuit inputs the clock outputs a pulse width of the synchronous output as an output pulse width of one period of the second clock, the inputs and synchronization outputs the first clock the synchronous output A second synchronization circuit that synchronizes the first clock with the first clock and outputs the reset signal as the reset signal. 2. The pulse synchronization circuit according to claim 1, wherein said holding circuit holds an input pulse at a timing of a rise of said first clock. 3. The holding circuit comprises: a first terminal connected to a clock terminal, the input terminal connected to a set terminal; the reset terminal connected to a reset terminal;
3. The pulse synchronizing circuit according to claim 2, further comprising a flip-flop that inputs and outputs a holding output. 4. The pulse synchronizing circuit according to claim 1, wherein said holding circuit holds the input pulse at a rising timing of said input pulse. 5. The holding circuit according to claim 1, wherein the first terminal is a clock terminal, the input terminal is a set terminal, the reset terminal is a reset signal,
A flip-flop to be inputted respectively; an inverted signal of the first clock to a clock terminal; an input pulse to a D terminal; and an input signal, an output signal of the JK flip-flop and the D signal. 5. The pulse synchronization circuit according to claim 4, further comprising: an OR circuit that receives an output signal of the flip-flop and outputs the output as a hold output. 6. A first D flip-flop that inputs a second clock to a clock terminal, a holding output output from the holding circuit to a D terminal, and a clock terminal, The second clock is supplied to the D terminal by the D
6. The pulse synchronizing circuit according to claim 1, further comprising a second D flip-flop that receives an output signal of the flip-flop and outputs the same as a synchronous output. 7. A first D flip-flop for inputting a first clock to a clock terminal, a holding output from the holding circuit to a D terminal, and a clock terminal to a clock terminal, respectively. The first clock is supplied to the D terminal by the D clock.
6. The pulse synchronizing circuit according to claim 1, further comprising a second D flip-flop which receives an output signal of the flip-flop and outputs the reset signal as a reset signal. 8. A D flip-flop for inputting the second clock to a clock terminal and the synchronization output to a D terminal, an inverted signal of an output signal of the D flip-flop and the synchronization output, respectively. 6. A pulse synchronization circuit according to claim 1, further comprising: an AND circuit for inputting the following.