JPH02126717A - Duty converting circuit - Google Patents

Abstract

PURPOSE:To freely change a frequency and to facilitate bit extension by using a selector circuit, switching two values and supplying a data value to a counter circuit. CONSTITUTION:When a synchronizing clock is inputted from an initial condition, the data of An-1 are loaded to an (n) bit down counter circuit 2, counted down from the load value, and when a borrow comes out by the (n) bit down counter circuit 2, the data of Bn to 1 are loaded and the output of an output Y is inverted. Counting-down is executed from the loaded value, the borrow comes out by the (n) bit down counter circuit 2, the data of An-1 are loaded and the output of the output Y is inverted. By repeating such a process, an arbitrary clock pulse is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a duty conversion circuit 1 which is capable of changing the duty of a clock signal to an arbitrary value.

[Conventional technology]

FIG. 4 is a circuit diagram showing an example of a conventional duty conversion circuit.

In the figure, αO is an n-bit up counter circuit, (b)
is an n-bit comparison circuit. FIG. 5 is a waveform diagram showing the timing of waveforms of each part of the circuit of FIG. 4.

Next, the operation will be explained. The duty conversion circuit includes an n-bit up counter circuit αQ that counts clocks and a count value (An) of the n-bit up counter circuit αQ.
-1) and the data input (Bn-1) that specifies the changing point of the pulse of the output signal? As input, compare the above two values,
It consists of an n-bit ratio correction circuit α9 that outputs %H# when the comparison condition is satisfied.

Next, the timing chart of FIG. 4 will be explained. At point A shown in FIG. 4, the n-bit up counter circuit αQ is initialized, the count value is O(H), and n
The condition of the bit comparison circuit αq is An-1<Bn~1, and the output Y becomes 'L'. At point B, the count value of the n-bit up counter circuit α0 is 3 [H], and the conditions of the n-bit comparison circuit αη are An~1>Bn~1 and the output Y
becomes 'H'. At point C.

The count value of the n-bit up counter circuit 00 carries up and returns to 0CH), the condition of the n-bit comparison circuit αυ becomes A n -1 (B n+ 1), and the output Y becomes 'L'.

[Problem that the invention seeks to solve]

Since the conventional duty conversion circuit is configured as described above, it is not possible to set the pulse width, and therefore it is not possible to change one frequency.

There were problems such as spikes occurring in the output.

This invention was made to solve the above problems, and it is possible to change the frequency completely freely, and
The purpose is to provide a long-life duty conversion circuit that allows easy bit expansion.

[Means to solve the problem]

The duty conversion circuit according to the present invention uses a selector circuit to switch between two values and provide a data value to a counter circuit.

[Effect]

The duty conversion circuit according to the present invention includes an AND circuit that takes the count value immediately before the borrow or carry of the counter circuit, and an OR circuit that takes this output signal and the borrow or carry. By switching the data value, one operation is made even if the operation is fast.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
2 is a circuit diagram showing a duty conversion circuit, and FIG. 2 is a waveform diagram showing timings of waveforms of various parts of the circuit of FIG. 1.

In the figure, (1) is an n-bit selector circuit that switches the data value that sets the pulse width, and (2) is an n-bit down counter circuit (n
bit up counter circuit), 13) is an AND circuit for indicating the count value immediately before borrow or carry;
(4) is an inverter circuit that outputs an inverted signal of the synchronous clock, and (5) is an inverter circuit that inverts all outputs depending on the state indicated by AND circuit (3), and outputs all signals that replace the data in the n-bit selector circuit ([). Flip-flop circuit on J-,
(6) is a borrow of the n-bit down counter circuit (2),
Alternatively, it is a J- flip-flop circuit whose output is completely inverted by a carry.

Next, the operation will be explained using the timing chart of FIG. When a synchronous clock is input from the initial state, the data of An-1 is loaded into the n-bit down counter circuit (2), and the countdown starts from the loaded value.
When a borrow occurs in the n-bit down counter circuit (2), data from Bn to 1 is loaded, and the output Y is inverted. Also, count down from this load value,
When a borrow occurs in the n-bit down counter circuit (2), the data of An-1 is loaded and the output Y is inverted.

By repeating this, all arbitrary clock pulses are output.

In addition, in the above embodiment, the duty conversion circuit is shown when the input data value is 1 [H] or more, but when the load value is 0
At [H], the n-bit selector circuit ('') cannot be switched. Therefore, this problem can be solved by devising a technique as shown in FIG. 3 Iζ. FIG. 3 is a circuit diagram of a duty conversion circuit according to another embodiment of the invention. In the figure, (1) to (3) are equivalent to those shown in FIG. (4m), (4b) are inverter circuits, (5
m), (sa) (9) is a D flip-flop.

(5b), (6b) are flip-flops on J-, +
7) and (8) are OR circuits. An OR circuit whose input is the output of the AND circuit (3) indicating the count value of the n-bit down counter circuit (2) immediately before the occurrence of a borrow or carry, and the borrow or carry of the n-bit counter circuit (2). (8), a D flip-flop circuit (5a) whose input is an inverter circuit (4&) that outputs an inverted signal of the output of the OR circuit (8) and a synchronous clock, and a D flip-flop circuit (5a) whose clock input is the output of the D flip-flop (5&). According to the timing of the output of the D flip-flop (5a), J-
The flip-flop (6b) is an n-bit selector circuit (
1) All switching signals are generated. Also, reset 1 to initialize the entire circuit! ! No.-1i-D flip-flop circuit (9)'! By operating with the inverted 1a of the i-synchronous clock, the entire circuit is operated from the rising edge of all clocks.

Another feature of the AND circuit according to the present invention is that the selector circuit is switched earlier than the read timing in the counter circuit.

〔Effect of the invention〕

As described above, according to the present invention, not only the duty of the output clock can be changed, but also the frequency can be changed, and bit expansion can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a duty conversion circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram showing the timing of each waveform in FIG. 1, and FIG. 3 is a duty conversion circuit according to another embodiment of the invention. FIG. 4 is a circuit diagram of a conventional duty conversion circuit, and FIG. 5 is a waveform diagram showing timings of waveforms of various parts in FIG. 4. In the figure, ([) is an n-bit selector circuit, (2) is an n-bit down counter circuit (n-bit up counter circuit), +3) is an AND circuit, (4m), (4b) is an inverter circuit, (5m) , (6m), (9) are D flip-flops, (5), (51)), (6),
(6b) is a flip-flop circuit at J-, +7),
(8) is an OR circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] An n-bit selector circuit that inputs a signal to set the pulse width of an output signal, switches the input setting signal and outputs it, and reads the setting value output from the n-bit selector circuit at borrow or carry timing. An n-bit down counter circuit (n-bit up counter circuit) that counts the pulse width of the output signal with `H' at the count value one time before the borrow or carry timing in the above n-bit down counter circuit. an inverter circuit that outputs an inverted signal of the synchronous clock; and a first J-K flip-flop that receives the outputs of the AND circuit and the inverter circuit and outputs a signal for switching the selector circuit. and a second JK flip-flop circuit that inverts and outputs an output based on a borrow or carry input of the n-bit down counter circuit.