JP2932813B2 - Output latch circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output latch circuit, and more particularly to an output latch circuit capable of changing the output timing with respect to an external clock.

[0002]

2. Description of the Related Art As a conventional output latch circuit, there is one as shown in a block diagram of FIG. As shown in FIG. 4, the conventional output latch circuit receives input signals from input terminals 7a to 7n, which are n input terminals. Input terminal 7
a to 7n are latch circuits 1a to 1n which are n latch circuits.
1n input terminals. The clock input terminals of the latch circuits 1a to 1n are connected to output terminals of the buffer circuit 4 whose input terminals are connected to the external clock input terminal 10, respectively. Latch circuits 1a to 1n
Output terminal is a latch circuit 2a which is n latch circuits.
To 2n input terminals. Latch circuit 2
Output terminals a to 2n are connected to output terminals 6a to 6n, which are n output terminals, respectively. The input terminal of the inverter 5 is connected to the output terminal of the buffer circuit 4,
Output terminals of the inverter 5 are connected to clock input terminals of the latch circuits 2a to 2n, respectively. The terminal 12 is provided at the output terminal of the buffer circuit 4, the terminal 13 is provided at the output terminal of the inverter 5, and the terminal 14 is provided at the output terminal of the latch circuit 1a for convenience of explanation.

Next, the operation of the conventional output latch circuit shown in FIG. 4 configured as described above will be described. FIG.
5 is a timing chart showing the operation of the conventional output latch circuit shown in FIG. The signal waveform appearing at the input terminal 7a is
An input signal at the input terminal 7a is shown, and a signal waveform appearing at the external clock input terminal 10 indicates an external clock input signal. The external clock input signal is inverted by the buffer circuit 4 and output to the terminal 12, and the latch circuit 1a
-1n clock input terminals, and further output to one of the input terminals of the inverter 5. Latch circuit 1a
, The input signal input from the input terminal 7a is output according to the clock signal appearing at the terminal 12, so that the signal appearing at the terminal 14 is one of the clock input signals appearing at the terminal 12 rather than the input signal at the input terminal 7a. / 2 cycles.

In the latch circuit 2a, since a signal having a phase opposite to that of the clock input signal appearing at the terminal 12 appears at the terminal 13, the output signal outputted at the output terminal 6a is more at the terminal 13 than at the terminal 14. It is delayed by a half cycle of the appearing clock input signal. Terminal 12 and terminal 13
, The cycle of the clock input signal appearing at the input terminal 7a is equal to the cycle of the external clock input signal. Therefore, the input signal input from the input terminal 7a is delayed by one cycle of the external clock input signal via the latch circuits 1a and 2a. It is output in synchronization with the rise of the clock input signal. Input signals input from the input terminals 7b to 7n are also output to the output terminals 6b to 6n at the same timing as described above.

[0005]

However, in the conventional output latch circuit described above, the input signal input from the input terminal is output to the output terminal in synchronization with the rising of the external clock input signal. The signal has a delay. For this reason, in another circuit that receives the output signal of the conventional output latch circuit, the timing of the output signal with respect to the external clock input signal, the delay time with respect to the external clock input signal, and the timing of taking in the output signal must be considered. If these timings do not match, a latch circuit may be further added to the input unit, or a clock input signal having an inverted phase or a delayed clock input signal may be generated and supplied to the input unit circuit. There is a need.

As described above, in the conventional output latch circuit,
In some cases, it is necessary to design in consideration of the timing of signals in the next-stage circuit so that a new circuit is not added to another circuit connected to the next stage. However, in a conventional output latch circuit configured with highly versatile electronic components and electric circuits, it is difficult to match the timing of an output signal with the timing of taking in an input signal in another circuit connected to the next stage. .

Therefore, in the conventional output latch circuit, since the timing of the output signal is fixed, a latch circuit or the like must be further added depending on another circuit connected to the next stage. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an output latch circuit for controlling a timing of outputting an output signal based on an external clock input signal is provided. It is an object to provide an output latch circuit that can be changed.

[0009]

An output latch circuit according to the present invention has a first latch circuit having n latch circuits for controlling the timing of outputting an input signal based on a clock input signal input from the outside. And a second latch circuit group having n latch circuits having the output signals of the n latch circuits in the first latch circuit group as input signals. A polarity inverting circuit for receiving a signal and inverting the clock input signal in accordance with the output polarity selection signal, and outputting a signal input in the second latch circuit group based on an output signal of the polarity inverting circuit; The timing is controlled.

[0010]

In the output latch circuit according to the present invention, the first
Are controlled based on a clock input signal input from the outside, and the second latch circuit group controls the clock input signal and an output polarity selection for inverting the clock input signal. The timing for outputting the input signal is controlled based on the signal. Therefore, the output latch circuit according to the present invention selects the level “H” or “L” of the output polarity selection signal applied to the output polarity selection terminal, thereby changing the input signal input from the input terminal to the rising edge of the external clock input signal. , Or output in synchronization with the fall of the external clock input signal.

[0011]

Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an output latch circuit according to a first embodiment of the present invention. In FIG. 1, the same reference numerals as those of the conventional output latch circuit shown in FIG. 4 and described above have the same functions, so that the description thereof is omitted here. 1. In FIG. 1, the configuration different from the conventional output latch circuit shown in FIG. 4 is that the inverter 5 in FIG. 4 is replaced by an exclusive OR circuit 3 in FIG. The output polarity selection terminal 11 is connected to one of the input terminals of the exclusive OR circuit 3.

Next, the operation of the output latch circuit according to the first embodiment configured as described above will be described. FIG.
3 is a timing chart showing the operation of the output latch circuit according to the first embodiment of the present invention shown in FIG. The signal waveform at the input terminal 7a indicates an input signal at the input terminal 7a, and the signal waveform at the external clock input terminal 10 indicates an external clock input signal. The external clock input signal is inverted by the buffer circuit 4, output to the terminal 12, output to the clock input terminals of the latch circuits 1a to 1n, respectively, and further output to one of the input terminals of the exclusive OR circuit. In the latch circuit 1a, the input signal input from the input terminal 7a is output according to the clock signal appearing at the terminal 12, so that the signal appearing at the terminal 14 is higher than the clock signal appearing at the input terminal 7a. Delay by one half cycle of the signal.

In the latch circuit 2a, the latch circuit 1
The signal input from the output terminal a is output according to the clock input signal appearing at the terminal 13. The clock input signal appearing at the terminal 13 is a signal having a phase opposite to that of the clock input signal appearing at the terminal 12 when the output polarity selection terminal 11 is “H”, and is output when the output polarity selection terminal 11 is “L”. 12 is in phase with the clock input signal appearing at 12. When the output polarity selection terminal 11 is at "H", a signal having a phase opposite to that of the clock input signal appearing at the terminal 12 is input to the clock input terminals of the latch circuits 1a to 1n. The output signal is output after being delayed by a half cycle of the clock input signal appearing at the terminal 13 from the signal appearing at the terminal 14. Therefore, since the cycle of the clock input signal appearing at the terminals 12 and 13 is equal to the cycle of the external clock input signal, the input terminal 7
The input signal input from a is delayed by one cycle of the external clock input signal via the latch circuit 1a and the latch circuit 2a and output in synchronization with the rising of the external clock input signal.

On the other hand, when the output polarity selection terminal 11 is "L", a signal in phase with the clock input signal appearing at the terminal 12 is input to the clock input terminals of the latch circuits 1a to 1n. The output signal of the circuit 2a has the same phase as the signal appearing at the terminal 14. Therefore, the input signal input from the input terminal 7a is delayed by a half cycle of the external clock input signal via the latch circuit 1a and the latch circuit 2a and output in synchronization with the fall of the external clock input signal.

The input signals input from the input terminals 7b to 7n are output to the output terminals 6b to 6n at the same timing as the input signal input from the input terminal 7a.

As described above, the output latch circuit according to the first embodiment synchronizes the input signals input from the input terminals 7a to 7n with the rise of the external clock input signal by the level of the signal applied to the output polarity selection terminal 11. Output or output in synchronization with the fall of the external clock input signal.

FIG. 3 is a block diagram showing an output latch circuit according to a second embodiment of the present invention. The second book shown in FIG.
In the output latch circuit according to the third embodiment, the components different from the output latch circuit according to the first embodiment shown in FIG.
The exclusive OR circuit 3 in FIG. 1 is replaced by an inverter 5 and switches 8a and 8b in FIG. As shown in FIG. 3, the input terminal of the inverter 5 is connected to the output terminal of the buffer circuit 4 and one terminal of the switch 8b. The other terminal of the switch 8b is connected to one terminal of the switch 8a and the latch circuits 2a to 2n.
Clock input terminal. Switch 8a
Is connected to the output terminal of the inverter 5.

Next, the operation of the output latch circuit according to the second embodiment configured as described above will be described. The operation of the output latch circuit according to the second embodiment is the same as that of the first embodiment.
The operation is basically the same as that of the output latch circuit according to the embodiment. The switch 8a is turned on only when the output polarity selection terminal 11 is "H", and the switch 8b is turned off only when the output polarity selection terminal 11 is "H". Thus, the clock input signal appearing at the terminal 13 becomes a signal having a phase opposite to that of the clock input signal appearing at the terminal 12 when the output polarity selection terminal 11 is "H". At this time, the signal is in phase with the clock input signal appearing at the terminal 12. As described above, the timing of the clock input signal appearing at the terminal 13 is the same as the timing of the clock input signal appearing at the terminal 13 in the output latch circuit according to the first embodiment.

Therefore, the output latch circuit according to the second embodiment operates in a manner similar to the operation of the output latch circuit according to the first embodiment when the output polarity selection terminal 11 is at "H". The output signal 2a is output with a delay of a half cycle of the clock input signal appearing at the terminal 13 with respect to the signal appearing at the terminal 14. The input signal input from the input terminal 7a is input to the latch circuit 1a and the latch circuit 2a.
Is delayed by one cycle of the external clock input signal and output in synchronization with the rise of the external clock input signal.

On the other hand, when the output polarity selection terminal 11 is "L", a signal in phase with the clock input signal appearing at the terminal 12 is input to the clock input terminals of the latch circuits 1a to 1n. The output signal of the circuit 2a has the same phase as the signal appearing at the terminal 14. Therefore, the input signal input from the input terminal 7a is delayed by a half cycle of the external clock input signal via the latch circuit 1a and the latch circuit 2a and output in synchronization with the fall of the external clock input signal.

As described above, in the output latch circuit according to the second embodiment, similarly to the operation of the output latch circuit according to the first embodiment, the input terminal 7a depends on the level of the signal applied to the output polarity selection terminal 11. 7n is output in synchronization with the rising edge of the external clock input signal,
Alternatively, it is possible to select whether to output in synchronization with the fall of the external clock input signal.

It should be noted that the buffer circuit 4 used in the above-described first and second embodiments has the same structure as that of the buffer circuit 4 in the case where the buffer circuit 4 is configured using two stages of inverters. If one inverter is used as the inverter 5, the output latch circuit according to the present embodiment can be realized while suppressing an increase in the number of elements.

[0024]

As described above, according to the output latch circuit of the present invention, the input signal input from the input terminal is determined by the level "H" or "L" of the output polarity selection signal applied to the output polarity selection terminal. Can be controlled in synchronization with the rising edge of the external clock input signal or in synchronization with the falling edge of the external clock input signal. Therefore, in the output latch circuit according to the present invention, even if another circuit connected to the next stage takes in the input signal in synchronization with the rising of the external clock input signal, the output latch circuit is synchronized with the falling of the external clock input signal. Even circuits that take in data can output signals directly to those circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an output latch circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the output latch circuit according to the first embodiment of the present invention shown in FIG.

FIG. 3 is a block diagram illustrating an output latch circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating an example of a conventional output latch circuit.

FIG. 5 is a timing chart showing an operation of the conventional output latch circuit shown in FIG.

[Explanation of symbols]

1a, 1b, 1c, 1n, 2a, 2b, 2c, 2n;
Latch circuit 3; Exclusive OR circuit 4; Buffer circuit 6a, 6b, 6c, 6n; Output terminal 7a, 7b, 7c, 7n; Input terminal 10; External clock input terminal 11; Output polarity selection terminal

Claims (3)

(57) [Claims] 1. A timing for outputting an input signal is controlled based on a clock input signal input from the outside.
A first latch circuit group having n latch circuits, and a second latch circuit group having n latch circuits having output signals of the n latch circuits in the first latch circuit group as input signals. An output latch circuit having a polarity inversion circuit for inputting an output polarity selection signal from the outside and inverting the clock input signal in accordance with the output polarity selection signal; An output latch circuit for controlling a timing at which an input signal is output in the group of latch circuits. 2. The exclusive-OR circuit according to claim 1, wherein the polarity-inverting circuit has an exclusive-OR circuit, receives the output polarity selection signal from one input terminal of the exclusive-OR circuit, and inputs the other input terminal of the exclusive-OR circuit. 2. The output latch circuit according to claim 1, wherein the clock input signal is input. 3. The polarity reversing circuit includes an inverter, a first switch connected in series to the inverter, and a second switch connected in parallel to the inverter and the first switch. 2. The output latch circuit according to claim 1, wherein the first and second switches operate based on the output polarity selection signal such that the open / close states are opposite to each other.