JPH0756553A - Video signal control circuit - Google Patents

Abstract

PURPOSE:To provide a video signal control circuit which can select and set a clock signal which is always in optimum phase relation for a video signal. CONSTITUTION:In a flat display which samples a video signal and displays it, a video signal control circuit is constituted with a clock signal reproducing circuit 7 which generates plural clock signals which have the same frequency as that of the video signal and a different phase from it, a clock signal selecting circuit 6 which samples a clock signal at the point of time of changing of the video signal and selects one clock signal plural clock signals based on based on this sampling, and a video signal outputting circuit 2 which samples a video signal with a selected clock signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal control circuit used in a flat display device.

[0002]

2. Description of the Related Art In a flat display device such as a liquid crystal display or a plasma display, an input video signal is sampled and converted into a digital signal by A / D conversion or the like, and the flat display device is responsive to the magnitude of the digital value. Is driven to display. When the sampling of the video signal in this flat display device is performed at the timing of the clock signal on the side of the flat display device, the clock having the optimum display state is selected from the plurality of clock signals having different phase relations to the video signal. You need to select a signal. Conventionally, this clock signal is selected by selecting a plurality of clock signals having different phases by switching a selection switch, sampling a video signal according to the selected clock signal and displaying it, and observing the display screen to obtain the optimum clock signal. This is done by searching for signals.

[0003]

However, in the above-described conventional video signal control, when environmental conditions such as temperature and power supply voltage change, the phase relationship between the video signal and the clock signal shifts and the video signal sampling error occurs. Occurs, and the display screen is disturbed.

When the signal source of the video signal is changed with respect to the flat display device, a clock signal having an optimum phase relationship with the video signal every time the signal source is changed on the flat display device side. Need to be set.

Therefore, the present invention solves the above-mentioned problems of the conventional video signal control, and provides a video signal control circuit capable of selecting and setting a clock signal which always has an optimum phase relationship with the video signal. The purpose is to provide.

[0006]

In order to achieve the above object, a video signal control circuit of the invention of the present application is a flat display for sampling and displaying a video signal, and a plurality of video signals having different phases at the same frequency as the video signal are provided. Clock signal reproducing circuit for generating clock signals, and clock signal selection for sampling the clock signal at the time when the video signal changes and selecting one clock signal from a plurality of clock signals based on the sampling A circuit and a video signal output circuit for sampling the video signal according to the selected clock signal.

In the video signal control circuit, the clock signal selection circuit selects the clock signal by combining a plurality of sampling values of the clock signals having different phases at the time when the signal of the video signal changes, and performs sampling of the video signal. Can be set as a clock signal for the video signal, and the clock signal to be selected is the phase between the video signal and the clock signal with a phase difference of 1/4 cycle of the video signal from the change point of the video signal as the center. It is a clock signal whose signal changes in a section where the relationship is the same.

In the present invention, the clock signal reproducing circuit is a circuit having a function of generating a signal having the same frequency as the input signal, and for example, a PLL circuit can be used.

Further, in the present invention, the clock signal selection circuit is a circuit having a function of selecting one signal from a plurality of signals, and can be constituted by, for example, a decoder, a logic circuit or the like.

Further, in the present invention, the video signal output circuit is a circuit having a function of sampling an analog signal and converting it into a digital signal for driving a flat display, and is constituted by, for example, a sample hold circuit, an A / D circuit and the like. be able to.

[0011]

According to the invention of the present application, a clock signal reproducing circuit generates a plurality of clock signals having the same frequency as the video signal but different phases based on the synchronizing signal from the video signal source. , A clock signal is sampled at the time when the signal of the video signal changes, and one clock signal is selected from a plurality of clock signals from the clock signal reproduction circuit based on the sampling, and the clock signal is output in the video signal output circuit. The video signal is sampled by the clock signal selected by the selection circuit, and the flat display is driven by the sampled value to display an image.

The clock signal selection circuit selects a clock signal by a combination of sampling values of a plurality of clock signals having different phases at the time when the signal of the video signal changes, and the selected clock signal is sampled in the video signal. Can be set as a clock signal for performing the video signal, and the clock signal to be selected is set to 1/4 of the video signal from the change point of the video signal.
It is possible to use a clock signal in which the signals change within a section in which the phase relationship between the video signal and the clock signal is the same around the time point of the phase difference of the cycle. By selecting the clock signal in this section, it is possible to reduce the mis-sampling due to the signal change and perform the sampling with the clock signal having the most margin.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings, but the present invention is not limited to the embodiments.

FIG. 1 is a block diagram showing an embodiment of a video signal control circuit of the present invention, showing an example of an NC device as a signal source of a video signal. In FIG. 1, reference numeral 1 denotes a flat display device such as a liquid crystal display and a plasma display. In FIG. 1, this flat display device is illustrated by a liquid crystal display.
A video signal output circuit 2, a clock signal output circuit 3, a horizontal synchronizing signal output circuit 4, and a vertical synchronizing signal output circuit 5 are connected to the liquid crystal display 1. The video signal output circuit 2 inputs the video output signal output from the NC device 8 and outputs the video signal to the liquid crystal display 1 in synchronization with the clock signal from the clock signal selection circuit 6.
The clock signal output circuit 3 is a circuit for outputting the clock signal from the clock signal selection circuit 6 to the liquid crystal display 1, and the liquid crystal display 1 performs a display operation in synchronization with this clock signal. The horizontal synchronizing signal output circuit 4 and the vertical synchronizing signal output circuit 5 receive the horizontal synchronizing signal and the vertical synchronizing signal output from the NC device 8 and synchronize with the clock signal from the clock signal selecting circuit 6. This is a circuit for outputting to the liquid crystal display 1.

The clock signal selection circuit 6 selects a clock signal which is always in the optimum phase relationship with the video signal from a plurality of clock signals having different phases output from the clock signal reproduction circuit 7, and It is a circuit for outputting the selected clock signal to the video signal output circuit 2, the clock signal output circuit 3, the horizontal synchronizing signal output circuit 4, and the vertical synchronizing signal output circuit 5. The clock signal reproduction circuit 7 is a circuit that forms a clock signal having the same cycle as the horizontal synchronizing signal from the NC device 8 that is a video signal source, and can be configured by, for example, a PLL circuit. The clock signal reproducing circuit 7 also forms a plurality of clock signals having mutually different phases and outputs them to the clock signal selecting circuit 6. With this clock signal reproducing circuit 7, the frequencies of the clock signals on the video signal source side and the liquid crystal display 1 side can be made uniform.

When the flat display device is composed of a liquid crystal display, the period of the vertical synchronizing signal on the video signal source side corresponds to one scanning line of the liquid crystal display 1, and the period of the horizontal synchronizing signal corresponds to one pixel of the liquid crystal display 1. To the liquid crystal display 1 by a clock signal formed corresponding to the cycle of the horizontal synchronizing signal.
The driving timing of each pixel can be controlled.

In the video signal control circuit of the present invention, the clock signal selecting circuit 6 in the block diagram selects a clock signal which is always in the optimum phase relationship with the video signal.

First, the phase relationship of the clock signal with respect to the video signal will be described with reference to FIG.

In the liquid crystal display 1, the display of the video signal is performed by driving each pixel forming the liquid crystal display 1 based on the input video signal. For that purpose, it is necessary to sample the input video signal with a clock signal corresponding to each pixel to obtain a sampling value.

In sampling this video signal,
When the video signal and the clock signal have a phase relationship as shown in FIG. 3D, it can be performed, for example, at the falling timing of the clock signal. In addition,
In the figure, the timing of the falling edge of this clock signal is indicated by the thick chain line. In order to sample the video signal at the falling edge of the clock signal, the video signal must have a signal value at the falling edge of the clock signal (in the figure,
High state) is required. That is, when the phase relationship between the video signal and the clock signal is deviated, the video signal cannot be sampled by the clock signal.

For example, in FIG. 3D, when the clock signal fluctuates due to changes in temperature and power supply voltage and has a phase relationship shown by a broken line, sampling of the video signal is performed at the falling timing of the clock signal. Can't do it. Further, in FIG. 3E, even when the video signal fluctuates due to a change in temperature or power supply voltage or a difference in video signal source, and the phase relationship shown by the broken line is obtained,
The video signal cannot be sampled at the falling edge of the clock signal.

In the video signal control circuit of the present invention,
The sampling timing of the video signal is set to a time point near the center of the portion having the signal component of the video signal (high state of the signal), and the clock signal for performing the sampling is selected from a plurality of clock signals having different phases. It is obtained by selecting the clock signal at the time point.
3A to 3C show that by sampling with the clock signal selected in the video signal control circuit of the present invention, the video signal can be sampled regardless of fluctuations of the video signal and the clock signal. Is shown.

FIG. 3A shows the case where the falling time point of the clock signal is at the central time point of the portion having the signal component of the video signal (high state of the signal).
Here, when the video signal and the clock signal fluctuate back and forth by, for example, a maximum ¼ cycle of the clock signal as indicated by the broken line arrow, as shown in FIG. The case where the video signal is advanced by 1/4 cycle and the video signal is advanced by 1/4 cycle of the clock signal, as opposed to the case where the video signal is advanced by 1/4 cycle of the clock signal, as shown in FIG. That is, the clock signal is always within a section having a delay of 1/4 cycle of the clock signal from the central time point of the video signal. In this section, as shown in the figure, the falling edge of the clock signal is the portion having the signal component of the video signal (the signal is in the high state).
It is inside and sampling can be performed.

That is, a clock signal having a falling time point near the center of the portion having the signal component of the video signal (high state of the signal) is selected from a plurality of clock signals having different phases. By doing so, even if the phase relationship between the video signal and the clock signal changes, the video signal can be sampled.

In FIG. 3, the range of the clock signal capable of sampling the video signal is shown by hatching. Although the sampling timing is set to fall of the clock signal here, it may be set to rise of the clock signal.

In the video signal control circuit of the present invention,
The above clock signal is selected by combining two clock signals having different 1/4 cycle phases at the time of falling of the video signal value. FIG. 2 shows the clock signal for selecting this clock signal. An embodiment of the selection circuit 6 will be shown. In FIG. 2, the flip-flop FF0 is a clock signal CLK0 to CLK3 in which the phase output from the video signal source such as the NC device 8 and the phase output from the clock signal reproducing circuit 7 are different from each other by 1/4 cycle. Clock signal CLK in
0 is input and its output is output to the decoder DEC63. Further, the flip-flop FF1 inputs the video signal and the clock signal CLK1 whose cycle is different from that of the clock signal CLK0 by 1/4 cycle. The output is output to the decoder DEC63. The decoder DEC63 receives the flip-flops FF0 and FF1 as input signals, and outputs outputs corresponding to the combination of the input signals from the output terminals D0 to D3 to the AND circuits AND0 to AND3. Also,
The clock signal reproduction circuit 7 is connected to the AND0 to AND3.
From which clock signals CLK0 to CLK3 are input, and the logical product with the output of the decoder DEC63 is obtained.
Then, the outputs of the AND0 to AND3 are input to the OR circuit OR68, and the output logical sum of the AND0 to AND3 is output. The flip-flop FF0 and the flip-flop FF1 have a function of holding the state of each clock signal at the time of the fall of the video signal. The clock signal selection circuit 6 shown in FIG. 2 receives the decoder DE according to the combination of the signal values of the two clock signals CLK0 and CLK1.
The clock signal selection signal determined by C63 is output, and the clock signals CLK0 to CLK0 are output according to the clock signal selection signal.
One clock signal is selected from CLK3 and output.

4 to 7 show two clock signals CLK.
It is a figure which shows selection of the clock signal by the combination of the signal value of 0 and CLK1. 4 to 7, the video signal, the clock signals CLK0 to CLK3, and the signals of the flip-flops FF0 and FF1 are shown.

First, FIG. 4 shows a flip-flop FF0,
The case where the signal of FF1 is "1" and "0" is shown, respectively. Video and clock signals CLK0 and CLK
In the case where 1 is in the phase relationship of FIG. 4, the clock signal CLK0
The values of CLK1 and CLK1 are "1" and "0" as indicated by FF0 and FF1, respectively.

Then, at the time point delayed by 1/4 cycle of the video signal from the time point of the fall of the video signal, the clock signal CLK0 is output in the section of 1/4 cycle before and after the clock signal (the hatched portion in the figure). And CLK1
There is a signal trailing edge at (the thick arrow in the figure). Even if the video signal or the clock signal fluctuates, the sampling of the video signal is performed in the section that is delayed by 1/4 cycle of the video signal from the falling time of the video signal and further preceded by 1/4 cycle of the clock signal. The video signal can be sampled by selecting a clock signal having a falling time point within this section. In the video signal control circuit of the present invention, this clock signal C
CLK0 is selected from LK0 and CLK1 and the video signal is sampled by this clock signal.

Note that, in FIG. 4, the hatched portion on the lower left indicates the range of signal positions that the clock signal can take with respect to the video signal when the trailing edge of the video signal coincides with the rising edge of the clock signal CLK0, and the right portion The hatched portion of the falling line indicates the range of signal positions that the clock signal can take with respect to the video signal when the falling edge of the video signal coincides with the rising edge of the clock signal CLK1, and FF0 and FF1 are "1", "0"
The phase relationship between the video signal and the clock signal is included within the range of these two diagonal lines.

Further, FIG. 5 shows flip-flops FF0 and FF.
6 shows the case where the signals of 1 are "1" and "1", respectively.
Shows the case where the signals of the flip-flops FF0 and FF1 are "0" and "1", respectively, and FIG.
The case where the signals of F0 and FF1 are "0" and "0", respectively, is shown, and in the phase relationship of each signal, the clock signal CL at the time of the trailing edge indicated by the arrow of the video signal is shown.
It is set by the values of K0 and CLK1.

Then, at the time point delayed by 1/4 cycle of the video signal from the time point of the fall of the video signal, in the section of 1/4 cycle before and after the clock signal (the hatched portion in the figure), in FIG. Clock signals CLK1 and CLK
2 has a falling edge (thick arrow in the figure), FIG. 6 has falling edges of the clock signals CLK2 and CLK3 (thick arrow in the figure), and FIG. 7 has clock signals CLK3 and CLK0. There is a signal fall (thick arrow in the figure). Even if the video signal or the clock signal fluctuates, the sampling of the video signal is performed in the section that is delayed by 1/4 cycle of the video signal from the falling time of the video signal and further preceded by 1/4 cycle of the clock signal. The video signal can be sampled by selecting a clock signal having a falling time point within this section. In the video signal control circuit of the present invention, the clock signals CLK1 and C in FIG.
CLK1 of LK2 is selected, CLK2 of clock signals CLK2 and CLK3 is selected in FIG. 6, and clock signals CLK3 and C of FIG. 7 are selected.
CLK3 of LK0 is selected, and the video signal is sampled by this clock signal.

It should be noted that, in FIGS. 5 to 7, in the same manner as in FIG. 4, the diagonally downward-sloping portion indicates the trailing edge of the video signal.
When the rising edge of one selectable clock signal coincides with the rising edge of the video signal, the clock signal indicates the range of possible signal positions with respect to the video signal. It indicates the range of signal positions that the clock signal can take with respect to the video signal when the rising edge of the clock signal coincides.

FIG. 8 shows a table of selected clock signals for combinations of the values of the flip-flops FF0 and FF1. In FIG. 8, a selected clock signal A indicates a selected clock signal in the video signal control circuit of the present invention. When the signals of FF0 and FF1 are "0" and "0", respectively, the clock signal CLK3 is selected, FF0 and FF
When the signals of 1 are "0" and "1", respectively, the clock signal CLK2 is selected, and when the signals of FF0 and FF1 are "1" and "0", respectively, the clock signal CLK0 is selected and FF0 and The FF1 signal is "1" and "1", respectively.
In this case, the clock signal CLK1 is selected.

Further, the selected clock signal B shows another case of the selected clock signal in the video signal control circuit of the present invention, and like the selected clock signal A, the sampling of the video signal is performed by this selected clock signal. You can

The decoder DEC63 can be composed of an ordinary decoder or a logic circuit. For example, in the case of a normal decoder, the above-mentioned FF0
And a FF1 signal for selecting a clock signal for outputting a clock signal selection signal.

In the case of a logic circuit, the circuit shown in FIG. 9 can be used. The circuit shown in FIG. 9 is a circuit that realizes the selected clock signal A of FIG. 8, and the output terminals D0 to D are formed by the NOT circuit and the AND circuit.
3 to output a clock signal selection signal for selecting a clock signal of CLK0 to CLK3.

(Effects peculiar to the embodiment) With the above configuration,
In the embodiment, even when different NC devices are connected to the flat display device, in order to automatically select the clock signal having the optimum phase, the work such as selecting and setting the display signal of the flat display device is performed. Without having to set the clock signal.

(Modifications) The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

In the above-mentioned embodiment, the example of the NC device is shown as the signal source of the video signal, but the signal source of the video signal is not limited to this NC device, and any device that outputs an image signal. Applicable to

In the above embodiment, the clock signal is selected from the state of the clock signal at the falling edge of the video signal, but the clock signal can be selected from the state of the clock signal at the rising edge of the video signal. Further, instead of sampling the video signal at the falling edge of the clock signal, the sampling of the video signal can be performed at the falling edge of the clock signal.

[0042]

As described above, according to the present invention,
It is possible to provide a video signal control circuit that selects and sets a clock signal that always has an optimum phase relationship with a video signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a video signal control circuit of the present invention.

FIG. 2 is a block diagram showing an embodiment of a clock signal selection circuit of the present invention.

FIG. 3 is a time chart explaining the phase relationship of the clock signal with respect to the video signal of the present invention.

FIG. 4 is a time chart explaining selection of a clock signal of the present invention.

FIG. 5 is a time chart explaining selection of a clock signal of the present invention.

FIG. 6 is a time chart explaining selection of a clock signal of the present invention.

FIG. 7 is a time chart explaining selection of a clock signal of the present invention.

FIG. 8 is a table of selected clock signals for combinations of flip-flop values of the present invention.

FIG. 9 is an embodiment of a logic circuit which constitutes a decoder of the present invention.

[Explanation of symbols]

 1 liquid crystal display 2 video signal output circuit 3 clock signal output circuit 4 horizontal synchronizing signal output circuit 5 vertical synchronizing signal output circuit 6 clock signal selecting circuit 7 clock signal reproducing circuit 8 NC device 61, 62 flip-flop 63 decoder 64 to 67 AND circuit 68 OR circuit

Claims (3)

[Claims] 1. In a flat display for sampling and displaying a video signal, (a) a clock signal reproduction circuit for generating a plurality of clock signals having the same frequency as the video signal but different phases, and (b) a signal of the video signal. A clock signal selection circuit that samples a clock signal at the time of change of, and selects one clock signal from a plurality of clock signals based on the sampling,
(C) A video signal control circuit comprising a video signal output circuit for sampling a video signal according to a selected clock signal. 2. The video signal control circuit according to claim 1, wherein the clock signal selected by the clock signal selection circuit is set by a combination of sampling values of a plurality of clock signals having different phases at the time when the signal of the video signal changes. . 3. The clock signal selected by the clock signal selection circuit is 1 / th of the video signal from the time when the video signal changes.
2. The video signal control circuit according to claim 1, wherein the clock signal is a clock signal in which the signal changes within a section in which the phase relationship between the video signal and the clock signal is the same around the time point of the phase difference of 4 cycles.