JPH10200401A - Phase adjusting circuit and control signal generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase adjusting circuit whose adjusting range and adjusting sensitivity are constant and whose linearity and stability are satisfactory without depending on a clock frequency that controls the device of an object to be adjusted and also a control signal generating circuit which generates a control signal whose linearity and stability are satisfactory. SOLUTION: This device consists of a ring voltage controlled oscillator circuit comprising n-stage variable delay circuits (VD1 to VD4), a control signal generating circuit 102 that weights n+1 pieces of outputs v1 to v5 which are fetched from the voltage control oscillator circuit with phase control signal voltage Vcp and performs phase control and a phase-locked loop(PLL) means which compares the output v5 of the voltage control oscillator circuit with an external pixel clock PCLK1 and locks phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase adjustment circuit, and more particularly, to a phase adjustment circuit having a constant adjustment range and adjustment sensitivity regardless of a clock frequency for controlling a device to be adjusted, and having good linearity and stability of adjustment. The present invention relates to a phase adjustment circuit.

The present invention also relates to a control signal generation circuit for selectively generating a plurality of analog-interpolated control signals which are selectively used in phase adjustment or the like, and more particularly to a control signal generation circuit for controlling the linearity and stability of the generated control signal. The present invention relates to a good control signal generation circuit.

[0003]

2. Description of the Related Art In recent years, in electronic devices such as personal computers and workstations, a display as a display means is a flat panel display represented by a CRT (Cathode Ray Tube: CRT) to an LCD (Liquid Crystal Device). There is a flow to be replaced. In addition, conventional OHP (Over Head
Projector-type projectors that can be directly connected as personal computer displays instead of presentations by Projectors are becoming common. Many of such projectors use an LCD.

[0004] Since these displays use the same interface and connection method as CRT displays, signals are transmitted by analog RGB in their current usage. In the future, digital transmission is of course conceivable. However, while CRT displays are mainstream, analog RGB transmission must be assumed.

On the other hand, a flat panel display represented by an LCD is different from a CRT display in that pixels are composed of independent units and have a discrete structure. Therefore, a signal transmitted in analog is sampled again. It needs to be converted to a discrete signal. Originally, signals from personal computers are discrete signals,
It is very wasteful to convert this into a continuous signal and sample it, but it is inevitable as long as the assumption of borrowing the interface of the CRT display is made.

FIG. 14 shows a personal computer 50.
FIG. 2 is a configuration diagram of a system (first conventional example) when display output data from 0 is output to an LCD display 600. Video RAM in personal computer 500
(Video RAM) The display output digital data held in the 501 is converted into a digital to analog converter (DAC).
The signal is converted into an analog RGB signal by a D / A converter (502) 502 and transmitted to the LCD display 600 via the analog RGB cable 510.

[0007] In the LCD display 600, the received analog RGB signals are processed by the first signal processing unit 601.
After performing γ correction processing for correcting the non-linear characteristic of the LCD element, processing such as luminance and contrast, and sampling by a sample and hold circuit (S / H) 602, the signal is converted into a parallel signal by a second signal processing unit 603, and the The panel 604 is driven.

Here, the time corresponding to one pixel is called a pixel clock, and is about 20 to 100 [MHz]. In addition, elements constituting the LCD panel 604 have several structures. For example, STN (Super Twisted Nemaic)
Type or a TFT (Thin Film Transistor) type in which a thin film transistor is provided for each liquid crystal element.
Among the FT types, there are a type using amorphous silicon and a type using polycrystalline silicon.

Since the TFT type using polycrystalline silicon can operate at a relatively high speed, for example, a viewfinder attached to a video camcorder or an LCD panel of at most 200,000 [pixels] such as a small liquid crystal monitor is used. In the case of, the signal can be read as it is based on the pixel clock. However, the monitor of the personal computer 500 has at least 300,000 [pixels], and the frame frequency is considerably higher than the television signal. Therefore, regardless of the structure, a signal is input as it is based on such a high-speed clock, and L
It cannot be displayed on the CD panel 604. For example,
In a TFT type using amorphous silicon, a signal for one horizontal scanning line is temporarily converted into a parallel signal, and a signal is written for each row.

In a TFT type using polycrystalline silicon capable of relatively high-speed operation, a signal transmitted at a pixel clock frequency is converted into, for example, 2 to 12 parallel signals, and a clock used for reading is used. The frequency is dropped and input to the liquid crystal panel 604. These processes are performed by the sample and hold circuit 602 and the second signal processing unit 603.

FIG. 15 shows display output data from the personal computer 500 on an LCD display 70.
FIG. 11 shows a configuration diagram of a system (second conventional example) having another configuration when outputting to 0. In this conventional example, an analog RGB signal transmitted from a personal computer 500 via an analog RGB cable 510 is converted to an ADC (Analog to Digital).
digital converter (A / D converter) 701, converts the signal again into a digital signal, performs γ correction and the like by the first signal processing unit 702, and then performs a plurality of DACs 703-1.
703-n is used to drive the LCD panel 704 by obtaining a parallel signal with a reduced clock frequency.

Next, the sample and hold (S
/ H) The importance of the timing of the sampling operation / holding operation in the circuit 602 will be described. FIG. 16 shows a timing chart of each signal in the system of the first conventional example.

DAC 5 of personal computer 500
02, as shown in FIGS. 16 (a) and (b),
It is assumed that the output changes at the rising edge of the pixel clock. Here, the output of the DAC 502 is ideally a step-like waveform output as shown by a dotted line in FIG. 16B. However, due to the performance of the DAC 502 and the influence of the input / output circuit, the interface cable, and the like, for example, The waveform becomes blunt as shown by the solid line in FIG. The rounding in the figure is simple due to the first-order time constant, but actually becomes a more complicated waveform such as a waveform with overshoot. In addition, the waveform distortion due to the dullness becomes relatively severe as the pixel clock is higher and the monitor is higher in definition.

The output of the DAC 502 is supplied to a sample-and-hold circuit 601 (ADC 701 in the second conventional example).
Is resampled by
If the trailing edge of the output data of the DAC 502 can be sampled successfully at the timing shown as the first S / H pulse (first sample and hold pulse) in (c), the output will be relatively faithful to the original signal. However, FIG.
If the leading edge of the output data of the DAC 502 is sampled at the timing shown by the second S / H pulse (second sample hold pulse) in (d), the output will be significantly different from the original waveform. .

[0015] Such a phenomenon is peculiar to computer image output. That is, a dot or thin line of one pixel on a white background or an image obtained by inverting the dot or thin line is extremely common in a text image or a graphic screen. Such a phenomenon does not occur in an image captured from a camera.

By the way, it is not practically possible to properly manage the timing as shown in FIG.
That is, since the pixel clock is not supplied from the personal computer 500 side, the LCD display 6
At 00, the pixel clock is usually reproduced based on the horizontal synchronization signal. On the other hand, the personal computer 500 does not manage the phase of the pixel clock of the DAC 502 and the phase of the horizontal synchronization signal.
The pixel clocks on the LCD and display sides are generated independently of each other. Even if it is attempted to manage, for example, when the pixel clock is close to 100 [MHz], if the required accuracy is expressed in time, it is 1-2.
[Ns]. Therefore, the management becomes very difficult, and even if it becomes possible, several tens [k] is required on the LCD display 600 side.
Reproducing a pixel clock with an accuracy of 1-2 [ns] from a horizontal synchronizing signal of about [Hz] involves considerable difficulty.

After all, at present, the LCD display 6
A manual phase adjustment is provided on the 00 side, and the phase is appropriately adjusted while checking the image quality. Conventionally, as a means for changing the phase, means constituted by a polarity inversion circuit and a variable delay circuit has been used. In a very simple device, there is a device that performs only polarity reversal, but it is not satisfactory in image quality.

FIG. 17 shows an example of a typical variable delay circuit using a bipolar transistor circuit. Basically,
This is a configuration of a buffer using a differential type CML (Current Mode Logic) logic circuit. Emitter followers Q1 and Q2
The delay time is controlled by inserting a capacitive element C between the emitters and controlling the current Ic with the control voltage Vc. The maximum value of the delay obtained by this circuit is
The theoretical limit is 180 [°] in terms of phase. Therefore, a configuration in which at least two stages are connected in series is necessary to secure an adjustment range of 180 °. The adjustment range is narrow because the pixel clock changes and the change width of the control current Ic cannot be made very wide. Therefore,
In practice, a configuration in which at least four to eight stages are connected in series is required.

[0019]

However, there are some problems in the phase adjustment using such a conventional variable delay circuit. First, in order to support several types of display modes such as a multi-scan display, the pixel clock needs to be changed over a wide range.

Second, the linearity of the control characteristics is very poor.
For example, the variable delay circuit shown in FIG. 17 is basically a circuit whose delay time is inversely proportional to the control current Ic, which is one of the reasons for deteriorating the linearity. Due to the delay time of the differential buffers of Q3 and Q4, even if the control current Ic is increased, the delay time does not decrease in inverse proportion thereto.
Note that this phenomenon becomes remarkable especially when the pixel clock becomes high.

Third, the purpose of the phase adjustment circuit is to adjust the phase with high accuracy. The variable delay circuit, which is a component of the phase adjustment circuit, sets the delay time. This means that when the pixel clock changes, the phase and its adjustment range greatly change. That is, a large change in the adjustment sensitivity means that, for example, when the phase adjustment data is to be given as digital data, the resolution must be increased unnecessarily from the original adjustment accuracy. is there.

Fourth, in the conventional phase adjustment circuit,
From the viewpoint of power supply voltage dependence and temperature dependence, it is difficult to obtain stable characteristics.

The present invention has been made in view of the above-described conventional circumstances, and has a constant adjustment range and adjustment sensitivity irrespective of a clock frequency (pixel clock frequency) for controlling a device to be adjusted. It is an object of the present invention to provide a phase adjustment circuit having good characteristics and stability.

Another object of the present invention is to provide a control signal generating circuit for selectively generating a plurality of analog-interpolated control signals which are selectively used in phase adjustment or the like. It is to provide a good control signal generation circuit.

[0025]

In order to solve the above-mentioned problems, a phase adjustment circuit according to the present invention comprises n stages (n
Is a positive integer), a voltage-controlled oscillation circuit that negatively feeds back the output of the last-stage variable delay circuit to the input of the first-stage variable delay circuit, and the output of the voltage-controlled oscillation circuit and an external supply. Phase locked loop means for comparing the phase with the clock, outputting a delay control signal, controlling the delay time in the variable delay circuit at each stage of the voltage controlled oscillation circuit, and locking the phase, and a phase supplied from the outside. Outputting k (k is an integer of at least 3) weighting coefficient signals based on the control signal, wherein the weighting coefficient signal is given a maximum coefficient at substantially equal intervals with respect to the phase control signal. A control signal generating circuit that interpolates the intermediate section so that the sum of the weighting coefficients is substantially constant; and k signals having substantially the same phase difference extracted from the variable delay circuits at each stage in the voltage controlled oscillation circuit. k of the control signal generating circuit outputs
And a weighting means for weighting each of the weighting coefficient signals and outputting the result as an output signal of the phase adjustment circuit.

Further, in the phase adjustment circuit according to the present invention, the control signal generation circuit includes a pair of common emitter differential transistors to which emitters of first and second transistors are connected, and a common emitter of the pair of common emitter differential transistors. And k-1 sets of current sources connected to the
The first weighting coefficient signal output is taken from the collector of the first transistor of the first common emitter differential transistor pair, and the kth signal is output from the collector of the second transistor of the (k-1) th common emitter differential transistor pair. The weighted coefficient signal output is extracted, and the collector of the second transistor of the i-th (i is 1 or more and k-2 or less) common emitter differential transistor pair is the (i + 1) th emitter common differential transistor pair. Of the i-th common emitter differential transistor pair from the collector of the second transistor of the i-th common emitter differential transistor pair.
The weighted coefficient signal output is taken out, the phase control signal is supplied to the base of one of the first and second transistors of the k-1 common emitter differential transistor pair, and the base of the other transistor is supplied to the base of the other transistor. And a voltage obtained by roughly equally dividing the first and second reference potentials into k-1 pieces.

Further, the phase adjustment circuit of the present invention includes the variable delay circuit including a transistor, and a current source connected to an emitter of the transistor and controlled by a delay control signal from the phase locked loop means. A CML buffer circuit including two emitter follower circuits, a pair of emitter-common differential transistors connecting the emitters of the second and third transistors, and an emitter between the respective transistors of the two emitter follower circuits. And a connected capacitive element.

Further, in the phase adjusting circuit according to the present invention, the number k of weighted coefficient signals or the number of substantially equal phase difference signals extracted from the voltage controlled oscillation circuit is equal to n + 1, and Is approximately equal phase difference signal 1
80 ° is divided into n equal parts, and the (n + 1) th roughly equal phase difference signal has a phase opposite to that of the first roughly equal phase difference signal.

Further, in the phase adjustment circuit according to the present invention, the number of weighting coefficient signals or the number of approximately equal phase difference signals extracted from the voltage controlled oscillation circuit is equal to 2 · n + 1, and The arrangement of the phases of the substantially equal phase difference signals up to the n-th is so divided as to divide 360 ° into n,
The + 1st roughly equal phase difference signal has the same phase as the first roughly equal phase difference signal.

Further, the control signal generation circuit of the present invention has a first
And k-1 pairs (k is a positive integer) of a common emitter differential transistor pair to which the emitters of the second transistor are connected and a current source connected to the common emitter of the common emitter differential transistor pair. Then, the first weighting coefficient signal output is extracted from the collector of the first transistor of the first emitter common differential transistor pair, and
The k-th weighting coefficient signal output is taken out from the collector of the second transistor of the -1st emitter common differential transistor pair, and the ith (i is 1 or more and k-2 or less) signal is output.
The collector of the second transistor of the common emitter differential transistor pair is connected to the collector of the first transistor of the (i + 1) -th common emitter differential transistor pair;
The (i + 1) th weighted coefficient signal output is taken out from the collector of the second transistor of the i-th common emitter differential transistor pair, and the first and second of the k-1 common emitter differential transistor pairs are taken out. A phase control signal is supplied to the base of one of the transistors, and the first and second reference potentials are applied to the base of the other transistor by k.
-1 is supplied with a voltage approximately equally divided.

Further, the control signal generation circuit of the present invention
K-2 current sources respectively connected to the (k-1) th to (k-1) th weighted coefficient signal outputs, and for each of the k-1 emitter common differential transistor pairs, the base of the first transistor Is supplied with a voltage obtained by substantially equally dividing the first and second reference potentials into k−1,
The above-mentioned phase control signal is supplied to the base of the transistor.

Further, the control signal generating circuit according to the present invention includes k current sources connected to all k weighting coefficient signal outputs, respectively, wherein each of the k-1 emitter common differential transistor pairs is provided. , The phase control signal is supplied to the base of the first transistor, and a voltage obtained by substantially equally dividing the first and second reference potentials into k−1 is supplied to the base of the second transistor. is there.

For example, when a discrete signal such as an image signal from a personal computer is input to a drive circuit of an LCD display device, it is very important where to sample the signal. Adjusting the phase of the signal and the sample pulse is essential.
In the control signal generation circuit and the phase adjustment circuit using the same according to the present invention, a plurality of signals having substantially equal phase differences are generated by a ring-type voltage controlled oscillation circuit, and external phase control is performed on the signals having substantially equal phase differences. The weighting coefficient signal controlled by the signal is weighted, and the phase is adjusted based on the weighted result, so that the adjustment sensitivity and the adjustment range can be kept constant regardless of the pixel clock frequency, and the adjustment linearity and It is possible to improve the stability.

That is, in the phase adjustment circuit of the present invention, an adjustment range of 0 to 360 [°] can always be obtained irrespective of the pixel clock. Since the required number of stages of the variable delay circuit does not increase, it is particularly suitable for a case where it corresponds to several kinds of display modes such as a multi-scan display.

Further, the control signal generating circuit of the present invention and the phase adjusting circuit using the same have good linearity of the control characteristics. This is because a maximum coefficient is given to the phase control signal at substantially equal intervals, and a weighting coefficient signal is generated by interpolating an intermediate section so that the sum thereof is substantially constant. This is because the signal is switched.

Further, in the phase adjusting circuit of the present invention, not the delay time but the phase is controlled. Therefore, even if the pixel clock frequency changes, the control sensitivity does not change. If the data is passed as digital data, the resolution will be minimal.

Further, the phase adjustment circuit of the present invention is stable against temperature and power supply voltage fluctuations. This is because the delay time of the variable delay circuit is automatically adjusted by the phase locked loop (PLL) means so as to correspond to the phase (external clock) of the pixel clock.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a phase adjustment circuit and a control signal generation circuit according to the present invention will be described below. [Summary of the Invention], [First Embodiment of Phase Adjustment Circuit], [Second Embodiment of Phase Adjustment Circuit] , [Embodiment of the control signal generation circuit] will be described in detail with reference to the drawings.

[Outline of the Invention] FIG. 1 shows a schematic configuration diagram of a phase adjustment circuit according to the present invention. The phase adjustment circuit of the present invention is composed of three main elements. That is, the phase of a ring-type voltage-controlled oscillation circuit including an n-stage (n = 4 in FIG. 1) variable delay circuit and n + 1 outputs (v1 to v5) extracted from the ring-type voltage-controlled oscillation circuit are determined. A control signal generating circuit 102 for performing phase control by weighting with a control signal voltage Vcp, an output (v5) of a ring-type voltage controlled oscillator, and an external pixel clock PCLK1
And a phase locked loop (PL
L) means.

First, the voltage-controlled oscillation circuit connects n stages of variable delay circuits VD1 to VD4 in series, and inverts the phase of the output v5 of the last stage variable delay circuit VD4 by the inverter 111 to generate the first stage variable delay circuit VD1. It can be configured by performing negative feedback as the input v1. As the variable delay circuits VD1 to VD4, CML as shown in FIG.
The configuration using the buffer of the logic circuit is suitable for high-speed operation,
This is one of the most suitable realizing means because the circuit configuration is simple.

The number n of stages is a variable delay circuit as shown in FIG.
When a buffer of a CML logic circuit as shown in FIG. 7 is used, it is appropriate to select at least three or four stages.
This is because the two stages have only two time constants, so that safe oscillation cannot be performed. In the configuration example of FIG. 1, the number is set to four.

Further, a phase-locked loop means (in the figure, Phase
Det LPF) 101 includes a phase comparator that compares the phase of the output v5 of the voltage controlled oscillation circuit with the external pixel clock PCLK1 supplied from the outside, and a low-pass filter that outputs a delay control signal Vcf based on the comparison result. At least a variable delay circuit VD of each stage of the voltage controlled oscillator circuit.
The delay time in 1 to VD4 is controlled to lock the phase.

Consider the output phase at each stage of the variable delay circuit when the phase adjustment circuit having the configuration shown in FIG. 1 is phase-synchronized with the external pixel clock PCLK1. First, the input v1 of the first stage and the output v5 of the fourth stage must have opposite phases. The output v1 of the first stage to the output v4 of the fourth stage
Until, there must be a constant phase transition corresponding to τ (Vcf), so that the phase arrangement is as shown in FIG. That is, the phase arrangement is such that the phase plane of 0 to 180 [°] is divided into n.

For an arbitrary n-stage variable delay circuit, 0
It is as if the phase plane of -180 [°] was divided into n. The output point for weighting the variable delay circuit of n stages is (n + 1)
In the case of the configuration example of FIG. 1, outputs v1 to v5 must be obtained, and outputs v1 and v (n +
It is necessary that 1) be out of phase. Otherwise, 0 ~
The adjustment range of 180 [°] cannot be secured.

Next, the control signal generation circuit 102 will be described. The control signal generation circuit 102 controls the phase control voltage Vcp
, Weighting coefficients having weights as shown in FIG. 3 are generated, and k (k = n + 1 = 5 in FIG. 1) weighting coefficient signals K1 to K5 to be supplied to the weighting circuits W1 to W5 are set. I do. That is, the maximum coefficient is given to the phase control voltage Vcp at substantially equal intervals from the weighting coefficient signal K1 to the weighting coefficient signal K5, and the intermediate section is analog-interpolated so that the sum of the weighting coefficients is substantially constant. I will switch.

As a result, in the configuration shown in FIG. 1, the k weighted signals v1 to v5 having substantially the same phase difference extracted from the variable delay circuits VD1 to VD4 at each stage in the voltage controlled oscillation circuit by the weighting circuits W1 to W5. , Control signal generation circuit 102
The internal clock PCLK2 output by weighting the k weighting coefficient signals K1 to K5 output as the output signal of the phase adjustment circuit can be arbitrarily changed in the range of 0 to 180 [°]. Actually, 0-360
Although an adjustment range of [°] is required, in FIG. 1, an inverting circuit may be inserted at, for example, the input terminal position of the external pixel clock PCLK1 or the output terminal position of the internal clock PCLK2, and the switching may be performed in combination.

[First Embodiment of Phase Adjustment Circuit] Next, a more specific configuration example of the phase adjustment circuit according to the first embodiment of the present invention will be described. The basic configuration is shown in FIG. 1, and the main components of the variable delay circuit and the weighting circuit are shown in FIG. 4 and the control signal generation circuit 102 is shown in FIG. Show.

FIG. 4 is a circuit diagram of a variable delay circuit and a weighting circuit constituting a ring-type voltage controlled oscillation circuit.
In FIG. 4, the variable delay circuit includes two stages of variable delay circuits and has three outputs. The first-stage variable delay circuit includes NPN transistors (emitter followers) Q1 and Q2 and a capacitor C1. Its output includes a common emitter differential NPN transistor pair Q serving as an output extraction circuit (weighting circuit) having a weighting function.
3 and Q4, and CML gate circuits Q5 and Q6 for driving a variable delay circuit at the next stage. An emitter common differential NPN transistor pair Q3 and Q4 serving as an output extraction circuit (weighting circuit) is weighted by the weighting current Iw1 supplied from the control signal generation circuit 102, and the output Io1 is output.
And Io1X.

The variable delay circuit of the second stage is also basically the first variable delay circuit.
It has the same configuration as the variable delay circuit at the stage,
The point is that a set of output extraction circuits (weighting circuits) is provided. That is, two sets of outputs Io2, Io2X, Io3, and Io3X weighted by the weighted currents Iw2, Iw3, respectively, are extracted from the two sets of emitter common differential NPN transistor pairs Q9, Q10, Q11, and Q12.

FIG. 5 is a diagram showing a configuration in which a ring-type voltage-controlled oscillation circuit and a weighting circuit are formed by using two configurations of the variable delay circuit and the weighting circuit of FIG. Since the variable delay circuits VD1 to VD4 have a differential input / output configuration as shown in FIG. 4, the feedback from the last variable delay circuit VD4 to the first variable delay circuit VD1 requires the inverter 1 shown in FIG.
Step 11 is unnecessary, and it is sufficient to simply exchange the differential output and feed back.

In the left block 201, the emitter-common differential NPN transistor pair Q3 and Q in FIG.
4 corresponds to the weighting circuit W2.
Similarly, an output extraction circuit including the common emitter differential NPN transistor pair Q9 and Q10 corresponds to the weighting circuit W3. Further, the other output extraction circuits Q13 and Q14 provided in the second stage are connected to a phase locked loop (PLL).
L) It is used as a comparison output for forming a loop of the means.

In the right block 202, the common emitter differential NPN transistor pair Q3 and Q in FIG.
4 corresponds to the weighting circuit W4.
The two sets of output extraction circuits Q9 and Q10 and Q11 and Q12 provided in the second stage are weighting circuits W1,
Used as W5. The inputs of the weighting circuits W1 and W5 are simply inverted in phase. Therefore, only the outputs Io3 and Io3X are inverted with respect to the other outputs to output the internal pixel clock output terminals PCLK2 and PCLK2.
Connected to X.

Next, a specific circuit configuration of the control signal generation circuit 102 will be described. FIG. 6 shows a control signal generation circuit 1
FIG. 2 is a specific circuit configuration diagram of No. 02. In FIG. 6, a control signal generating circuit 102 includes four sets of emitter common differential NPNs.
It includes transistor pairs P1 and P2, P3 and P4, P5 and P6, and P7 and P8. At the bases of the first transistors P1, P3, P5 and P7 of each emitter common differential NPN transistor pair, three reference voltages VH and VL on the high potential side and three low potential sides are provided. Are equally divided by the resistors RD1, RD2, and RD3. Further, a phase control voltage Vcp is applied to the bases of the second transistors P2, P4, P6 and P8.

From the collector of the first transistor P1 of the first emitter common differential NPN transistor pair, the first
The fifth weighting coefficient signal output IK1 is taken out, the fifth weighting coefficient signal output IK5 is taken out from the collector of the second transistor P8 of the fourth emitter common differential NPN transistor pair, and the i-th (i is The collectors of the second transistors P2, P4 and P6 of the common emitter differential NPN transistor pair (1 or more and 3 or less)
The collectors of the second transistors P2, P4 and P6 of the i-th common emitter differential NPN transistor pair are respectively connected to the collectors of the first transistors P3, P5 and P7 of the i-th common emitter differential NPN transistor pair. From the (i + 1) th weighted coefficient signal output IK2, IK
K3 and IK4 are respectively extracted.

Here, a potential difference obtained by dividing the two reference potentials VL and VH into three is defined as ΔV. As a result, the threshold value at which the collector currents of the first and second transistors of each emitter common differential NPN transistor pair cross each other is shifted by a potential difference ΔV. Assuming that the collector currents of the respective transistors are IQ1 to IQ8, they exhibit characteristics as shown in FIG. 7 with respect to the phase control voltage Vcp. Note that I2 in the drawing is a current supplied by each of the current sources JS1 to JS7.

Further, as shown in the circuit configuration of FIG. 6, when the transistors P2 and P3, P4 and P5, and P6 and P7 are connected, and the offset of the current I2 by the current source is subtracted, each of the weighting coefficient signals IK1 to IK1 The current flowing into the IK 5 has characteristics as shown in FIG. 8, and it can be seen that the desired characteristics described with the characteristics in FIG. 3 in the configuration example in FIG. 1 can be realized. For example, the transistor P
The collector current IQ3 of the transistor P2 and the collector current IQ3 of the transistor P3 move differentially, but by shifting the threshold value by the potential difference ΔV, the weighting coefficient signal IK2 can be generated almost during the potential difference ΔV.

Next, a modification of the phase adjustment circuit of the present embodiment will be described. In the first embodiment described above, the comparison output to the phase locked loop (PLL) means is extracted from a certain stage of the variable delay circuits VD1 to VD4, weighted by the output extraction circuit of each stage, and the combined output is output to the second stage. Is used as the pixel clock PCLK2, but this does not change its function at all even if it is replaced.

In the first embodiment, the phase control voltage Vcp
Range from 0 to 180 [°], and the adjustment range of 0 to 360 [°] is obtained by using the phase switching circuit together. However, the adjustment range of 0 to 360 [°] is continuously obtained. It can also be configured as follows. FIG. 9 shows the principle. If a control signal generating circuit having signals having phases of v6 to v9 and having nine outputs is prepared,
An adjustment range of 60 [°] can be obtained continuously. v
A signal having a phase of 6 to v9 can be easily created using the signals of v1 to v4. However, in this configuration,
Although there is a feature that 360 [°] can be continuously obtained, the circuit scale increases accordingly.

In Embodiment 1, FIGS.
The ring-type voltage-controlled oscillation circuit described above uses four stages of variable delay circuits with two sets of emitter followers in each of which a capacitor is arranged between the emitters. Oscillates. That is, the variable delay circuit has three stages, and the phase arrangement of the signal in FIG.
The circuit scale can be reduced by setting the interval at 60 [°] instead of the interval at 5 [°].

[Second Embodiment of Phase Adjustment Circuit] The output v2 of the first-stage variable delay circuit and the output v4 of the third-stage variable delay circuit in FIG.
Can be thinned out, and phase synthesis can be performed using signals at intervals of 90 [°]. The phase control circuit according to the second embodiment of the present invention has a configuration realizing this.

FIG. 10 is a circuit configuration diagram of a variable delay circuit and a weighting circuit constituting the ring-type voltage controlled oscillation circuit according to the second embodiment. This is a configuration in which the output extraction circuit using the common emitter differential NPN transistor pair Q3 and Q4 in the first embodiment (FIG. 4) is omitted. Further, the entire configuration of the ring-type voltage controlled oscillation circuit and the weighting circuit is as shown in FIG. In other words, with the elimination of the output extraction circuit by the emitter-common differential NPN transistor pair Q3 and Q4, the control signal generation circuit is changed from five outputs to three outputs, so that it can be simplified as shown in FIG. Becomes
10, 11, and 12, FIG. 4, FIG.
6 (Embodiment 1) are denoted by the same reference numerals, and description thereof is omitted.

The advantage of the large number of stages of the weighting circuit is shown in FIG.
The overlap characteristics of the respective control outputs (weighting coefficient signals K1 to K5) shown in (1) have a small effect on the linearity of the control characteristics and the output amplitude. However, they are not an essential problem, and if the overlap characteristics are carefully designed, 90 [°] as in the present embodiment.
Even with the stepped phase arrangement, it is possible to realize characteristics without any problem.

Next, the number of stages of the variable delay circuit (n: n is a positive integer) and the number of roughly equal phase difference signals or weighting coefficient signals (k: k is a positive integer) taken out from the voltage controlled oscillator are generally described. Become

When the continuous adjustment range is set to 180 [°], there is a relation of k = n + 1, and the step of the phase is 180 / n.
At every [°], the output phase of the first variable delay circuit and the output phase of the k-th variable delay circuit become opposite phases. Also,
When the continuous adjustment range is 360 [°], k = 2 ·
It has a relationship of n + 1, and the phase is 360 / n [°], and the output phase of the first variable delay circuit and the output phase of the k-th variable delay circuit are in phase.

As described above, Embodiments 1 and 2
In the phase adjustment circuit of FIG.
1 to VD4), a plurality of signals v1 to v having substantially the same phase difference.
5 are generated, and for the roughly equal phase difference signals v1 to v5,
The weighting coefficient signals K1 to K5 controlled by the external phase control signal Vcp are weighted, and the weighted result PCLK
2, the adjustment sensitivity and the adjustment range can be kept constant irrespective of the pixel clock frequency, and the linearity and stability of the adjustment can be improved.

That is, an adjustment range of 0 to 360 [°] can always be obtained irrespective of the pixel clock, and even if the pixel clock changes over a wide range, the required number of stages of the variable delay circuit increases as in the prior art. This is particularly suitable for supporting several types of display modes such as a multi-scan display. Further, in the phase adjustment circuit and the control signal generation circuit of the present embodiment, the control characteristics have good linearity. This is because a maximum coefficient is given to the phase control signal Vcp at substantially equal intervals, and while the intermediate section is interpolated so that the sum thereof is substantially constant, the weighted coefficient signals K1 to K5 are generated. Are the weighting coefficient signals K1 to K5
Is switched. Also, in the phase adjustment circuit of the present embodiment, not the delay time but the phase is controlled,
Even if the pixel clock frequency changes, the control sensitivity does not change. Therefore, in combination with the good linearity, the resolution can be minimized when the adjustment data is passed as digital data. Furthermore, the phase adjustment circuit of the present embodiment is stable against temperature and power supply voltage fluctuations. this is,
This is because the delay time of the variable delay circuit is automatically adjusted by the phase locked loop (PLL) means so as to correspond to the phase of the pixel clock (external clock PCLK1).

[Embodiment of Control Signal Generating Circuit] The embodiment of the control signal generating circuit according to the present invention is, for example, as shown in FIG.
The configuration is as shown in FIG. The control signal generation circuit according to the present invention is applicable not only to the adjustment of the phase of the pixel clock of the LCD display, but also to various uses for selecting a plurality of signals while performing analog interpolation.

The control signal generating circuit shown in FIG.
The control current IK 1
To IK5, but depending on the application, the control current flowing in the direction from the control signal generation circuit may be more convenient. FIG. 13 is a circuit configuration diagram of a signal generation circuit that generates control currents IK1 to IK5 in a direction flowing out of the control signal generation circuit. In the figure, parts that are the same as in FIG. 6 (Embodiment 1) are assigned the same reference numerals, and descriptions thereof are omitted.

FIG. 13 differs from FIG. 6 in that the first and second transistors T1 and T2, T3 and T4, T5 and T5 of each emitter-coupled differential NPN transistor pair are different.
6, the voltages applied to the bases of T7 and T8 are reversed, and all control signal outputs IK1-IK
5 is connected to a current source for supplying the current I2.

That is, in FIG. 13, k current sources KS0, KS2, KS4, KS6 and KS connected to all k (k = 5) control signal outputs IK1 to IK5, respectively.
8 for each of the k−1 emitter-common differential NPN transistor pairs.
3, the phase control signal Vcp is supplied to the bases of T5 and T7, and the bases of the second transistors T2, T4, T6 and T8 are connected to the first by resistors RV1, RV2 and RV3.
Of the reference potential VH and the second reference potential VL are equally divided into k-1 pieces.

[0071]

As described above, according to the control signal generating circuit and the phase adjusting circuit using the same according to the present invention, a plurality of signals having substantially the same phase difference are generated by the voltage controlled oscillation circuit. The phase difference signal is weighted by the weighting coefficient signal controlled by the external phase control signal, and the phase is adjusted based on the weighted result, so that the adjustment sensitivity and the adjustment range are kept constant regardless of the pixel clock frequency. Therefore, the linearity and stability of the adjustment can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a phase adjustment circuit according to the present invention.

FIG. 2 is an explanatory diagram illustrating an output phase arrangement in each stage of a variable delay circuit.

FIG. 3 shows a phase control voltage Vcp of weighting coefficient signals K1 to K5.
FIG. 4 is an explanatory diagram showing characteristics with respect to FIG.

FIG. 4 is a circuit configuration diagram of a variable delay circuit and a weighting circuit that constitute the ring-type voltage controlled oscillation circuit according to the first embodiment.

5 is a configuration diagram in a case where a ring-type voltage controlled oscillation circuit and a weighting circuit are configured using two circuits of the configuration of FIG. 4;

FIG. 6 is a specific circuit configuration diagram of a control signal generation circuit according to the first embodiment.

FIG. 7 is an explanatory diagram showing characteristics of collector currents IQ1 to IQ8 of respective transistors in a control signal generation circuit with respect to a phase control voltage Vcp.

FIG. 8 is a diagram showing a phase control voltage V of a current flowing into each of the weighting coefficient signals IK1 to IK5 from which an offset caused by a current source is subtracted.
FIG. 4 is an explanatory diagram showing characteristics for cp.

FIG. 9 is an explanatory diagram illustrating the phase arrangement of the output at each stage of the variable delay circuit when the adjustment range of 0 to 360 [°] is continuously obtained.

FIG. 10 is a circuit configuration diagram of a variable delay circuit and a weighting circuit that constitute the ring-type voltage controlled oscillation circuit according to the second embodiment.

11 is a configuration diagram in a case where a ring-type voltage controlled oscillation circuit and a weighting circuit are configured using two circuits of the configuration of FIG. 10;

FIG. 12 is a specific circuit configuration diagram of a control signal generation circuit according to a second embodiment.

FIG. 13 is a circuit configuration diagram of a signal generation circuit that generates control currents IK1 to IK5 in a direction flowing out of the control signal generation circuit.

FIG. 14 is a configuration diagram of a system (first conventional example) for outputting display output data from a personal computer to an LCD display.

FIG. 15 is a configuration diagram of a system (second conventional example) for outputting display output data from a personal computer to an LCD display.

FIG. 16 is a timing chart of each signal in the system of the first conventional example.

FIG. 17 is a circuit diagram of a typical variable delay circuit using a bipolar transistor circuit.

[Explanation of symbols]

VD1 to VD4: variable delay circuit, 101: phase locked loop means, 102: control signal generation circuit, W1 to W5: weighting circuit, 111: inverter, PCLK1: external pixel clock (external clock), PCLK2: output of phase adjustment circuit (Internal clock), Vcf... Delay control signal, v1 to v
5. Output of variable delay circuit (signal of approximately equal phase difference), Vc
p: phase control voltage, Q1 to Q14: NPN transistor, C1, C2: capacitive element, IS1 to IS7: current source,
R1 to R4: resistance, R11 to R14: resistance, Iw1 to I
w3: Weighted current, Io1 to Io3, Io1X to Io3X
... weighted output, Vcc ... power supply (potential), GND ... ground potential, IN, INX ... variable delay circuit input from previous stage, OU
T, OUTX: Variable delay circuit output to the next stage, P1 to P8
... NPN transistor, JS1 to JS7 ... current source, RD
1 to RD3: resistance, VH: high potential reference potential (first reference potential), VL: low potential reference potential (second reference potential), 201, 202, 211, 212 ... variable delay circuit and weighting circuit , T1 to T8... NPN transistors, KS0 to KS8... Current sources, RV1 to RV3.

Claims (8)

[Claims] 1. A voltage controlled oscillator circuit comprising an n-stage (n is a positive integer) variable delay circuit connected in series, and negatively feeding back the output of the last-stage variable delay circuit to the input of the first-stage variable delay circuit; The phase of the output of the voltage-controlled oscillation circuit is compared with the phase of a clock supplied from the outside, and a delay control signal is output to control the delay time in the variable delay circuit of each stage of the voltage-controlled oscillation circuit, thereby locking the phase. Means for outputting k (k is an integer of at least 3) weighting coefficient signals based on an externally supplied phase control signal, wherein the weighting coefficient signal is A maximum coefficient is given to the signal at substantially equal intervals, and a control signal generation circuit that interpolates an intermediate section so that the sum of the weighting coefficients is substantially constant, and a variable delay circuit at each stage in the voltage controlled oscillation circuit. Weighting means for respectively weighting the extracted k signals of approximately equal phase difference and the k weighting coefficient signals output by the control signal generation circuit and outputting the weighted signals as an output signal of the phase adjustment circuit; Having a phase adjustment circuit. 2. A control signal generating circuit comprising: a pair of common emitter differential transistors connected to emitters of first and second transistors; a current source connected to a common emitter of the pair of common emitter differential transistors;
The first weighting coefficient signal output is taken out from the collector of the first transistor of the first common emitter differential transistor pair, and the k-1st common emitter differential The k-th weighted coefficient signal output is taken from the collector of the second transistor of the transistor pair, and the output of the k-th weighted coefficient signal of the second transistor of the i-th (i is 1 or more and k-2 or less) common emitter differential transistor pair is obtained. The collector is connected to the collector of the first transistor of the (i + 1) -th common emitter differential transistor pair, and is connected to the collector of the second transistor of the i-th common emitter differential transistor pair from the collector of the second transistor.
A first weighted coefficient signal output is taken out, and the first of the k-1 emitter common differential transistor pairs is
The phase control signal is supplied to the base of one of the transistors and the second transistor, and a voltage obtained by substantially equally dividing the first and second reference potentials into k−1 is supplied to the base of the other transistor. Item 2. The phase adjustment circuit according to Item 1. 3. The variable delay circuit includes two emitter follower circuits each including a transistor, and a current source connected to an emitter of the transistor and controlled by a delay control signal from the phase locked loop means. CML with a common emitter differential transistor pair connecting the emitters of the second and third transistors
2. The phase adjustment circuit according to claim 1, further comprising: a buffer circuit; and a capacitance element connected between the emitters of the respective transistors of the two emitter follower circuits. 4. The number k of the weighted coefficient signals or the number of approximately equal phase difference signals extracted from the voltage controlled oscillator circuit.
Is equal to n + 1, and the phases of the first to n-th approximate equal phase difference signals are arranged so as to divide 180 ° into n equal parts, and the (n + 1) th approximate equal phase difference signal is the first approximate equal phase difference signal. 2. The phase adjustment circuit according to claim 1, wherein the phase adjustment circuit has a phase opposite to that of the equal phase difference signal. 5. The number k of the weighted coefficient signals or the number of approximately equal phase difference signals extracted from the voltage controlled oscillation circuit.
Is equal to 2 · n + 1, and the phases of the first to second · nth approximate equal phase difference signals are arranged so as to divide 360 ° into n equal parts. 2. The phase adjustment circuit according to claim 1, wherein the signal is in phase with the first substantially equal phase difference signal. 6. A set of k-1 pairs of a common-emitter differential transistor pair connecting the emitters of the first and second transistors and a current source connected to the common emitter of the common-emitter differential transistor pair (K is a positive integer), the first weighted coefficient signal output is taken out from the collector of the first transistor of the first pair of common emitter differential transistors, and the (k−1) th common emitter differential transistor The k-th weighted coefficient signal output is taken from the collector of the pair of second transistors, and the collector of the second transistor of the i-th (i is 1 or more and k-2 or less) common emitter differential transistor pair is extracted. Are connected to the collector of the first transistor of the (i + 1) -th common emitter differential transistor pair, and the second of the i-th common emitter differential transistor pair. The i-th from the collector of the transistor +
A first weighted coefficient signal output is taken out, and the first of the k-1 emitter common differential transistor pairs is
And a control signal in which a phase control signal is supplied to the base of one of the second and second transistors, and a voltage obtained by substantially equally dividing the first and second reference potentials into k−1 is supplied to the base of the other transistor. Generator circuit. 7. A semiconductor device comprising: k-2 current sources connected to the second to (k-1) th weighting coefficient signal outputs, respectively; 7. The base of the first transistor is supplied with a voltage obtained by substantially equally dividing the first and second reference potentials into k-1 pieces, and the phase control signal is supplied to the base of the second transistor. The control signal generation circuit according to any one of the preceding claims. 8. A semiconductor device comprising: k current sources respectively connected to all k weighting coefficient signal outputs; and for each of the k−1 emitter common differential transistor pairs, a base of the first transistor. 7. The control signal generating circuit according to claim 6, wherein the phase control signal is supplied, and a voltage obtained by substantially equally dividing the first and second reference potentials into k-1 pieces is supplied to the base of the second transistor.