JP3300813B2 - Color liquid crystal display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a color liquid crystal display device for A / D converting a video signal input from the outside and displaying the digitized image data on a liquid crystal panel.

[0002]

2. Description of the Related Art The purpose of a conventional color liquid crystal display device is to faithfully reproduce and display a video signal sent from the outside. To achieve that goal, P
A clock having the same frequency as the frequency of the video signal sent by the LL circuit (Phase Lock Loop) is internally generated, and sampling is performed at the most stable timing of one pixel of the video signal, and A / D conversion is performed. Clear images are reproduced. The improvement can be achieved by allowing the phase of the clock generated by the PLL circuit to be selected in several stages by the phase selection circuit and performing A / D conversion at the most stable sampling point. However, in recent years, liquid crystal display devices have also become full-color RGB.
It has a data amount of 8 bits each, and the least significant bit
It must be stable data even until. Further, since the video frequency has been increased, an optimum sampling point cannot be obtained by a phase switching method in which several stages are selected.
That is, unless the phase is continuously changed after the phase switching through the delay circuit selected in several stages, the optimum timing cannot be obtained.

[0003]

In the above-described conventional method of perceiving pixels, the transmitted video signal has a wide frequency range and a high speed, so that sampling at the true center position of one pixel is impossible. Was. Unless the phase is changed continuously by the phase switching method through the delay circuit, sampling at the center position cannot be performed. In addition, a simple circuit requires a continuous delay to the input horizontal synchronization signal instead of changing the phase of the generated clock so that the phase of the clock generated by the PLL circuit also changes continuously. I can't.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the conventional problems, and has an input horizontal synchronizing signal whose waveform is blunted by the time constant of CR and which is shaped by a CMOS gate IC. A color liquid crystal having a delay circuit that applies a continuously changing bias voltage to the smoothed waveform, converts the time into a continuous time change using a threshold level of a gate IC, and continuously converts a clock phase. A display device is proposed.

[0005]

According to the present invention, since the clock phase changes continuously by giving a continuous delay to the input horizontal synchronizing signal, sampling is performed at the center of the pixel and A /
D conversion is performed.

[0006]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an electrical block diagram showing the configuration of the present invention. The horizontal synchronization signal A input from the outside is input to the continuous delay circuit 2. The user presses the operation switch 12 to change the phase of the horizontal synchronizing signal, whereby the switch signal 11 is transmitted to the CPU 3. The CPU 3 supplies the D / A input data 9 to the D / A converter 1 according to the command of the switch signal 11. The D / A input data 9 is a digital quantity that changes continuously, and the D / A output signal 10 of the D / A converter 1 is input to the continuous delay circuit 2 based on the change. The D / A output signal 10 is a voltage that changes continuously,
A continuous delay signal C whose delay amount changes in accordance with the voltage change is output. The continuous delay signal C is input to a phase comparator 5 which is one of the components of the PLL circuit 4, and is compared in phase with an N counter output signal D generated by an N counter 7. The phase comparator 5 outputs the phase difference signal 13 and controls the voltage controlled oscillator 6 so that the phase difference becomes zero. The voltage controlled oscillator 6 changes the oscillation frequency in response to the phase difference signal 13 and generates a clock E synchronized with the video signal.
An externally input video signal F is input to an A / D converter 8 which converts the video signal F into digital data for display on a liquid crystal.

A clock E is inputted as a clock for converting the video signal for each pixel, and a sampling point is determined. The user can control the CPU so that the conversion timing becomes the most stable timing of one pixel, change the delay amount, and display an image with good display quality on the liquid crystal.

The delay operation of the continuous delay circuit according to the present invention will be described with reference to the continuous delay circuit diagram of FIG. 2 and the timing chart of FIG. The input video signal includes a horizontal synchronization signal A
Is sent. The horizontal synchronizing signal A has a waveform like the signal B with the time constants of R1 and C due to the integration circuit composed of R1 and C. A voltage that changes continuously from the output of the D / A converter is input to one of R2 and the other is connected to the connection point of the integration circuits R1 and C, thereby generating an integration signal B whose bias changes continuously. .

By inputting the integration signal B to the CMOS gate IC 15, the output changes to high or low at the threshold level of the CMOS gate IC15. That is, D / A
If the voltage of the converter output is high, the bias voltage is also high, resulting in a waveform a1, and the continuous delay signal C changes from low to high at the time of a2. If the voltage of the output of the D / A converter is low, the integrated signal B becomes b1 and the amount of delay increases, and the continuous delay signal C changes from low to high at the time of b2. The transition of the integration signal B from a1 to b1 is a continuous change amount, and the delay amount of the integration signal C is also continuous. The clock E generated by the PLL circuit 4 is delayed in the same manner as the continuous delay signal C and is subjected to A / D conversion at the optimal timing of the video signal F. Further, the time constant is determined by the resistor R1 and the capacitor C, which determines how the waveform is rounded.

Since the amount of bias from a1 to b1 is determined by the ratio of the resistors R2 and R1, the time constants of the resistors R1, R2 and the capacitor C are R1 = 1KΩ, R2 = 2KΩ in the experiment.
When C = 22 pF and the 74AC series is used for the CMOS IC, a delay of 30 nsec is obtained, which is appropriate for the delay of one pixel.

[0011]

As described above, a delay circuit that changes continuously can be realized with a simple circuit configuration, the user can select an optimal sampling timing, and there can be no flickering and an optimal display quality can be obtained. .

[Brief description of the drawings]

FIG. 1 is an electrical block diagram of the present invention.

FIG. 2 is a diagram of a continuous delay circuit

FIG. 3 Timing chart

[Explanation of symbols]

 Reference Signs List 1 D / A converter 2 Continuous delay circuit 3 CPU 4 PLL circuit 5 Phase comparator 6 Voltage controlled oscillator 7 N counter 8 A / D converter 9 D / A input data 10 D / A output signal 11 Switch signal 12 Operation switch 13th Phase difference signal 14 A / D output data 15 CMOS gate IC A Horizontal synchronization signal B Integration signal C Continuous delay signal DN counter output signal E Clock F Video signal

Claims (1)

(57) [Claims] 1. A waveform of an input horizontal synchronization signal is blunted by a time constant of CR, the signal is shaped by a CMOS gate IC, and a bias voltage that continuously changes to the blunted waveform is passed through a resistor. A color liquid crystal display device having a delay circuit for converting the voltage into a continuous time change using a threshold level of a gate IC.