JPH09258904A - Circuit for preventing sampling point deviation for a/d conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the sampling point of an A/D conversion circuit from deviating when the circuit delay quantity of a synchronous polarity discrimination/polarity inversion circuit drifts. SOLUTION: The A/D conversion circuit 10 converting an analog video signal into a digital video signal is provided with a circuit 16 for discriminating the polarity of an input horizontal synchronizing signal HD and making the polarity of the HD signal into either a positive electrode or a negative electrode, positive electrode, for example, a circuit 32 which exclusively OR-operates the signal HD and a discrimination signal and a PLL(phase locked loop) circuit 22 generating CLK for sampling in the A/D conversion circuit with the exclusive OR signal as a reference signal. The signal HD is inputted to the PLL circuit as the reference signal through the circuit 32 which does not have delay quantity without passing through the circuit 16 with large delay quantity. When delay quantity by the circuit 16 drifts owing to the change of a temperature, the phase of CLK for sampling, which is outputted from the PLL circuit 22, does not change and the sampling point of the A/D conversion circuit 10 is not deviated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention discriminates the polarity of an input horizontal synchronizing signal, and creates a clock by using a signal obtained by always processing the polarity of the input horizontal synchronizing signal as either a positive polarity or a negative polarity as a reference signal. The present invention relates to an A / D (analog / digital) conversion circuit for sampling an analog video signal with the created clock and converting it into a digital video signal.

[0002]

2. Description of the Related Art Conventionally, this type of A / D conversion circuit has been constructed as shown in FIG. That is, in the A / D conversion circuit 10, the analog RGB video signal input to the analog video signal input terminal 12 is converted into a digital RGB video signal by sampling with the clock CLK, and is output to the digital video signal output terminal 14. Is output.

When the input signal is a personal computer (personal computer), the polarity of the horizontal synchronizing signal may be positive or negative, and a synchronizing polarity discriminating and polarity inverting circuit provided so as to correspond to either polarity. In (hereinafter, simply referred to as sync polarity determination / polarity inversion circuit) 16, the horizontal sync signal input to the horizontal sync signal input terminal 18 for determining the display timing of the analog RGB video signal on the display screen is The sync polarity is determined, and the sync polarity determination signal and the positive polarity horizontal synchronization signal (or the negative polarity horizontal synchronization signal) are always output as one polarity (for example, positive polarity) regardless of whether the polarity is positive or negative.
Input to and used for synchronization processing.

A PLL (phase locked loop) circuit 22 outputs a positive polarity horizontal sync signal (reference signal H.REF) output from the sync polarity determination / polarity inversion circuit 16 and a comparison signal H.REF. VARI
Phase comparison circuit 2 for comparing and outputting a phase difference detection pulse
4 and LP connected to the output side of the phase comparison circuit 24
F (low pass filter) 26 and a frequency f (= H.REF frequency × N) using the output of the LPF 26 as a control voltage.
VCO (voltage controlled oscillator) that outputs the clock CLK
28 and the frequency f of the clock CLK output from the VCO 28 are divided into 1 / N and the comparison signal H.28. VARI to the phase comparison circuit 24 and the frequency divider 30 for outputting the positive polarity horizontal synchronization signal (or the negative polarity horizontal synchronization signal) output from the synchronization polarity determination / polarity inversion circuit 16 to the reference signal H.V. Create a clock CLK as REF and use this clock CLK for A / D
It is used for sampling the conversion circuit 10.

The sync polarity discrimination / polarity inversion circuit 16 is currently I
It is made into a C (integrated circuit), and by using this, the above-mentioned circuit can be easily realized.

[0006]

However, in the conventional circuit shown in FIG. 4, although there is no circuit delay until the analog RGB video signal input to the input terminal 12 reaches the A / D conversion circuit 10, Since the horizontal sync signal input to the terminal 18 reaches the A / D conversion circuit 10, there is the sync polarity determination / polarity inversion circuit 16 formed by an IC, so there is a circuit delay. If the circuit delay amount is always constant, no problem will occur. However, if the delay amount drifts due to a change in ambient temperature or the like, a problem as shown in FIG. 5 will occur.

That is, assuming that the analog RGB video signal input to the input terminal 12 has a waveform representing a white vertical line of 1 dot on the screen as shown in FIG. When the delay amount by the circuit 16 is constant, the positive horizontal synchronizing signal as the reference signal input to the PLL circuit 22 becomes as shown in FIG. 7B, and accordingly, the clock CLK output from the PLL circuit 22. Becomes a signal which is phase-synchronized with the positive polarity horizontal synchronization signal as shown in FIG.
1, S2 and S3 can be set to desired positions.

However, the sync polarity discrimination / polarity inversion circuit 16
If the amount of delay due to drift due to temperature changes, etc.
The phase of the positive horizontal synchronizing signal input to the LL circuit 22 is shown in FIG.
As shown in (d), it changes only for the period t, and accordingly P
The phase of the clock CLK output from the LL circuit 22 changes as shown in FIG. This is clock C
LK sampling points are S1, S2, S3 to S1
It means that it shifts to d, S2d, and S3d. When the sampling point deviates from the desired point in this way, when displaying on a digital display panel such as a PDP (plasma display panel) or LCD (liquid crystal display panel), two vertical lines appear where two vertical lines should appear. There was a problem that the focus on the screen was shifted, such as vertical lines appearing.

The present invention has been made in view of the above points, and the A / D conversion is performed even when the circuit delay amount by the sync polarity determination / polarity inversion circuit or the sync polarity determination circuit drifts due to a temperature change or the like. It is an object of the present invention to provide a circuit that prevents the sampling points in the circuit from shifting.

[0010]

According to another aspect of the present invention, there is provided a sampling point shift prevention circuit, wherein an analog video signal is sampled and converted into a digital video signal in an A / D conversion circuit. A sync polarity discriminating circuit for discriminating and outputting a sync polarity discriminating signal, an exclusive OR circuit for outputting an exclusive OR signal of an input horizontal synchronizing signal and a sync polarity discriminating signal, and an output of this exclusive OR circuit And a phase locked loop circuit for creating a sampling clock for the A / D conversion circuit using the signal as a reference signal.

The synchronous polarity discriminating circuit discriminates the polarity of the input horizontal synchronizing signal and outputs the synchronous polarity discriminating signal, and the exclusive OR circuit outputs the exclusive OR signal of the input horizontal synchronizing signal and the synchronous polarity discriminating signal. Output. The PLL circuit creates a clock CLK using the output signal of the exclusive OR circuit as a reference signal, and the A / D conversion circuit creates a clock C created by the PLL circuit.
The LK samples the analog video signal and converts it to a digital video signal. The input horizontal synchronizing signal does not pass through the sync polarity discriminating circuit having a large circuit delay amount, but passes through the exclusive OR circuit having almost no circuit delay amount, and is supplied as a PL signal as a reference signal.
Since it is input to the L circuit, even if the circuit delay amount due to the synchronization polarity determination circuit drifts due to temperature change or the like,
Along with this, the phase of the clock CLK output from the PLL circuit does not change, and the sampling point in the A / D conversion circuit does not shift.

According to another aspect of the present invention, there is provided a sampling point deviation prevention circuit, wherein in an A / D conversion circuit for sampling an analog video signal and converting it into a digital video signal, the polarity of the input horizontal sync signal is judged to determine the sync polarity. In addition to outputting a signal, a sync polarity determination and polarity inversion circuit that outputs the input horizontal sync signal with either the positive polarity or the negative polarity and an exclusive OR signal of the input horizontal sync signal and the sync polarity determination signal is output. It is characterized by comprising an exclusive OR circuit and a phase locked loop circuit for creating a sampling clock of the A / D conversion circuit using the output signal of the exclusive OR circuit as a reference signal.

The sync polarity discriminating / polarity inverting circuit discriminates the polarity of the input horizontal synchronizing signal and outputs the sync polarity discriminating signal, and also makes the polarity of the input horizontal synchronizing signal positive or negative (for example, positive). Output. The exclusive OR circuit outputs an exclusive OR signal of the input horizontal sync signal and the sync polarity determination signal. The PLL circuit creates a clock CLK using the output signal of the exclusive OR circuit as a reference signal,
The / D conversion circuit samples the analog video signal with the clock CLK created by the PLL circuit and converts it into a digital video signal. Since the input horizontal synchronizing signal is input to the PLL circuit as a reference signal through the exclusive OR circuit having almost no circuit delay amount, without passing through the synchronization polarity determining / polarity inverting circuit having a large circuit delay amount, Even if the delay amount due to the sync polarity determination / polarity inversion circuit drifts due to a temperature change or the like, the phase of the clock CLK output from the PLL circuit does not change accordingly, and the sampling in the A / D conversion circuit is performed. The points do not shift.

According to a third aspect of the present invention, in the first or second aspect of the invention, the exclusive OR circuit includes an inverting amplifier that inverts the polarity of the input horizontal synchronizing signal and outputs the inverted horizontal synchronizing signal, and an input horizontal synchronizing signal and an inverting amplifier. By configuring the output signal and the switching device that switches the output signal by the sync polarity determination signal and outputs the signal, the configuration of the exclusive OR circuit is simplified.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. In FIG. 1, reference numeral 10 is an A / D conversion circuit 10.
The A / D conversion circuit 10 converts the analog RGB video signal input to the input terminal 12 into a digital RGB video signal by sampling with the clock CLK output from the PLL circuit 22, and outputs the digital RGB video signal to the output terminal 14. Is configured.

Reference numeral 18 is a horizontal synchronizing signal input terminal. The horizontal synchronizing signal HD for determining the display timing of the analog RGB video signal input to the input terminal 12 on the display screen is input to the input terminal 18. . Reference numeral 16 is a sync polarity discriminating / polarity inverting circuit. The sync polarity discriminating / polarity inverting circuit 16 is a horizontal sync signal H input to the input terminal 18.
A sync polarity determination signal is output by determining the sync polarity of D, and a horizontal sync signal of one polarity (for example, positive polarity) is always output regardless of whether the polarity of the input horizontal sync signal HD is positive or negative. Is configured to.

Reference numeral 32 is an exclusive OR circuit formed by a general logic IC with almost no drift of the circuit delay amount.
The exclusive OR circuit 32 is an exclusive OR signal (for example, a positive polarity horizontal sync signal) between the horizontal sync signal HD input to the input terminal 18 and the sync polarity judgment signal output from the sync polarity judgment / polarity inversion circuit 16. ) Is output. The exclusive OR circuit 32 is configured, for example, as shown in FIG.

That is, the exclusive OR circuit 32 is
The inverting amplifier 34 that inverts the polarity of the horizontal synchronizing signal HD input to the input terminal 18 and outputs the inverted horizontal synchronizing signal HD input to the input terminal 18 and the inverted horizontal synchronizing signal rHD output from the inverting amplifier 34 are switched. And a switching unit 36 which outputs the signal as a switching signal. The switching unit 36 switches the signal HD and the signal rHD by using the synchronization polarity determination signal of the synchronization polarity determination / polarity inversion circuit 16 as a switching signal, and always performs horizontal synchronization of one polarity. It is configured to output a signal (for example, a positive polarity horizontal synchronization signal).

Reference numeral 22 is a PLL circuit.
Is the same as that described with reference to FIG.
F26, VCO 28, and frequency divider 30, and outputs a horizontal sync signal (for example, positive polarity horizontal sync signal) of one polarity output from the exclusive OR circuit 32 as a reference signal H.264. A clock CLK is generated as REF, and the clock CLK is output to the A / D conversion circuit 10 as a sampling signal.

Next, the operation of FIGS. 1 and 2 will be described with reference to FIG. For convenience of explanation, a case will be described in which the horizontal synchronizing signal HD input to the input terminal 18 is input to the PLL circuit 22 with the positive polarity. Sync polarity determination / polarity inversion circuit 1
Reference numeral 6 determines whether the polarity of the input horizontal synchronization signal HD is negative or positive, outputs a synchronization polarity determination signal (H, L) as shown in FIG. 3, and also inputs the horizontal synchronization signal HD. The positive polarity is used for output (this output is not used).

The exclusive OR circuit 32 outputs an exclusive OR signal of the horizontal synchronizing signal HD input to the input terminal 18 and the sync polarity discriminating signal. That is, in FIG. 2, when the polarity of the input horizontal sync signal HD is positive, the sync polarity determination signal is set to L level to control the switching piece of the switch 36 to the position shown by the solid line, and the polarity of the input horizontal sync signal HD is When the polarity is negative, the horizontal polarity signal H input to the input terminal 18 is controlled by setting the sync polarity determination signal to H level and controlling the switching piece of the switch 36 to the position shown by the dotted line.
Whether the polarity of D is positive or negative, the positive horizontal synchronizing signal is always output to the output side of the switch 36.

The PLL circuit 22 uses the positive horizontal synchronizing signal output from the exclusive OR circuit 32 as the reference signal H.264. A clock CLK is generated as REF, and the A / D conversion circuit 10 is a PLL.
The analog RGB video signal is sampled by the clock CLK created by the circuit 22, converted into a digital RGB video signal, and output to the output terminal 14.

As described above, the horizontal sync signal HD input to the input terminal 18 is used to determine the sync polarity with a large circuit delay amount.
Without passing through the polarity reversing circuit 16, it becomes a positive polarity horizontal synchronizing signal via the exclusive OR circuit 32 having almost no circuit delay amount,
The PLL circuit 22 uses the positive horizontal synchronizing signal as a reference signal.
Input to the sync polarity determination / polarity inversion circuit 16
Even if the amount of circuit delay due to drift due to temperature change or the like, the phase of the clock CLK output from the PLL circuit 22 does not change accordingly, and the sampling point in the A / D conversion circuit 10 shifts. There is no.

In the above-described embodiment, regardless of whether the polarity of the horizontal synchronizing signal HD input to the input terminal 18 is positive or negative, the positive horizontal synchronizing signal is always used as the reference signal for the PLL.
Although the case of inputting to the circuit 22 has been described, the present invention is not limited to this, and regardless of whether the polarity of the horizontal synchronizing signal HD input to the input terminal 18 is positive or negative, the negative horizontal synchronizing signal is always output. It can also be used when inputting to the PLL circuit 22 as a reference signal.

For example, by making the function of the sync polarity discrimination / polarity inversion circuit 16 in FIG. 1 reverse to that in FIG. 3, that is, when the polarity of the input horizontal sync signal HD is negative, it is L level, and when it is positive, it is. It is configured to output an H-level sync polarity determination signal. Then, in FIG. 2, when the polarity of the input horizontal sync signal HD is negative, the sync polarity determination signal is set to L level to control the switching piece of the switch 36 to the position shown by the solid line, and the polarity of the input horizontal sync signal HD is positive. In this case, the sync polarity determination signal is set to the H level and the switching piece of the switch 36 is controlled to the position shown by the dotted line, so that the horizontal sync signal HD input to the input terminal 18 is switched between the negative polarity and the positive polarity. Bowl 3
The negative horizontal sync signal is always output to the output side of 6.

In the above-mentioned embodiment, the case where the exclusive OR circuit is composed of the inverting amplifier and the switch has been described, but the present invention is not limited to this, and the input horizontal synchronizing signal and the synchronizing polarity are determined. It suffices to output an exclusive OR signal with the sync polarity determination signal output from the polarity inverting circuit.

In the above embodiment, the sync polarity discriminating signal, which is one input signal of the exclusive OR circuit, is discriminated from the polarity of the input horizontal synchronizing signal to output the sync polarity discriminating signal, and the input horizontal synchronizing signal is outputted. Although one signal (synchronization polarity determination signal) output from the synchronization polarity determination / inversion circuit that outputs the polarity of the signal as one of the positive polarity and the negative polarity is used, the present invention is not limited to this. It may be a signal output from a sync polarity determination circuit that determines the polarity of the signal and outputs only the sync polarity determination signal (sync polarity determination signal).

[0028]

The sampling point shift prevention circuit according to the first aspect of the present invention obtains the exclusive OR of the sync polarity discriminating signal of the input horizontal synchronizing signal discriminated by the sync polarity discriminating circuit and the input horizontal synchronizing signal. A horizontal sync signal having one polarity (for example, positive polarity) is obtained regardless of the polarity of the input horizontal sync signal, a clock is created by a PLL circuit using this horizontal sync signal as a reference signal, and the created clock is used as a sampling clock A Since the analog video signal is converted into the digital video signal by the D / D conversion circuit, the input horizontal sync signal does not pass through the sync polarity discriminating circuit having a large circuit delay amount, and the exclusive OR with almost no circuit delay amount. It is input to the PLL circuit as a reference signal via the circuit. Therefore, even if the circuit delay amount due to the synchronization polarity determination circuit drifts due to a temperature change or the like, the phase of the sampling clock output from the PLL circuit does not change accordingly, and the A / D conversion is performed. The sampling points in the circuit do not shift.

In the video signal processing circuit according to the present invention, the exclusive polarity OR of the input horizontal synchronization signal and the synchronization polarity determination signal of the input horizontal synchronization signal determined by the synchronization polarity determination / polarity inversion circuit is performed. A horizontal sync signal having one polarity (for example, positive polarity) is obtained regardless of the polarity of the input horizontal sync signal, a clock is created by a PLL circuit using this horizontal sync signal as a reference signal, and the created clock is used as a sampling clock A Since the analog video signal is converted to a digital video signal by the / D conversion circuit, the input horizontal sync signal does not pass through the sync polarity discrimination / polarity inversion circuit with a large circuit delay amount It is input to the PLL circuit as a reference signal via the logical OR circuit. Therefore, even if the circuit delay amount due to the sync polarity determination / polarity inversion circuit drifts due to a temperature change or the like, the phase of the sampling clock output from the PLL circuit does not change accordingly, and A The sampling point in the / D conversion circuit does not shift.

According to a third aspect of the present invention, in the first or second aspect of the invention, the exclusive OR circuit includes an inverting amplifier that inverts the polarity of the input horizontal synchronizing signal and outputs the exclusive horizontal OR signal, and an input horizontal synchronizing signal and the inverting amplifier. Since the output signal and the switch for switching the output with the sync polarity determination signal are output, the configuration of the exclusive OR circuit can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sampling point shift prevention circuit of an A / D conversion circuit according to the present invention.

FIG. 2 is a block diagram showing a specific example of the exclusive OR circuit of FIG.

FIG. 3 is an explanatory diagram of a sync polarity determination function of the sync polarity determination / polarity inversion circuit of FIG.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a circuit diagram of FIG.
FIG. 6 is a waveform diagram for explaining a deviation of sampling points when the circuit delay amount of 1 drifts.

[Explanation of symbols]

10 ... A / D (analog / digital) conversion circuit, 1
2 ... Analog RGB video signal input terminal, 14 ... Digital RGB video signal output terminal, 16 ... Sync polarity determination / polarity inversion circuit, 18 ... Horizontal sync signal input terminal,
20 ... Synchronous processing circuit, 22 ... PLL (phase locked loop) circuit, 24 ... Phase comparison circuit, 26 ... LPF (low-pass filter), 28 ... VCO (voltage controlled oscillator), 30 ... Divider, 32 ... Exclusive logic Sum circuit,
34 ... Inverting amplifier, 36 ... Switching device, CLK ... Clock, f ... Clock frequency, HD ... Input horizontal synchronizing signal, H.V. REF ... reference signal, H.H. VARI ... Comparison signal, S1 to S3 ... Sampling points when there is no drift, S1d to S3d ... Sampling points when there is drift, rHD ... Signals obtained by inverting the input horizontal synchronizing signal.

Claims (3)

[Claims] 1. An A / D conversion circuit for sampling an analog video signal and converting it into a digital video signal, and a sync polarity discriminating circuit for discriminating the polarity of an input horizontal sync signal and outputting a sync polarity discriminating signal; An exclusive OR circuit that outputs an exclusive OR signal of an input horizontal sync signal and the sync polarity determination signal, and a sampling clock of the A / D conversion circuit using the output signal of the exclusive OR circuit as a reference signal. And a phase-locked loop circuit for producing the sampling point deviation prevention circuit of the A / D conversion circuit. 2. An A / D conversion circuit for sampling an analog video signal and converting it into a digital video signal, discriminating the polarity of the input horizontal synchronizing signal and outputting a synchronizing polarity discriminating signal, and at the same time, the input horizontal synchronizing signal. A polarity polarity inverting and polarity inverting circuit that outputs the polarity as either positive or negative, and an exclusive OR circuit that outputs an exclusive OR signal of the input horizontal synchronization signal and the synchronization polarity determination signal, A phase-locked loop circuit that creates a sampling clock for the A / D conversion circuit using the output signal of the exclusive OR circuit as a reference signal, and prevents deviation of the sampling point of the A / D conversion circuit. circuit. 3. An exclusive OR circuit switches an inverting amplifier that inverts the polarity of an input horizontal synchronizing signal and outputs it, and switches the input horizontal synchronizing signal and the output signal of the inverting amplifier by a sync polarity discriminating signal and outputs the same. 3. A sampling point shift prevention circuit for an A / D conversion circuit according to claim 1, further comprising a switching device.