JPH08125943A - Signal conversion circuit - Google Patents

Abstract

PURPOSE: To shorten the time until a screen is stably displayed after power is supplied or the like by providing a PLL information storage part and storing and utilizing PLL information operated in a previous time and synchronization frequency information immediately judged when a synchronization frequency is changed. CONSTITUTION: Input video signals passed through an A/D converter 9 are written in a video storage part 10 corresponding to the output of a first PLL 8, read through a second PLL 11 and supplied to a display part 30. When power supply is detected in a power supply detection part 20, the frequency information of the PLL 8 at the time of the operation of the previous time stored in a PLL information storage part 5 is read and the output frequency of the PLL 8 is quickly stabilized through a frequency division value setting part 6 and a clock frequency setting part 7. In the meantime, when the input video signals are switched, the synchronization frequency is inmmediately judged in a frequency judgment part 3 and written in the storage part 5, the output frequency of the PLL 8 is quickly stabilized similarly and the time until the screen is stably displayed after the power is supplied or at the time of video signal changeover is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing technique, and more particularly to a synchronization follow-up circuit in a signal conversion circuit which inputs an analog video signal, converts it into a digital video signal and outputs it.

[0002]

2. Description of the Related Art Conventionally, an analog video signal is input from a video input section for switching and inputting a video signal having a different synchronizing frequency such as a TV video signal of NTSC or PAL or a video signal from a personal computer and converted into a digital video signal. As shown in FIG. 3, the signal conversion circuit for outputting the sync signal separates the sync signal from the video signal from the video input section for inputting the video signal, and the horizontal sync signal separated by the sync separation circuit. A frequency discriminating section for discriminating the frequency, and a control section for controlling the clock frequency setting section or the like based on the discriminating frequency,
The clock frequency setting unit that sets the clock frequency of the first PLL circuit under the control of the control unit, and the first unit that generates a dot clock of a predetermined frequency in synchronization with the synchronization signal from the synchronization separation circuit. PLL circuit, an A / D converter that samples the video signal with the dot clock and converts it into a digital signal, and a video storage unit that writes and stores the digital video signal from the A / D converter with the dot clock. And a second PLL circuit that generates a predetermined dot clock for reading in synchronization with the sync signal from the sync separation circuit, separates the sync signal from the input video signal, and determines the frequency of the sync signal. Discrimination is performed by counting the number of synchronizing signals in one field period, and the first PLL circuit is controlled based on the discrimination result to write a predetermined frequency. Since the dot clock is transmitted and the first PLL is automatically locked, it takes time to lock the first PLL, and the screen is distorted until the synchronization is achieved. .

[0003]

SUMMARY OF THE INVENTION The present invention solves the problems described above, and after the power is turned on or the signal is switched, the PLL locks to generate a stable dot clock.
It is an object of the present invention to provide a signal conversion circuit that shortens the time until the screen is displayed stably.

[0004]

In order to solve the above-mentioned problems, the present invention provides a video input section for switching and inputting video signals having different synchronizing frequencies such as TV video signals such as NTSC and PAL and video signals from a personal computer. A sync separation circuit for separating a sync signal from a video signal from the input section, a frequency judgment section for judging the frequency of the horizontal sync signal separated by the sync separation circuit, and a frequency division value of a PLL circuit for the judgment frequency, A PLL information storage unit that stores PLL information such as a clock frequency and a horizontal synchronizing frequency of an operating video signal, and a control unit that controls the frequency division value setting unit, the clock frequency setting unit, and the like based on the PLL information. A frequency division value setting unit that sets a frequency division value of the first PLL circuit under the control of the control unit; a clock frequency setting unit that sets a clock frequency; The first PLL circuit that generates a dot clock of a predetermined frequency in synchronization with the synchronization signal from the phase separation circuit, and an A / D conversion unit that samples the video signal with the dot clock and converts it into a digital signal. A video storage unit for writing and storing a digital video signal from the A / D conversion unit at the dot clock, and a second read dot clock for synchronizing with a sync signal from the sync separation circuit. Composed of a PLL circuit,
The dot clock is used to read out and output a digital video signal from the video storage unit.

[0005]

With the above-described structure, according to the signal conversion circuit of the present invention, when the power is turned on, the PLL information that was operating last time (before the power is turned off) is read from the PLL information storage unit, and the PLL information is read. The frequency division value setting unit sets the frequency division value based on the above, the clock frequency setting unit sets the clock frequency, and the frequency division value and the clock frequency of the first PLL circuit are set and separated from the input video signal. The horizontal synchronizing signal is input to the first PLL circuit, and the phase of the dot clock is locked by the horizontal synchronizing signal. When the synchronizing frequency changes by switching the input video signal, the synchronizing frequency is immediately determined, and the PLL information storage unit refers to the PLL information such as the dot clock frequency and the frequency division value for the determined frequency. Then, since the frequency and frequency division value of the dot clock of the first PLL are set,
L can immediately lock to the new sync frequency. In this way, the video signal input by the writing dot clock generated in the first PLL is sampled and converted into a digital video signal, which is written and stored in the video storage unit with the same writing dot clock. On the other hand, the second PLL generates a read dot clock having a predetermined oscillation frequency in synchronization with the vertical synchronizing signal of the input video signal, reads the dot clock from the video storage unit at the dot clock, and outputs the dot clock.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A signal conversion circuit according to the present invention will be described in detail below with reference to the drawings. 1 is a block diagram showing an embodiment of a signal conversion circuit according to the present invention. In the figure, 1
Is a video input section for matching the impedance, level, etc. of a video signal input by switching a TV video signal such as NTSC or PAL or a video signal from a personal computer having different synchronizing frequencies. Reference numeral 2 denotes a sync separation circuit, which separates a horizontal sync signal and a vertical sync signal from an input video signal. Reference numeral 3 denotes a frequency discriminating unit which discriminates the frequency of the horizontal synchronization signal separated by the synchronization. A control unit 4 controls the PLL information storage unit 5, the frequency division value setting unit 6, the clock frequency setting unit 7, and the like based on the frequency of the power-on detection signal and the synchronization signal. Reference numeral 5 denotes the PLL information storage unit, which stores the frequency and frequency division value of the dot clock with respect to the horizontal synchronizing frequency of the input video signal, and PLL information such as the horizontal synchronizing frequency of the currently operating video signal. Reference numeral 6 denotes the frequency division value setting unit, which based on the PLL information
The division value of the dot clock generated by 8 is set.
The clock frequency setting unit 7 sets the frequency of the dot clock generated by the first PLL 8 based on the PLL information. Reference numeral 8 is the first PLL, which is a phase comparison circuit 81 for comparing the phase of the horizontal synchronizing signal with a signal from a frequency dividing circuit 84 for dividing the generated dot clock, and a low pass filter for passing a low frequency component. 82
A VCO 83 for transmitting the dot clock frequency and the frequency dividing circuit 84. Reference numeral 9 denotes an A / D converter which samples the input video signal with a dot clock generated by the first PLL 8 and converts it into a digital signal. A video storage unit 10 writes and stores the digital video signal from the A / D conversion unit at the timing of the dot clock generated by the first PLL 8 and reads it by the read dot clock from the second PLL 11. Digital display device 3 such as plasma display
Outputs to 0. Reference numeral 11 denotes the second PLL, which generates a read dot clock in phase with the vertical synchronizing signal from the synchronizing separation circuit 2. Reference numeral 20 denotes a power supply detection unit, which detects that the power supply has been turned on and notifies the control unit 4 of it. Reference numeral 30 is a digital display device such as the plasma display or liquid crystal display.

The operation of the above arrangement will be described below. First, the case where the power is turned on will be described. When the power is turned on, the power detection unit 20 detects this and notifies the control unit 4, and the control unit 4 causes the PLL information storage unit 5 to operate.
The PLL information that was operating last time (before power-off) is read out, and the frequency division value of the frequency division circuit 84 of the first PLL circuit 8 is set in the frequency division value setting unit 6 based on the PLL information. The frequency setting unit 7 sets the clock frequency of the VCO 83. The frequency division value and the clock frequency of the first PLL circuit 8 are set, and the sync separation circuit 2 is set from the input video signal.
The horizontal synchronizing signal separated by is input to the first PLL circuit 8, and the phase of the dot clock is locked by the horizontal synchronizing signal.

Next, when the video signal input by the video input unit 1 is switched and the synchronizing frequency changes, the frequency discriminating unit 3 immediately discriminates the synchronizing frequency by counting the number of synchronizing signals in one field period. , Inform the control unit 4,
The control unit 4 uses the PLL information storage unit 5 to determine the PLL frequency of the dot clock and the frequency division value for the determined frequency.
By referring to the information, the frequency division value setting unit 6 and the clock frequency setting unit 7 are controlled to set the frequency and frequency division value of the dot clock of the first PLL 8, so the first PLL
8 can immediately lock to the new sync frequency. In the A / D conversion unit 9, as described above, the first PL
The video signal input by the writing dot clock generated in L8 is sampled and converted into a digital video signal,
The same writing dot clock is written and stored in the video storage unit 10. On the other hand, the second PLL 11 generates a dot clock for reading of a predetermined oscillation frequency in synchronization with the vertical synchronizing signal of the input video signal, and the dot clock can be read from the video storage unit 10 to display a Puma display or the like. Is output to the digital display device 30.

FIG. 2 shows another embodiment of the present invention,
The frequency discriminating unit 3 is omitted from FIG. 1, and the same effect can be obtained if the synchronizing frequency of the input video signal is constant. In this case, the PLL information storage unit does not store the synchronization frequency before power-off, but stores only the PLL information of the frequency division value and the frequency of the dot clock, and when the power is turned on, this is read out and set in the PLL. As a result, the PLL is locked in a short time.

[0010]

As described above, according to the signal conversion circuit of the present invention, when the power is turned on, the first PLL 8 is set to the PLL information before the power is turned off, and the input video signal is synchronized with the synchronization frequency. When the signal is switched to a different signal, the synchronization frequency is immediately determined and stored in the PLL information storage unit.
Referring to the PLL information corresponding to the synchronization frequency, the first PL
Since the setting of L8 is changed, the time until the PLL is locked can be shortened. The time from when the power is turned on until the screen is displayed stably and after the signal is switched the screen is displayed stably. It is possible to provide a signal conversion circuit that shortens the time until it is turned on.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a signal conversion circuit according to the present invention.

FIG. 2 is a block diagram showing another embodiment of the signal conversion circuit according to the present invention.

FIG. 3 is a block diagram showing a conventional signal conversion circuit.

[Explanation of symbols]

 1 Video Input Section 2 Sync Separation Circuit 3 Frequency Discrimination Circuit 4 Control Section 5 PLL Information Storage Section 6 Frequency Division Setting Section 7 Clock Frequency Setting Section 8 First PLL 9 A / D Conversion Section 10 Video Storage Section 11 Second Section PLL 20 Power source detection unit 30 Plasma display 81 Phase comparison circuit 82 Low pass filter 83 VCO 84 Frequency divider circuit

Claims (6)

[Claims] 1. A video input section for inputting a video signal, a sync separation circuit for separating a sync signal from the video signal from the input section, and PLL information such as frequency division value and clock frequency of the PLL circuit before power-off. A PLL information storage unit for storing
A control unit for controlling the frequency division value setting unit and the clock frequency setting unit based on the LL information, and the frequency division value setting unit for setting the frequency division value of the first PLL circuit under the control of the control unit. A clock frequency setting unit that sets a clock frequency; the first PLL circuit that generates a dot clock having a predetermined frequency in synchronization with a sync signal from the sync separation circuit; A / D conversion unit for sampling and converting into a digital signal by a signal, a video storage unit for writing and storing a digital video signal from the A / D conversion unit with the dot clock, and a synchronization signal from the synchronization separation circuit And a second PLL circuit that generates a predetermined read dot clock,
The dot clock is used to read out and output a digital video signal from the video storage unit, and when the power is turned on, the frequency division value and the clock frequency of the PLL circuit before the power is turned off are set to the first PLL from the PLL information storage unit. A signal conversion circuit characterized by being started up. 2. A video input section for switching and inputting a video signal having a different synchronizing frequency such as a video signal from a TV such as NTSC or PAL or a video signal from a personal computer, and a synchronization for separating the synchronizing signal from the video signal from the input section. A separation circuit, a frequency discriminating section for discriminating the frequency of the horizontal synchronization signal separated by the synchronization separation circuit, a frequency division value and a clock frequency of the PLL circuit with respect to the discrimination frequency, a horizontal synchronization frequency of the video signal in operation, etc. A PLL information storage unit that stores PLL information;
A control unit for controlling the frequency division value setting unit, the clock frequency setting unit, etc. based on the PLL information, and the frequency division value setting unit for setting the frequency division value of the first PLL circuit under the control of the control unit. A clock frequency setting unit that sets a clock frequency; the first PLL circuit that generates a dot clock having a predetermined frequency in synchronization with a sync signal from the sync separation circuit; An A / D converter for sampling with a clock and converting it into a digital signal, a video memory for writing and storing the digital video signal from the A / D converter with the dot clock, and a sync signal from the sync separation circuit. A second PLL circuit that synchronously generates a predetermined dot clock for reading, and reads a digital video signal from the video storage unit by the dot clock. Signal conversion circuit which is characterized in that so as to output Te. 3. The first PLL circuit compares the phase of a horizontal sync signal from the sync separation circuit with a frequency-divided signal obtained by dividing a dot clock signal into a predetermined frequency division value by a frequency division circuit. A phase comparison circuit, a low-pass filter that cuts high-frequency components of the comparison signal from the phase comparison circuit and passes low-frequency components, and a VCO that generates a dot clock that controls the phase by the signal from the low-pass filter,
And a dividing circuit for dividing the dot clock frequency, the dividing value of the dividing circuit is set by the dividing value setting unit, and the oscillation frequency of the VCO is set by the clock frequency setting unit. The signal conversion circuit according to claim 1, wherein: 4. The signal conversion circuit according to claim 2, wherein the PLL information storage section uses a ROM in which data is stored in advance. 5. The PLL information storage unit is rewritable, E
The signal conversion circuit according to claim 1 or 2, wherein a nonvolatile storage element such as an EPROM or a RAM backed up by a battery is used to constantly rewrite and store new PLL information. 6. The signal conversion circuit according to claim 1, wherein the write and read clocks of the video storage section use the same or different clock frequencies.