JPH07226860A - Pll circuit - Google Patents

Abstract

PURPOSE:To provide a PLL circuit making possible reproducing a dot clock being stable even when an abnormal period exists in a horizontal synchronizing signal. CONSTITUTION:In the PLL circuit having a phase comparator 1, a low-pass filter 2, a voltage control oscillator 3 and a frequency divider circuit 4, a logic circuit block 14 is added. The logic circuit block 14 generates a pseudo horizontal synchronizing signal in the abnormal period of the horizontal synchronizing signal, restricts the frequency change of the dot clock reproduced in the period and reproduces the stable dot clock with few jitters at an output end 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit for reproducing a dot clock from a horizontal synchronizing signal in a digital display device.

[0002]

2. Description of the Related Art Generally, a television receiver using a color flat panel, a liquid crystal panel or the like and a display monitor for a computer perform signal processing such as sampling of a video signal and operation of an internal circuit by a digital method. There is.

A PLL circuit is generally used as a means for obtaining the reference signal for the digital processing, and the dot clock is reproduced from the horizontal synchronizing signal. The horizontal synchronizing signal output from a general computer has a pulse-like waveform with a constant cycle, but the television signal and the horizontal synchronizing signal of some computers are superimposed on the video signal and the vertical synchronizing signal. It is necessary to separate the horizontal sync signal by the sync separation circuit. The horizontal sync signal separated by sync is
There may be an irregular period such as a case where the sync signal is not output around the vertical sync period and an equivalent pulse is output, and the obtained horizontal sync signal differs depending on the sync separation circuit.

Since a normal phase comparison is not performed in the PLL circuit during such an irregular period of the horizontal synchronizing signal,
The PLL is unlocked, and the frequency of the reproduced dot clock changes greatly.

When it is necessary to deal with a signal source that can only obtain a horizontal synchronizing signal having such an irregular period,
The following methods have been used in conventional digital display devices and their PLL circuits.

(1) An extraordinary period exists in the PLL circuit that reproduces the dot clock by providing a separate PLL circuit in the sync separation circuit and reproducing a new horizontal sync signal from the sync separated horizontal sync signal. Prevent horizontal sync signals from being input.

(2) By adjusting the constant of the low-pass filter (hereinafter referred to as LPF) of the PLL circuit, the influence of the abnormal horizontal synchronizing signal does not appear in the display period.

(3) PL in the irregular period of the horizontal synchronizing signal
The phase comparison operation of the L circuit is stopped.

[0009]

However, such a conventional method has the following problems. (1) In the method of reproducing the horizontal synchronizing signal by the PLL,
The sync separation circuit becomes complicated, or the sync separation I
The selection of C is not limited to the one having a built-in PLL circuit, and the horizontal synchronizing signal obtained thereby has a lot of jitter with respect to the horizontally separated horizontal synchronizing signal. Therefore, the jitter of the dot clock reproduced by the PLL circuit increases, and it is difficult to reduce the jitter particularly in the PLL circuit of the computer display device that requires low jitter.

(2) In the method of adjusting the constant of the LPF, it is difficult to optimize the constant considering the basic performance of the PLL circuit itself. (3) In the method of stopping the phase comparison operation during the abnormal period of the horizontal synchronizing signal, the phase comparator used in the PLL circuit must first have a function of stopping the operation. Also, since the period during which the horizontal sync signal becomes irregular varies depending on the signal source or sync separation circuit, the period for which the operation of the phase comparator should be stopped for various signal sources is clarified, and a control signal is generated. Is difficult.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a PLL circuit capable of reproducing a dot clock with little jitter for various signal sources.

[0012]

In order to achieve the above object, the present invention has a logic circuit block having the following features in a horizontal synchronizing signal input portion of a PLL circuit.

(1) When a normal horizontal synchronizing signal is input, it is output as it is. (2) After outputting the horizontal synchronizing signal, the horizontal synchronizing signal is not output to the input within a certain period less than the horizontal period.

(3) After outputting the horizontal synchronizing signal, if there is no input within a fixed period other than the horizontal period, a pulse is forcibly output.

[0015]

According to the PLL circuit of the present invention having such characteristics, even when an equivalent pulse exists in the horizontal synchronizing signal, it does not add to the phase comparator of the PLL circuit, and there is a period in which the horizontal synchronizing signal is missing. Even if they exist, since a pseudo sync signal is added to the phase comparator, their influences can be minimized, and stable dot clock reproduction is possible.

[0016]

1 shows a PLL circuit according to an embodiment of the present invention.
Will be explained. FIG. 1 is a block diagram showing the configuration of the PLL circuit. The PLL circuit is characterized by including a logic circuit block 14 including a microcomputer 5, a counter 6, a register 7, a comparator 8, a decoder block 9, an OR circuit 10 and an AND circuit 11. In the PLL circuit shown in FIG. 1, the input terminal 12 is a terminal to which a horizontal sync signal is input from the sync separation circuit. The polarity of the horizontal synchronizing signal is always positively converted here. The input horizontal synchronizing signal is applied to the phase comparator 1 via the OR circuit 10 and the AND circuit 11. The phase comparator 1 detects the phase difference between the horizontal synchronizing signal and the signal obtained by dividing the dot clock by the frequency dividing circuit 4, and gives an output according to the detection result to the voltage controlled oscillator 3 via the low pass filter 2. The frequency division ratio is set by the microcomputer 5 here. The voltage controlled oscillator 3 oscillates according to the applied voltage and is taken out from the output terminal 13 as a dot clock.

The counter 6 is operated by the dot clock, and its output is given to the comparator 8 and the decoder block 9. The counter 6 is reset by the output of the AND circuit 11, that is, the horizontal synchronizing signal given to the phase comparator.

The register 7 holds a certain value equal to or higher than the frequency division ratio set by the microcomputer 5. The comparator 8 outputs a pulse when the value stored in the register 7 and the value of the counter 6 are equal. The decoder block 9 outputs a low level during a certain period of the horizontal period or less (hereinafter referred to as L) after the horizontal synchronizing signal is input to the phase comparator according to the value of the counter 6 and the setting from the microcomputer 5, and keeps the high level during other periods. Output (hereinafter H
And).

The operation of the PLL circuit configured as above will be described in more detail with reference to FIG. Here, it is assumed that the frequency division ratio set in the frequency dividing circuit 4 is 800, the value set in the register 7 is 810, and the decoder block 9 sets the output to be L during the period in which the value of the counter 6 is 100 to 700. .

First, when a normal horizontal synchronizing signal is applied to the input terminal 12, the output value of the counter 6 counts up from 0 to 799, but after that, it is set in the register 7 because it is cleared by the horizontal synchronizing signal. The output of the comparator 8 is always L. Further, since the output of the decoder block 9 is H in the vicinity of the horizontal synchronizing signal, the horizontal synchronizing signal input from the AND circuit 11 is directly output and added to the phase comparator 1. Therefore, the PLL circuit operates in the same manner as in the case without the present invention.

Next, when the horizontal synchronizing signal applied to the input terminal 12 is lost, the counter 6 is not cleared, and when the value becomes 810 set in the register 7, the output of the comparator 8 becomes H. Since the output of the decoder 7 is also H here, the output of the comparator 8 becomes a pseudo horizontal synchronizing signal and is added to the phase comparator 1. Therefore, the phase difference detected by the phase comparator 1 can be reduced even during the period when the horizontal synchronizing signal is missing, and the frequency change of the reproduced dot clock can be suppressed.

When an equivalent pulse is input to the input terminal 12, the output of the decoder block 9 is L when the value of the counter 6 is between 100 and 700, and therefore AND
No equivalent pulse appears at the output of the circuit 11. Therefore, erroneous phase comparison is not performed in the phase comparator 1,
A stable dot clock is reproduced as in the case where a normal horizontal synchronizing signal is input.

The logic circuit block 14 provided at the input stage of the phase comparator 1 is a simple logic circuit, and may be configured using other logic elements. Also, the polarity of the synchronization signal can be arbitrarily set by configuring a logic circuit according to the operation of the phase comparator 1.

[0024]

As is apparent from the above description of the embodiments, according to the present invention, even if there is an irregular period in the horizontal sync signal due to the sync separation, its influence can be minimized and stable. The reproduced dot clock can be reproduced. Further, even when the irregular period of the horizontal synchronizing signal is changed due to the change of the sync separation circuit or the like, it is possible to similarly reproduce the stable dot clock.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a PLL circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 Phase Comparator 2 Low Pass Filter 3 Voltage Controlled Oscillator 4 Divider Circuit 5 Microcomputer 6 Counter 7 Register 8 Comparator 9 Decoder Block 10 AND Circuit 11 OR Circuit 12 Input Terminal 13 Output Terminal 14 Logic Circuit Block

Claims (1)

[Claims] 1. A PLL circuit for dot clock reproduction, comprising a circuit for newly generating a signal corresponding to a horizontal synchronizing signal for an irregular period of a horizontal synchronizing signal obtained by synchronous separation. A PLL circuit characterized by: