JPH0630295A - Synchronizing circuit for video signal - Google Patents

Abstract

PURPOSE:To output the vertical synchronizing signal of a regular frequency even when the waveform of a video signal is distorted by inputting only the pulse component signal in a synchronizing state with the double frequency of the pulse component signal to be the base of a horizontal synchronizing signal as a reset signal to a vertical oscillating means. CONSTITUTION:A binarizing circuit 21, window circuit 22, vertical PLL circuit 23, lock detection circuit 23 and AND circuit 25 are added between an integration circuit 3 and a vertical oscillation circuit 14. The vertical synchronizing signal obtained from the circuit 3 is binarized with a reference threshold value by the circuit 21, and the other sprious synchronizing signal than the period of the vertical synchronizing signal is removed by the circuit 22, and the original vertical synchronizing signal can be stably discriminated by the circuits 23 and 24. Therefore, even when the waveform of the video signal is distorted, the vertical synchronizing signal at the regular frequency is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing circuit for separating a synchronizing signal contained in a video signal and shaping the waveform.

[0002]

2. Description of the Related Art Decoded video signals (hereinafter referred to simply as "video signals"
(Referred to as) includes a signal for carrying video information and a signal for synchronizing. For example, in the case of NTSC, the first pulse component signal having a small period of about 63.5 μS and the second pulse component signal having a large period of about 16,6 mS are included. In a device that receives a video signal, such as a television receiver, the first and second pulse component signals (hereinafter, "horizontal synchronization signal a" and "vertical synchronization signal b" for ease of description) from the video signal are used. (Hereinafter referred to as ") is separated and extracted to reproduce a horizontal and vertical synchronizing signal.

FIG. 5 and FIG. 6 show block diagrams of a conventional video signal synchronizing circuit. The configuration and operation of FIGS. 5 and 6 will be described below taking the case of NTSC as an example. In the synchronizing circuit of FIG. 5, the vertical synchronizing circuit and the horizontal synchronizing circuit are independent systems. In FIG. 5, the video signal supplied to the input terminal 1 is separated and extracted by the sync separation circuit 2 into a horizontal sync signal a and a vertical sync signal b. The vertical synchronizing signal b is integrated by the integrating circuit 3 and supplied to the vertical oscillating circuit (V-OSC) 4 to output from the output terminal 5 an output vertical synchronizing signal (hereinafter referred to as “V-OSC”).
"D"). The vertical oscillation circuit 24
Is a time constant CR determined by the resistor R and the capacitor C.
Free run at the frequency determined by.

The horizontal sync signal a separated and extracted by the sync separation circuit 2 is supplied to one input of the AFC circuit 6 and compared in phase with a signal supplied to the other input terminal.
The output signal of the AFC circuit 6 is integrated by the integrating circuit 7,
It is supplied to the horizontal oscillation circuit 8 as a control signal for controlling the oscillation frequency. In the horizontal oscillation circuit (H-OSC) 8, an oscillation signal is generated according to the control signal and supplied to the horizontal output circuit (H-DRIVE) 9 to generate the frequency f _H (= 1.
5.75 kHz) output horizontal synchronizing signal (hereinafter referred to as "HD") is transmitted from the output terminal 10, and at the same time, a signal obtained by integrating the flyback pulse in the integrating circuit 11 is input to the other input terminal of the AFC circuit 6. It becomes a signal to be supplied.

In the synchronizing circuit of FIG. 6, the horizontal synchronizing signal a is supplied from the horizontal oscillating circuit 12 in response to a control signal from the integrating circuit 7.
Signal at twice the frequency 2f _H (= 31.5kHz) is sent in the frequency f _H. This 2f _H signal is divided into 1/525 by the frequency divider 13 as a frequency dividing means, and a 60 Hz divided signal is supplied to the vertical oscillation circuit 14 to generate VD. That is, in the circuit of FIG. 6, the frequency divider 13 is reset at the position where the 2f _H signal is counted by 525 from the position at which it was last reset (the vertical synchronization signal b was separated last). . Therefore, even when the waveform of the video signal is disturbed and the vertical synchronization signal b cannot be obtained,
A pseudo vertical sync signal can be generated every 1/60 second. The frequency divider 15 divides the 2f _H signal into ½ and supplies it to the horizontal output circuit 9. 6, the same components as those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted.

[0006]

However, in the conventional synchronous circuit described above, in the case of the configuration of FIG. 5, if the supplied video signal has a disturbed waveform as shown in FIG. The output waveform of 23 is the waveform shown in FIG. 7B, and the vertical synchronization signals S1 and S2 that should be present are missing because they are not separated and extracted, and the false vertical synchronization signal S3 that is an unnecessary component.
Will be included.

Therefore, the output of the vertical oscillation circuit 4 is as shown in FIG.
The waveform shown in (d) is obtained, and the missing vertical synchronizing signal is complemented. However, the frequency of VD determined by the time constant RC is changed from the normal frequency as shown in FIG. 7 (d) due to temperature and other conditions. There is a problem in that it may be misaligned, a false vertical synchronization signal cannot be removed, and there is a problem that synchronization is lost or noise is generated in an image.

In the case of the configuration of FIG. 6, the output of the vertical oscillation circuit 4 has the waveform shown in FIG. 7E, and the missing vertical synchronizing signal is reproduced as VD having a regular frequency.
The problem that the false vertical sync signal could not be removed and the sync error and the image noise occurred could not be solved.

The present invention solves the above-mentioned problems of the related art. Even when a ghost or noise is mixed in the supplied video signal to cause a disturbed waveform of the video signal,
It is an object of the present invention to provide an excellent video signal synchronizing circuit capable of outputting VD having a regular frequency.

[0010]

SUMMARY OF THE INVENTION The present invention is to solve the above-mentioned problems of the prior art, and includes a first pulse component signal having a small period and a second pulse component signal having a large period included in a video signal. To separate the two of the first pulse component signal
Horizontal oscillation means for generating a double frequency signal having a double frequency, frequency dividing means for dividing the double frequency signal to generate a divided signal, and inputting the second pulse component signal and the divided signal And a vertical oscillating means for outputting a vertical synchronizing signal. Then, the double frequency signal is counted from the trailing edge of the second pulse component signal to a predetermined count value, and the period other than the counting period is counted. To the signal relay means for outputting the second pulse component signal, and the synchronization state of the second pulse component signal and the double-frequency signal obtained from the signal relay means, and a period other than the period of the synchronization state is determined. And a stability determination output means for stopping the input of the second pulse component signal to the vertical oscillation means.

[0011]

Therefore, according to the present invention, only the second pulse component signal in synchronization with the double frequency signal having a frequency twice that of the first pulse component signal which is the basis of the horizontal synchronizing signal is sent to the vertical oscillating means. Since it is input as a reset signal of, the ghost or noise is mixed in the video signal, and even if the video signal has a distorted waveform, it is possible to output the VD of the regular frequency.

[0012]

Embodiments of the present invention will be described below with reference to FIGS. 1 to 4 and FIG.

FIG. 1 is a block diagram of an embodiment of a video signal synchronizing circuit according to the present invention. In FIG. 1, components having the same configurations as those of the conventional example shown in FIGS. 5 and 6 are denoted by the same reference numerals and the description thereof will be omitted, and a configuration and an operation different from those of the conventional example will be described.

In FIG. 1, a binarization circuit 21 and a window circuit 2 are provided between the integration circuit 3 and the vertical oscillation circuit 14.
2, vertical PLL circuit 23, lock detection circuit 24 and AN
The D circuit 25 is newly added. The vertical PLL circuit (hereinafter referred to as “V-PLL”) 23 includes a counter 23.
a and an AND circuit 23b. Further, as shown in FIG. 2, the internal circuit of the window circuit 22 includes a D flip-flop (hereinafter referred to as “D-FF”) 31 and a counter 32 whose full count value is set to “519” which is a predetermined count value. , Buffer with enable terminal 33
And an inverter 34.

Next, the operation of this embodiment will be described.
When the normal VD has the waveform shown in FIG. 3A, the vertical synchronizing signal obtained from the integrating circuit 3 is binarized by the binarizing circuit 21 at the reference threshold level, and the window circuit 22 displays it. The vertical synchronizing signal b having the waveform shown in 6 (b) is
From the input terminal 35 of the window circuit 22 in FIG.
It is supplied to the clock input of the FF31 and the Q output signal e shown in FIG. 3 (e) becomes high level. As a result, the enable terminal and the reset terminal of the counter 32 become high level, and the count of the 2f _H signal as the double frequency signal supplied from the input terminal 36 to the clock input of the counter 32 is the trailing edge of the vertical synchronizing signal b. It starts from the time of rising.

FIG. 3C shows how the count value of the counter 32 changes. The count value is “0” at time t1, and the count value gradually increases and reaches the count value “519” at time t2.
Is output. This carry-out signal d causes D-FF3
1 is reset, and the Q output signal e becomes low level.
As a result, the counter 32 stops counting and the count value of "519" is reset to "0".

On the other hand, the vertical synchronizing signal b input to the buffer 33 is supplied to the inverter 34 when the enable terminal of the buffer 33 is at low level, and the window signal f based on the vertical synchronizing signal b is output from the output terminal 37. . However, the window signal f is not transmitted when the enable terminal of the buffer 33 is at the high level, that is, while the counter 32 is counting. That is, the window circuit 22 uses the cycle (1
/ 60 seconds), the false sync signal S31 included in other than can be removed, but when the next S2 is missing as shown in FIG.
The window signal is output in S32 and S33.

As described above, the window circuit 22 may mask the false sync signal, but even if the original vertical sync signal is masked, the PLL 23 and the lock detection circuit 24 in the next stage should make a stable determination. You can Further, an inverted window signal * f, which is the inverted window signal, is sent from the output terminal 38 via the inverter 34. That is, the window circuit 22 is a signal relay unit that relays and outputs the vertical synchronization signal b during a period other than the counting period for counting the 2f _H signal.

In the V-PLL 23 shown in FIG. 1, the counter 23a sends out the carry-out signal g shown in FIG. 4 (g) when the count value of the 2f _H signal becomes "525". Further, the count value of the counter 23a is reset by the reset signal h which is the output of the AND circuit 23b which receives the inverted window signal * f and the carry-out signal g. FIG. 3 (h) shows the waveform of the reset signal h.

When the V-PLL 23 is locked, the inverted window signal * f, that is, the vertical synchronization signal b and the carry-out signal g are synchronized, and are not synchronized when unlocked. The lock detection circuit 24 detects the lock state of the V-PLL, and as shown in FIG. 4 (i), the lock detection signal i of high level is sent at the time of lock and low level at the time of unlock.

Further, this lock detection signal i is supplied to one input of the AND circuit 25, and based on the logical product with the window signal f supplied to the other input, FIG. 4 (j).
The signal j shown in is supplied to the vertical oscillation circuit 14 including a countdown circuit. This vertical oscillation circuit 14
It is reset by the signal j, and even if the signal j is high level for a certain period, it is reset by the free-running counter,
The output terminal 5 outputs a stable signal k as VD.

That is, the V-PLL 23, the lock detection circuit 24, and the AND circuit 25 constitute a stable discrimination output means for discriminating the stable vertical synchronizing signal b and supplying it to the vertical oscillation circuit 14.

In the above embodiment, the signal relay means and the stability determination output means as shown in FIGS. 1 and 2 are used to generate the signal j, but the present invention is not limited to this embodiment. Various other circuit configurations are possible because the waveform of j is obtained.

[0024]

As is apparent from the above embodiment, the present invention separates and extracts the vertical synchronizing signal included in the video signal to obtain a stable vertical synchronizing signal as the synchronizing signal in the receiving device. Since the signal relay means and the stability determination output means are used, even if a ghost or noise is mixed in the supplied video signal and the video signal has a distorted waveform, the vertical synchronizing signal of the regular frequency is generated. It is possible to output, and it is effective in stabilizing the vertical synchronization of the monitor and stabilizing the operation of the TV mobile reception diversity system.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a synchronization signal circuit according to the present invention.

FIG. 2 is an internal circuit diagram of a window circuit in FIG.

FIG. 3 is a timing chart of signal waveforms of respective parts in FIG.

FIG. 4 is a timing chart of signal waveforms of respective parts in FIG.

FIG. 5 is a block diagram of an example of a conventional synchronization signal circuit.

FIG. 6 is a block diagram of another example of a conventional synchronization signal circuit.

FIG. 7A is a diagram showing a waveform of an input video signal.
(B) is a diagram showing a waveform of a vertical synchronizing signal separated and extracted from a video signal. 7C is a diagram showing a waveform of a signal obtained by shaping the signal of FIG. 7B. FIG. 6D is a diagram showing the waveform of the vertical synchronizing signal output from the synchronizing circuit of FIG.
7E is a diagram showing a waveform of a vertical synchronizing signal output from the synchronizing circuit of FIG. (F) is a diagram showing a waveform of a normal vertical synchronizing signal.

[Explanation of symbols]

 21 Binarization circuit 22 Window circuit 23 Vertical PLL circuit 24 Lock detection circuit 25 AND circuit

Claims (1)

[Claims] 1. A first pulse component signal having a short period and a second pulse component signal having a long period included in a video signal are separated to obtain a frequency twice as high as that of the first pulse component signal. Horizontal oscillating means for generating the frequency-doubled signal, frequency-dividing means for frequency-dividing the frequency-doubled signal to generate a frequency-divided signal, and vertical by inputting the second pulse component signal and the frequency-divided signal. In a synchronizing circuit provided with vertical oscillating means for outputting a synchronizing signal, the doubled frequency signal is counted from a trailing edge of the second pulse component signal to a predetermined count value, and the double frequency signal is counted in a period other than a counting period. A signal relay unit that outputs two pulse component signals, and a synchronization state of the second pulse component signal and the double frequency signal obtained from the signal relay unit are determined, and the period other than the period of the synchronization state is the above-mentioned. The second pulse component signal to the vertical oscillating means Synchronizing circuit of the video signal and having a stability determination output means for stopping the input.