JPH10164618A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a laterally drawn noise from being generated by the interference of line clock and to provide a satisfactory receiving state, in which the noise is hardly conspicuous, by a little shifting the clock frequency of a line lock PLL circuit from the frequency of the burst clock. SOLUTION: A frequency f2Hz of the line lock clock generated by a line lock PLL circuit 13 is set to a frequency different from a burst lock clock frequency f1Hz. The input signal of A/D converter interfered by the line lock clock is sampled by the burst lock clock and its frequency is different from the frequency of interference, its level is shifted little by little for each sampling point. Further, since the level is changed for each line as well by the jitter or the line lock PLL, a luminance change amount seems changed at random for each pixel. Since the interference level is difference for each pixel, not the laterally drawn low frequency noise but random noise occurs and a picture extremely easy to watch is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a television receiver including a circuit for processing clock conversion from burst lock to line lock.

[0002]

2. Description of the Related Art In recent years, digitalization of television receivers has been advanced, and three-dimensional Y / C separation processing using a frame memory, progressive scan conversion, and the like have been carried out to improve image quality even for standard television signals. Devices that perform digital signal processing are increasing.

In converting a television signal into a digital signal, an A / D converter for converting an analog input video signal into a digital signal and a clock generation circuit for A / D conversion are required. When a clock synchronized with a standard television signal is generated, there are two types of clocks, a burst lock clock locked to a color burst signal included in the television signal and a line lock clock locked to a horizontal synchronization signal. There is a characteristic.

A burst lock clock is suitable as a system clock for a three-dimensional Y / C separation or color demodulation circuit, but has a poor stability with respect to a non-standard signal such as a reproduction signal of a VTR (video tape recorder). I have. On the other hand, the line lock clock is based on the horizontal synchronization signal,
Even when a non-standard signal is input, sufficient synchronization can be obtained.

Therefore, a system using both a burst lock clock and a line lock clock in order to construct a stable system has been devised. (For example, it is described in a video signal phase correction circuit disclosed in JP-A-7-288847 and a video signal processing circuit described in JP-A-8-70463).

FIGS. 3 and 4 show a conventional embodiment. 3, 1 is an analog video signal input terminal, 2 is an A / D converter, 3 is a Y / C separation circuit for separating a luminance signal and a chrominance signal, 4 is a color demodulation circuit, 5 is a time axis correction circuit, 6 Is a signal processing circuit for performing, for example, progressive scan conversion, 7 is a D / A converter, 8 and 9 are output terminals of a luminance signal and a color signal, respectively.
Reference numeral 10 denotes a burst signal extraction circuit that extracts a color burst signal included in a television signal, 11 denotes a synchronization separation circuit, 12 denotes a burst lock PLL circuit that generates a burst lock clock, and 13 denotes a line lock PLL circuit that generates a line lock clock. It is.

Next, the operation of FIG. 3 will be described. A burst signal is extracted from a video signal converted into a digital signal by the A / D converter 2 by a burst extraction circuit 10, and a burst lock clock is generated by a burst lock PLL circuit 12 based on a color subcarrier frequency (fsc) of the burst signal. Let it. The clock frequency (f1 Hz) is fsc
Is often set to 4 times or 8 times. Writing of data to the A / D converter 2, the Y / C separation circuit 3, the color demodulation circuit 4, and the time axis correction circuit 5 is performed using the burst lock clock. On the other hand, the synchronization separation circuit 11 separates horizontal and vertical synchronization signals included in the input video signal, and inputs the horizontal synchronization signal to the line lock PLL circuit 13 to use it as a reference signal of the line lock clock. The line lock PLL circuit will be described in more detail.

FIG. 4 is a block diagram of a line lock PLL circuit. In FIG. 4, reference numeral 14 denotes a reference horizontal synchronization signal input terminal, 15 denotes a phase comparison circuit, 16 denotes a low-pass filter, 17 denotes a D / A converter, 18 denotes an oscillator that oscillates a clock, and 19 denotes a frequency divider that divides a clock. , 20 are horizontal pulse output terminals formed by dividing the clock by the frequency dividing circuit 19, and 21 is a line lock clock output terminal.

Hereinafter, the operation of FIG. 4 will be described. Oscillator 18
Is a voltage-controlled oscillation circuit that oscillates a line lock clock (frequency f2 Hz). The oscillation frequency (f2 Hz) changes according to the output voltage of the D / A converter 17. The line lock clock frequency (f2 Hz) is 4 × fsc or 8 × fsc which is the same frequency as the burst lock clock frequency (f1 Hz).

The frequency dividing circuit 19 is a circuit for dividing the clock output from the oscillator 18 to generate a signal having the same horizontal rate as the horizontal synchronizing signal. For example, if the clock is about 14.3 MHz which is four times fsc, the horizontal synchronization frequency is obtained by dividing the frequency by 910, and if the clock is about 28.6 MHz which is eight times, 182 is obtained.
What is necessary is just to divide by zero.

The horizontal rate signal produced in this manner is used as one input of a phase comparator 15 and the other input is input to the input terminal 14 with the horizontal sync signal separated by the sync separation circuit 11. , And a low-pass filter 16 is applied to the output, and a D / A converter 17
The signal is converted into an analog signal and returned to the oscillator 18.

The clock locked to the horizontal synchronizing signal is generated by the loop circuit as described above.

Returning to FIG. 3, a non-standard clock is used by using a line lock clock based on a horizontal synchronizing signal as a read clock of the time axis correction circuit 5 and a clock of the signal processing circuit 6 and the D / A converter 7. We have built a stable system for signals.

[0014]

However, such a system using a plurality of clocks has a problem that the clocks interfere with each other and the interference causes noise.

The cause of the noise will be briefly described with reference to FIG. 5A shows a burst lock clock, FIG. 5B shows a line lock clock having the same phase as the burst lock clock, and FIG. 5C shows a line lock clock (b).
Input signal of the A / D converter (original signal indicated by a broken line), (d) is a line lock clock when the phase is slightly shifted from the burst lock clock, and (e) is a line lock clock (d) This is the signal that was disturbed.

The signal shown in FIG. 5C is sampled by the burst lock clock (a). In this case, a point indicated by a black circle is sampled, and its level is the same as the original signal level. The influence of the disturbance of the lock clock (b) does not appear. However, when the phase of the line lock clock is slightly shifted as shown in (d), the disturbed signal (e) is sampled by the burst lock clock, and as shown in FIG. It slightly deviates from the signal level.

Since the line lock PLL performs phase comparison at the horizontal synchronizing frequency rate as shown in FIG. 4, the phase of the line lock clock and the phase of the burst lock clock are PLL.
Delicately changes for each horizontal scanning line due to the jitter. This phase change causes a subtle luminance change for each horizontal scanning line due to interference of the line lock clock to the A / D converter, and appears on the screen as horizontal-drawing noise. This horizontal subtraction noise is very small as a luminance change amount, but is very noticeable because it is a low-frequency noise.

[0018]

According to the present invention, there is provided an A / D converter for converting an analog video signal into a digital signal, and a clock synchronized with a burst signal included in the input video signal. , A line lock clock generation circuit that generates a clock synchronized with a horizontal synchronization signal included in the input video signal, and a Y / C separation and color input using the output of the A / D converter as an input. A first signal processing circuit that performs demodulation, synchronization separation, and the like; a second signal processing circuit that performs time axis correction using the burst lock clock and the line lock clock; and a third signal processing that performs scanning line interpolation and the like And a D / A converter for converting a digital signal into an analog signal, wherein the A / D converter and the first signal processing circuit are connected to the burst lock clock. Is operated using the clock, the third signal processing circuit and the D / A converter in the video signal processing circuit having a configuration to operate in the line lock clock,
By setting the clock frequency of the line lock clock generation circuit to a frequency different from the clock frequency of the burst lock clock generation circuit, it is possible to suppress the occurrence of horizontal noise and improve the image quality.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention according to claim 1 of the present invention provides an A / D converter that receives an analog video signal and converts it into a digital signal, and a clock synchronized with a burst signal included in the input video signal. A generated burst lock clock generation circuit, a line lock clock generation circuit for generating a clock synchronized with a horizontal synchronization signal included in an input video signal, and a Y / C separation and color demodulation using an output of the A / D converter as an input. , A first signal processing circuit that performs synchronization separation and the like,
A second signal processing circuit for performing time axis correction using the burst lock clock and the line lock clock, a third signal processing circuit for performing scanning line interpolation and the like, and a D / A converter for converting a digital signal into an analog signal And a container
A video signal processing circuit having a configuration in which the / D converter and the first signal processing circuit are operated by the burst lock clock, and the third signal processing circuit and the D / A converter are operated by the line lock clock. Wherein the clock frequency of the line lock clock generation circuit is set to a frequency different from the clock frequency of the burst lock clock generation circuit, so that the line lock clock interferes with the burst lock system. Has the effect of preventing the generation of noise.

According to a second aspect of the present invention, there is provided an oscillating circuit for oscillating a clock, a frequency dividing circuit for dividing a clock output of the oscillating circuit, a horizontal synchronizing signal separated from an output of the frequency dividing circuit and a video signal. And a phase comparison circuit for comparing the phases of both inputs and outputting a control signal for controlling the oscillation circuit, wherein the oscillation frequency of the oscillation circuit is changed by changing the frequency division ratio of the frequency divider circuit. And a PLL circuit capable of changing the frequency of the line-locked clock by changing the frequency division ratio.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 is a block diagram of a video signal processing circuit according to the present invention. In FIG. 1, 1 is an analog video signal input terminal, 2 is an A / D converter, and 3 is a luminance signal and a chrominance signal. , A color demodulation circuit, 5 a time axis correction circuit, 6 a signal processing circuit for performing, for example, sequential scan conversion, 7 a D / A converter, and 8 and 9 luminance signals, respectively. , A color signal output terminal, 10 is a burst signal extraction circuit for extracting a color burst signal contained in a television signal, 11 is a synchronization separation circuit, 12 is a burst lock PLL circuit for generating a burst lock clock, and 13 is a line lock clock. Is a line lock PLL circuit.

Next, the operation of FIG. 1 will be described. A burst signal is extracted from a video signal converted into a digital signal by the A / D converter 2 by a burst extraction circuit 10, and a burst lock clock is generated by a burst lock PLL circuit 12 based on a color subcarrier frequency (fsc) of the burst signal. Let it. The clock frequency (f1 Hz) is fsc
Is often set to 4 times or 8 times. Writing of data to the A / D converter 2, the Y / C separation circuit 3, the color demodulation circuit 4, and the time axis correction circuit 5 is performed using the burst lock clock. On the other hand, the synchronization separation circuit 11 separates horizontal and vertical synchronization signals included in the input video signal, and inputs the horizontal synchronization signal to the line lock PLL circuit 13 to use it as a reference signal of the line lock clock. Then, the read clock of the time axis correction circuit 5 and the signal processing circuit 6,
By using a line lock clock based on a horizontal synchronizing signal as a clock of the D / A converter 7, a stable system is constructed even for non-standard signals.

Although the description so far is the same as that of the conventional example, in this embodiment, the frequency (f2 Hz) of the line lock clock generated by the line lock PLL circuit 13 is set to a frequency different from the burst lock clock frequency (f1 Hz). It is characterized by:

The effect when the line lock clock is set to a frequency different from the burst lock clock will be described with reference to FIG.

FIG. 2A shows a burst lock clock having a frequency f1 Hz, FIG. 2B shows a line lock clock having a frequency f2 Hz slightly different from the burst lock clock, and FIG. Input signal of the A / D converter (the broken line is the original signal),
(D) is a line-locked clock slightly out of phase with (b), and (e) is a signal disturbed by the line-locked clock (d).

The signal shown in FIG. 2C is sampled by the burst lock clock (a). In this case, a point indicated by a black circle is sampled. However, since the frequency is different from the interference frequency (f2 Hz), each signal is sampled. The level shifts little by little. Further line lock PLL
2 (c) and FIG. 2 (e), the level also changes for each line as shown in FIG. 2 (c) and FIG. 2 (e), so that the luminance change amount appears to change randomly for each pixel. In this case, the influence of the disturbance of the line lock clock is not eliminated. However, since the disturbance level differs for each pixel, the noise is not a low frequency noise in a horizontal line like a conventional example but a random noise. In other words, the effect is such that the horizontal noise is diffused over the entire screen, and the screen is much easier to see than the horizontal noise.

Further, since the noise is no longer low-frequency noise, the noise component can be weakened by a low-pass filter or the like, and the noise feeling can be greatly improved when the entire screen is viewed.

(Embodiment 2) A block diagram of a line lock PLL circuit has the same configuration as that of FIG.

Here, differences from the conventional example will be described. In the conventional example, for example, the clock is 4
If the frequency is about 14.3 MHz, the frequency is divided by 910 and the frequency is multiplied by about 2
In the case of 8.6 MHz, the frequency was divided by 1820, but in this embodiment, the line lock clock frequency is changed by changing the frequency division ratio. The line-lock PLL circuit outputs a horizontal synchronizing signal (15.734 kHz) as a reference pulse.
In order to adjust the frequency to z), for example, if the frequency division ratio of the frequency dividing circuit 19 is slightly changed and set to 920, the line lock clock frequency is 15.7334 kHz × 920 =
14.475 MHz, 14.3 MHz of 4 × fsc
can be higher than z.

By changing the frequency division ratio of the frequency divider in the line-locked PLL circuit, the frequency of the line-locked clock can be easily changed, and the horizontal noise can be improved without increasing the cost compared to the conventional circuit. Can be.

[0031]

As described above, according to the present invention, the horizontal frequency noise generated by the disturbance of the line lock clock can be reduced by slightly shifting the clock frequency of the line lock PLL circuit from the frequency of the burst lock clock. Thus, it is possible to realize a good reception state in which noise is less noticeable.

[Brief description of the drawings]

FIG. 1 is a block diagram of a video signal processing circuit according to an embodiment of the present invention;

FIG. 2 is a waveform chart for explaining the effect of FIG. 1;

FIG. 3 is a block diagram of a conventional video signal processing circuit.

FIG. 4 is a block diagram showing an example of a line lock PLL circuit.

FIG. 5 is a waveform diagram illustrating a conventional problem.

[Explanation of symbols]

 Reference Signs List 3 Y / C separation circuit 5 Time axis correction circuit 6 Signal processing circuit 12 Burst lock PLL 13 Line lock PLL 15 Phase comparison circuit 18 Oscillator 19 Frequency dividing circuit

Claims (2)

[Claims] 1. An A / D converter that receives an analog video signal and converts it into a digital signal, a burst lock clock generation circuit that generates a clock synchronized with a burst signal included in the input video signal, and a burst lock clock generation circuit that is included in the input video signal A line-locked clock generation circuit for generating a clock synchronized with a horizontal synchronization signal to be output, a first signal processing circuit which receives an output of the A / D converter as input, and performs Y / C separation, color demodulation, synchronization separation, and the like; A second signal processing circuit for performing time axis correction using the burst lock clock and the line lock clock, a third signal processing circuit for performing scanning line interpolation and the like, and a D / A converter for converting a digital signal into an analog signal A / D converter and the first signal processing circuit are operated by the burst lock clock, and the third signal processing circuit and the D / A The converter is a video signal processing circuit having a configuration operated by the line lock clock,
A video signal processing circuit, wherein a clock frequency of the line lock clock generation circuit is set to a frequency different from a clock frequency of the burst lock clock generation circuit. 2. A line lock clock generation circuit,
An oscillation circuit for oscillating a clock, a frequency dividing circuit for dividing the clock output of the oscillation circuit, and an output of the frequency dividing circuit and a horizontal synchronizing signal separated from a video signal are input, and the phases of both inputs are compared. A phase comparison circuit that outputs a control signal for controlling the oscillation circuit; and a PLL circuit that can change the oscillation frequency of the oscillation circuit by changing the frequency division ratio of the frequency division circuit. The video signal processing circuit according to claim 1, wherein