JP2714193B2 - Digital television receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital television receiver, and more particularly, to whether a video signal to be input is a standard signal or a non-standard signal,
The present invention relates to a digital television receiver provided with a clock generation device that controls a clock used in a synchronization signal generation circuit and a signal processing circuit.

[Conventional technology]

FIGS. 4 (a) and 4 (b) are block diagrams each showing a conventional clock generator.

4 (a) and 4 (b), 1 is a video signal input terminal, 2 is a line lock clock generating circuit, 3 is a line lock clock, 4 is a burst lock clock generating circuit,
5 is a burst lock clock, 9 is a synchronization signal generation circuit,
Reference numeral 10 denotes a signal processing circuit, 11 denotes a synchronization signal output terminal, and 12 denotes a video signal output terminal.

 First, the circuit of FIG. 4A will be described.

The burst lock clock generation circuit 4 uses a crystal oscillator (not shown) to generate a stable burst lock clock 5 synchronized with a color burst signal included in the video signal input from the video signal input terminal 1. here,
The input video signal is a signal conforming to the standard television broadcasting system (hereinafter, abbreviated as a standard signal), and the frequency (fsc) of the color burst signal included in the standard signal.
And the frequency of the horizontal sync signal (f _H ) It has become.

Next, the synchronizing signal generating circuit 9 receives the burst lock clock 5 from the burst lock clock generating circuit 4 and generates a synchronizing signal using the relation of the equation (1).

Further, the signal processing circuit 10 includes a video signal input from the video signal input terminal 1 and a burst lock clock generation circuit 4.
, And performs signal processing on the video signal using the relationship of equation (1) to improve the image quality of the video signal. Examples of conventional circuits for improving the image quality of such video signals include, for example, those disclosed in
No. -18085.

 Next, the circuit of FIG. 4B will be described.

The line lock clock generation circuit 2 generates a line lock clock 3 synchronized with a horizontal synchronization signal included in a video signal input from the video signal input terminal 1.

Next, the synchronization signal generation circuit 9 receives the line lock clock 3 from the line lock clock generation circuit 2 and generates a synchronization signal.

The signal processing circuit 10 receives the video signal input from the video signal input terminal 1 and the line lock clock 3 from the line lock clock generation circuit 2, and performs signal processing on the video signal.

[Problems to be solved by the invention]

In the prior art described above, first, in the circuit of FIG. 4 (a), when the video signal input to the video signal input terminal 1 is a standard signal, a very stable synchronization signal can be generated and the video signal can be generated. Image quality can be improved.

However, a signal that does not strictly comply with the standard for the standard television broadcasting system (hereinafter, abbreviated as a non-standard signal), such as a video signal reproduced from a VTR (video tape recorder), that is, (1) Since such a non-standard signal is not taken into account when the relationship of the equation is not maintained, it is not possible to improve the image quality, that is, to improve the image quality, and to obtain synchronization if such a non-standard signal is input. There was a problem.

On the other hand, in the circuit of FIG. 4 (b), since the horizontal synchronization signal is used as a reference, sufficient synchronization can be obtained even when a non-standard signal is input, and therefore, images from various devices having different pull-in ranges are obtained. It is possible to respond to signals. As for the improvement of the image quality, when a non-standard signal is input, the non-standard signal does not maintain the relationship of the expression (1) as described above, so that the image quality can be improved in a range where the relationship is not used. It is.

However, when a standard signal is input, the standard signal maintains the relationship of equation (1). In the circuit of FIG. 4B, however, the oscillator (not shown) of the line lock clock generating circuit 2 Is not as high as the crystal oscillator (not shown) of the burst lock clock generation circuit 4 of the circuit of FIG. 4A and the stability of the generated clock is low. When trying to improve the image quality by utilizing the relationship, the effect of the improvement was low.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to improve the image quality of a signal processing circuit, whether a standard signal or a non-standard signal is input, that is, to improve the image quality. It is possible to provide an optimal clock that can improve the performance of the synchronization signal generator circuit. An object of the present invention is to provide a digital television receiver provided with a clock generation device capable of providing an optimal clock so that an extremely stable synchronization signal can be generated when the signal is input.

[Means for solving the problem]

In order to achieve the above object, according to the present invention, a first clock generating means for generating a first clock (burst lock clock) synchronized with an integer multiple of a frequency of a color burst signal included in an input video signal, Second clock generating means for generating a second clock (line lock clock) synchronized with an integral multiple of the frequency of the horizontal synchronizing signal included in the video signal, and detecting whether the video signal is a standard signal or a non-standard signal Detecting means, the first and second clocks are input, the first clock is selected when the detecting means detects a standard signal, and the second clock is selected when the non-standard signal is detected. Selecting means for selecting and outputting; synchronizing signal generating means operating on the second clock; and signal processing means operating on the clock output from the selecting means. In the digital television receiver, the second clock generating means includes: (a) frequency dividing means for dividing the output signal of the second clock by N (where N is a natural number) and outputting the divided signal; Phase comparing means for inputting an output signal from the frequency dividing means and a horizontal synchronizing signal included in the video signal, comparing the phases of the two, and outputting a signal corresponding to the comparison result; Low-pass filter means for extracting a low-frequency component of the output signal from the phase comparison means and outputting it as a control voltage; and (d) oscillating at a frequency corresponding to the control voltage from the low-pass filter means. Voltage-controlled oscillating means for outputting an oscillation output as the second clock; and
Phase control means for adding the AC component of the clock to the control voltage from the low-pass filter means to synchronize the phase of the second clock with the phase of the first clock. It is a feature.

In the present invention, the selection means is deleted from the above configuration,
The signal processing means may be operated by a second clock (line lock clock).

[Action]

In the present invention, the detection unit detects whether the video signal is a standard signal or a non-standard signal, and only when the video signal is detected as a standard signal, the phase control unit detects the line signal. The lock clock is phase-synchronized with the burst lock clock.

For the signal processing circuit, a line lock clock is input when a non-standard signal is input, and a burst lock clock or a line lock clock synchronized with the burst lock clock when a standard signal is input. , Respectively, the signal processing circuit can improve the image quality, that is, improve the image quality even when a standard signal or a non-standard signal is input.

For the synchronization signal generation circuit, a line lock clock having an original wide pull-in range is input when a non-standard signal is input, and a line lock clock synchronized with the burst lock clock is input when a standard signal is input. Since a lock clock is provided, the synchronization signal generation circuit can synchronize even if any non-standard signal is input from various devices having different pull-in ranges, and the standard signal can be obtained. When input, an extremely stable synchronization signal can be generated.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, 101 is a video signal input terminal, 102 is a line lock clock generation circuit, 103 is a line lock clock, 104 is a burst lock clock generation circuit, 105 is a burst lock clock, 106 is a standard / non-standard signal detection circuit, 108a and 108b are switches, 109 is a synchronization signal generation circuit, 110 is a signal processing circuit, 111 is a synchronization signal output terminal, 11
2 is a video signal output terminal, 113 is a sync separation circuit, 114 is 1820
A frequency divider, 115 is a low-pass filter (LPF), 116 is a capacitor, 118 is a phase comparator, 119 is a voltage controlled oscillator, and 120 is an adder.

 Now, the operation of the present embodiment will be described.

The video signal input from the video signal input terminal 101 is input to a line clock generation circuit 102, a burst lock clock generation circuit 104, and a standard / non-standard signal detection circuit 106. In line lock clock generator circuit 102, separated by the synchronization separation circuit 113 a horizontal synchronization signal included in the video signal, the line lock clock 103 with a 1820 times the frequency of the frequency f _H of the horizontal synchronizing signal, a phase comparator 118, L
It is generated by a phase locked loop (PLL) circuit composed of a PF 115, an adder 120, a voltage controlled oscillator 119, and a frequency divider 114.

The burst lock clock generation circuit 104 extracts a color burst signal included in the video signal, and generates a burst lock clock 105 having a frequency eight times the frequency fsc using a crystal oscillator (not shown). Let me. As described above, since the burst lock clock 105 is generated by the crystal oscillator, it is a very stable clock.

Next, the synchronization signal generation circuit 109 always receives the line lock clock 103 and divides the clock 103 to obtain a synchronization signal synchronized with the horizontal synchronization signal of the input video signal and output the synchronization signal. Output from terminal 111.

Further, the standard / non-standard signal detection circuit 106, between the frequency fsc of a frequency f _H and the color burst signal of the horizontal synchronizing signal of the input video signal, whether a relationship of the aforementioned equation (1) If it is detected that there is a relationship, it is determined that the input video signal is a standard signal. If it is detected that there is no relationship, it is determined that the input video signal is a non-standard signal. Is output as a detection signal. In addition,
Known examples of such standard / non-standard signal detection circuits include:
For example, JP-A-61-184082 can be mentioned.

Next, the switch 108a is connected to the standard / non-standard signal detection circuit 10
Input the detection signal from 6, if the input video signal is a non-standard signal, to the line lock clock side,
When the signal is a standard signal, the signal is closed to the burst lock clock side, and each clock is output to the signal processing circuit 110. The signal processing circuit 110 inputs a video signal from the video signal input terminal 101, performs digital signal processing using a clock supplied from the switch 108a, and achieves high image quality. Then, the processed video signal is output from the video signal output terminal 112.

 Next, the operation of clock phase control will be described.

The burst lock clock generation circuit 104 also outputs the burst lock clock 105 to the switch 108b. Switch 1
08b is controlled by a detection signal from a standard / non-standard signal detection circuit similarly to the switch 108a. When the input video signal is a standard signal, the switch is closed, and when the input video signal is a non-standard signal, the switch is opened. Therefore, switch 108b
Is a burst lock clock only when it is a standard signal.
5 is supplied to the line lock clock generation circuit 102.

The line lock clock generation circuit 102 includes a switch 108b
When the burst lock clock 105 is supplied, the operation is performed so that the phase of the output line lock clock 103 matches the phase of the burst lock clock 105.

Here, the operation of the line lock clock generation circuit 102 will be described in more detail.

First, the synchronization separation circuit 113 separates a horizontal synchronization signal included in the video signal input from the video signal input terminal 101,
Input to one input of phase comparator 118. 1820 divider 114
Divides the line-locked clock 103 output from the voltage-controlled oscillator 119 by 1820 and outputs the divided output to the phase comparator 118
To the other input of. Phase comparator 118 compares the phase of the input horizontal synchronization signal with the frequency-divided output from 1820 frequency divider 114, and outputs a voltage according to the phase difference. Then, LPF 115 extracts only the low-frequency component from the output voltage of phase comparator 118 and inputs the same to one input of adder 120. The voltage control oscillator 119 receives the control voltage output from the adder 120, oscillates at a frequency corresponding to the control voltage, and outputs the oscillation output as the line lock clock 103.

When the burst lock clock 105 is input from the switch 108b, the capacitor 116 removes the DC component of the burst lock clock 105, inputs only the AC component to the other input of the adder 120, and
When nothing is input from b, nothing is input to the adder 120. When the AC component of the burst lock clock 105 is input from the capacitor 116, the adder 120 adds (superimposes) the AC component of the burst lock clock 105 to the previously input output from the LPF 115, as described above. It is input to the voltage controlled oscillator 119 as a control voltage. Conversely, when nothing is input from the capacitor 116, the previously input output from the LPF 115 is directly input to the voltage control oscillator 119 as the above-described control voltage.

Therefore, the video signal input to the video signal input terminal 101 is a non-standard signal, and the capacitor
When nothing is input to the clock, the line lock clock 103 output from the voltage controlled oscillator 119 is a clock synchronized with the horizontal synchronization signal.

Conversely, when the video signal is a standard signal and the burst lock clock 105 is input to the capacitor 116 from the switch 108b, the line lock clock 103, which is the output of the voltage controlled oscillator 119, is synchronized with the clock phase-synchronized with the burst lock clock 105. Become. For such a circuit operation, refer to “Nonlinear Circuit Theory” by Masamichi Shimura (Electronic Circuit Course 3), pp. 69-74.

Next, the line lock clock generation circuit 102 and the switch 1
The specific configuration of 08b will be described with reference to FIG.

In FIG. 2, SW is a switch circuit, R1 to R10 are resistors, C1 to C6 are capacitors, D1 is a diode, L1 is a coil, and TR1 to TR4 are transistors.

As shown in FIG. 2, the phase comparator 118
Switch circuit SW using horizontal synchronization signal from 13 as control signal
The LPF 115 is composed of resistors R ₁ and R ₂ and a capacitor C1. The adder 120 is configured as a connection point between signal lines.

Further, the switch 108b includes transistors TR3 and TR4,
R9 to R11 and a capacitor C6. When the output from the standard / non-standard signal detection circuit 106 is at "H" level, the transistor T
Since R4 turns on and the emitter of transistor TR3 falls to ground, burst lock clock 105
Does not pass to Conversely, standard / non-standard signal detection circuit 10
When the output from 6 is at "L" level, the transistor TR4 is turned off and the collector of the transistor TR4 operates so that the burst lock clock 105 is transmitted to the capacitor 116, and only the AC component thereof is added to the adder 120. Is input to

Incidentally, the resistor R9 is for attenuating the signal amplitude of the burst lock clock 105. If the signal amplitude of the burst lock clock 105 is too large, the energy for causing the line lock clock generation circuit 102 to perform phase synchronization also increases, and noise is mixed into the video signal from the video signal input terminal 101, and the phase comparator 118 The line lock clock generation circuit 102 also synchronizes with the burst lock clock 105 even when the output is disturbed. Then, the phase comparator 118 works so as to hold the DC value of the output of the phase comparator 118 at the time of disturbance. Considering this on the input side of the phase comparator 118, the video signal input terminal 101
This means that the output of the 1820 frequency divider 114 is locked at a position different from the original phase relationship to be synchronized with the phase of the video signal from. That is, the image is not displayed at the correct horizontal position, but is displayed at a shifted position.

On the other hand, if the signal amplitude of the burst lock clock 105 is too small, the line lock clock generation circuit 102 causes phase synchronization. The energy is reduced, and the burst lock clock 105 is supplied to the line lock clock generation circuit 102.
Can not affect. Therefore, the line lock clock 103 is not synchronized with the burst lock clock 105 even at the time of the standard signal, so that the burst lock clock 105
Must be larger than a certain level. As described above, the amplitude level of the burst lock clock 105 is large enough to cause phase synchronization in the line lock clock generation circuit 102, and small so that phase synchronization does not occur when the output of the phase comparator 118 is greatly disturbed. Is attenuated.

By the way, when the switch 108b is controlled by the output from the standard / non-standard signal detection circuit 106, the output from the standard / non-standard signal detection circuit 106 is passed through the LPF composed of the resistor R11 and the capacitor C7, and then the base of the transistor TR4. , The control is gently applied, and the switching can be made inconspicuous.

Next, a second embodiment of the present invention will be described with reference to FIG.

3, the same components as those in FIG. 1 are denoted by the same reference numerals.

The operation of the present embodiment is different from the embodiment of FIG. 1 in that the signal processing circuit 110 is always operated by the line lock clock 103 from the line lock clock generation circuit 102, similarly to the synchronization signal generation circuit 109. It is.

 Hereinafter, the operation will be described.

First, when the video signal input to the video signal input terminal 101 is a non-standard signal, the switch 108b is opened, and the burst lock clock 105 from the burst lock clock generation circuit 104 is not transmitted to the adder 120 via the capacitor 116. , No phase synchronization control is performed.

However, when the signal is a standard signal, the switch 108b is closed, and the burst lock clock 105 from the burst lock clock generation circuit 104 is transmitted to the adder 120 via the switch 108b and the capacitor 116. Accordingly, as in the first embodiment, the line lock clock generation circuit 102 adjusts the phase of the output line lock clock 103 so as to synchronize with the phase of the burst lock clock 105.

Then, in the case of a non-standard signal, the synchronization signal generation circuit 10
9 and the signal processing circuit 110
On the other hand, at the time of the standard signal, on the other hand, the line lock clock 103 equivalent to the burst lock clock 105 in terms of substantially less jitter is supplied to both the synchronization signal generation circuit 109 and the signal processing circuit 110. Will be.

As described above, in each of the embodiments, when the video signal input from the video signal input terminal 101 is a non-standard signal, the line lock clock 103 having a wide synchronization pull-in range and good tracking performance with respect to jitter and the like is provided. Is supplied to the synchronization signal generation circuit 109 and the signal processing circuit 110, and when the signal is a standard signal, the line lock clock 103 is synchronized with the burst lock clock 105 to be highly stable, and the synchronization signal generation circuit 1
In addition, the signal processing circuit 110 is supplied with a burst lock clock 105 (first embodiment) or a line lock clock 103 (second embodiment).

Therefore, in the synchronization signal generation circuit 109, synchronization can be achieved regardless of what kind of non-standard signal is input, and extremely stable generation of a synchronization signal is performed when a standard signal is input. be able to. In addition, the signal processing circuit 11
At 0, high image quality can be achieved regardless of whether a standard signal or a non-standard signal is input.

Further, as described above, in the first embodiment, when a standard signal is input, different clocks are given to the synchronization signal generation circuit 109 and the signal processing circuit 110. However, both clocks are used. Because they are synchronized, there is no problem such as interference due to beats or screen shaking.

〔The invention's effect〕

In the present invention, a line lock clock (a clock generated in synchronization with a horizontal synchronization signal included in an input video signal) is changed to a burst lock clock (a clock generated in synchronization with a color burst signal included in the video signal). ), Synchronization is performed only when the video signal is a standard signal.

For the signal processing circuit, a line lock clock is input when a non-standard signal is input, and a burst lock clock or a line lock clock synchronized with the burst lock clock when a standard signal is input, Since each signal is given, the signal processing circuit can improve the image quality, that is, improve the image quality even when a standard signal or a non-standard signal is input.

In addition, a line lock clock is supplied to the synchronization signal generation circuit when a non-standard signal is input, and a line lock clock synchronized with the burst lock clock is supplied when a standard signal is input. Therefore, the synchronizing signal generation circuit can synchronize regardless of what kind of non-standard signal is input, and generate a very stable synchronizing signal when a standard signal is input. It can be carried out.

When a standard signal is input, a different clock such as a burst lock clock may be applied to the signal processing circuit and a line lock clock may be applied to the synchronization signal generation circuit. However, the standard signal is input. When the two clocks are synchronized, there is no problem such as interference due to beats and screen shaking.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
The figure shows the line lock clock generation circuit 102 in FIG.
FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIGS. 4 (a) and 4 (b) are blocks each showing a conventional clock generator. FIG. 101: Video signal input terminal, 102: Line lock clock generation circuit, 103: Line lock clock, 104: Burst lock clock generation circuit, 105: Burst lock clock, 106: Standard / non-standard signal detection circuit 108a, 108b switch, 109 synchronous signal generation circuit, 110 signal processing circuit, 118 phase comparator, 119 voltage controlled oscillator, 120 adder, 114 1820 frequency divider , 115 …… LPF.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Sekiya 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Video Engineering Co., Ltd. (72) Inventor Toshinori Murata 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Inside the Home Appliances Research Laboratory (72) Inventor Kazuhiro Kaizaki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Yokohama Factory, Hitachi, Ltd. (72) Takaaki Matino 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. (56) References JP-A-63-276994 (JP, A) JP-A-1-175480 (JP, A) JP-A-1-175481 (JP, A)

Claims (3)

(57) [Claims] A first clock generating means for generating a first clock synchronized with a frequency which is an integral multiple of a frequency of a color burst signal included in an input video signal; and an integer multiple of a horizontal synchronizing signal included in the video signal. Second clock generating means for generating a second clock synchronized with a frequency, detecting means for detecting whether the video signal is a standard signal or a non-standard signal,
When the first and second clocks are input and the detecting means detects a standard signal, the first clock is selected, and when the non-standard signal is detected, the second clock is selected and output. A digital television receiver, comprising: a selection unit that performs the second clock generation; a synchronization signal generation unit that operates with the second clock; and a signal processing unit that operates with the clock output from the selection unit. Means: (a) frequency dividing means for dividing and outputting the second clock, which is the output signal, by N (where N is a natural number); and (b) an output signal from the frequency dividing means and the video signal. Phase comparison means for inputting the horizontal synchronization signal included in the phase comparison means, comparing the phases of the two, and outputting a signal corresponding to the comparison result; and (c) calculating the low frequency component of the output signal from the phase comparison means. Extract and control electricity Low-pass filter means for outputting as a voltage; (d) voltage-controlled oscillating means for oscillating at a frequency corresponding to a control voltage from the low-pass filter means and outputting the oscillation output as the second clock; When the detection means extracts a standard signal, an AC component of the first clock is added to the control voltage from the low-pass filter means, and the phase of the second clock is A digital television receiver comprising a phase control means configured to synchronize the phase with one clock phase. 2. A first clock generating means for generating a first clock synchronized with an integer multiple of a frequency of a color burst signal included in an input video signal, and an integer multiple of a horizontal synchronization signal included in the video signal. Second clock generating means for generating a second clock synchronized with a frequency, detecting means for detecting whether the video signal is a standard signal or a non-standard signal,
A synchronous signal generating means operating on the second clock; and a signal processing means, wherein the second clock generating means: (a) outputs the second clock as an output signal to N (where N is a natural number) Frequency dividing means for dividing and outputting; and (b) inputting an output signal from the frequency dividing means and a horizontal synchronizing signal included in the video signal, comparing the phases of the two, and according to the comparison result, (C) low-pass filter means for extracting a low-frequency component of the output signal from the phase comparison means and outputting the same as a control voltage; and (d) low-pass filter means. And a voltage-controlled oscillating unit that oscillates at a frequency according to the control voltage from and outputs the oscillation output as the second clock. When the detecting unit detects a standard signal, The AC component of the clock is A digital television receiver comprising phase control means configured to add the control voltage from the band-pass filter means to synchronize the phase of the second clock with the phase of the first clock. . 3. An AC component of the first clock added to a control voltage from the low-pass filter by the phase control means is adjusted to a predetermined level. A digital television receiver according to item 1.