JP2661300B2 - Control method of image sampling clock - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of controlling an image sampling clock when an NTSC composite video signal is converted from analog to digital (hereinafter, referred to as A / D).

[Conventional technology]

FIG. 2 is a block diagram of an image sampling clock control device conventionally used in a television receiver having a digital image processing unit. In FIG.
Is a band-pass filter for inputting the NTSC composite video signal and passing the band of the color subcarrier frequency band. The frequency of the color subcarrier extracted from the NTSC composite video signal by the band-pass
Extracts only the color burst portion and sends it to a phase locked loop 3 (hereinafter, referred to as a PLL circuit).

The PLL circuit 3 generates a clock synchronized with the color burst signal, and supplies one input terminal of the clock switching circuit 6
Output to 6a.

On the other hand, reference numeral 4 denotes a horizontal synchronization separation circuit for extracting a horizontal synchronization signal from the NTSC composite video signal. The horizontal synchronization signal extracted by the horizontal synchronization separation circuit 4 is sent to a PLL circuit 5.

The PLL circuit 5 generates a clock synchronized with the horizontal synchronization signal and outputs the clock to the input terminal 6b of the clock switching circuit 6.

The clock switching circuit 6 switches between the clock generated by the PLL circuit 3 and the clock generated by the PLL circuit 5 by a switching control signal, and outputs a sampling clock from the output terminal 6c.

Next, the operation will be described. The bandpass filter 1 extracts the frequency band of the chrominance subcarrier from the NTSC composite video signal, and the burst separation circuit 2 extracts only the color burst portion from the extracted chrominance subcarrier and inputs it to the PLL circuit 3.

In the PLL circuit 3, in synchronization with the color subcarrier, and the color subcarrier frequency f of the frequency of an integral multiple of _SC clock 2Kf _SC
(K is a natural number) is generated and input to the input terminal 6a of the clock switching circuit 6.

On the other hand, the horizontal synchronization signal extracted from the NTSC composite video signal by the horizontal synchronization separation circuit 4 is input to the PLL circuit 5.

This PLL circuit 5 synchronizes with a horizontal synchronizing signal,
A clock 455 kf _H having a frequency that is an integral multiple of the horizontal scanning frequency f _H as a horizontal synchronization frequency is generated and input to the input terminal 6 b of the clock switching circuit 6.

The clock switching circuit 6 has two types of clocks,
A switching control signal for switching between these two types of clocks is input, and the state of the switching control signal causes a clock 2 having a frequency that is an integral multiple of the color subcarrier frequency f _SC generated by the PLL circuit 3 to be changed.
It is possible to select kf _SC and a clock 455 kf _H having a frequency that is an integral multiple of the horizontal scanning frequency f _H generated by the PLL circuit 5 and use either of them as a sampling clock.

Clock 2Kf _SC is selected if it meets a condition that is twice the frequency of the color subcarrier frequency f _SC is equal to 455 times the frequency of the horizontal scanning frequency f _H, the clock 455Kf _H is selected to satisfy the condition.

[Problems to be solved by the invention]

As described above, the method of the conventional image sampling clock is used. Assuming that two types of clocks to be switched are very close, a screen may be disturbed by interference between the two clocks.

Also, while a continuous video signal is being input,
When the sampling clock is switched, there is a problem that the position of the screen is shifted before and after the switching.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem. When two types of clocks satisfying each of two types of conditions where interference is likely to occur input a video signal determined to have the same frequency, It is another object of the present invention to provide an image sampling clock control method capable of eliminating interference caused by interference and minimizing a screen position shift when a required condition is switched.

[Means for solving the problem]

A method of controlling an image sampling clock according to the present invention is a method of outputting a first clock synchronized with a color subcarrier extracted from an input NTSC composite video signal and having a frequency that is an integral multiple of the color subcarrier frequency. And a second clock synchronized with the horizontal synchronization signal extracted from the input NTSC composite video signal and having a frequency close to the frequency of the first clock and equal to a frequency that is an integral multiple of the horizontal synchronization frequency. A second PLL circuit for outputting, a judging means for judging whether or not the frequency twice as high as the color subcarrier frequency is equal to 455 times the horizontal synchronizing frequency, and a first clock according to the output of the judging means And a gate element for controlling the passage of the image sampling clock, wherein the determination means determines that the frequency twice as high as the color subcarrier frequency is 455 times as high as the horizontal synchronization frequency. If it is determined that the clock is not correct, the first clock passed through the gate element is mixed into the voltage controlled oscillator constituting the second PLL circuit, and the clock synchronized with the first clock is used as the second image sampling clock. If the judgment means judges that the frequency twice as high as the color subcarrier frequency is not equal to the frequency 455 times as high as the horizontal synchronization frequency, the output of the second PLL circuit is the second one. It is characterized in that the clock is directly output as an image sampling clock.

(Operation)

In the control method of the image sampling clock according to the present invention, the first clock output from the first PLL circuit is always synchronized with the color subcarrier and always has a frequency that is an integral multiple of the color subcarrier frequency.

Further, the passage of the first clock is controlled using a gate element according to the output of the judging means.

〔Example〕

Hereinafter, an embodiment of a method for controlling an image sampling clock according to the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of an apparatus to which the embodiment is applied. In FIG. 1, the same parts as those in FIG.

In FIG. 1, a color subcarrier frequency band is extracted from an NTSC composite video signal by a band-pass filter 1, and
By inputting the frequency of the color subcarrier to the color burst separation circuit 2, only the color burst portion is extracted by the color burst separation circuit 2.

The color burst portion extracted by the color burst separation circuit 2 is sent to a phase comparator 7 as a reference phase. The phase comparator 7 has the same frequency as the color burst signal output from the frequency divider 10. f _{SC is} also input.

The phase comparator 7 compares the phase of the output f _SC of the frequency divider 10 with the color burst portion as a reference phase, and outputs the phase difference to the low-pass filter 8 as a voltage.

The low-pass filter 8 allows the low-frequency portion of the voltage output from the phase comparator 7 to pass, and
VCO).

The VCO 9 oscillates a clock of an integral multiple of the color subcarrier frequency f _SC (in this embodiment, 2 k times, where k is a natural number).
The clock 2kf _SC is sent to the gate element 16 and the frequency divider 10.

The frequency divider 10 divides the frequency of the clock 2kf _SC into 1 / 2k, and thus the phase comparator 7, the low-pass filter 8, the VC
The O9 and the frequency divider 10 constitute a first PLL circuit.

On the other hand, the horizontal sync separator 11 is adapted to separate the horizontal synchronizing signal from the NTSC composite video signal, the horizontal synchronization signal f _H is arranged to output to the phase comparator 12.

The phase comparator 12 uses this horizontal synchronization signal as a phase reference,
As a voltage the phase difference by the phase comparison between the horizontal scanning frequency f _H that is output from the frequency divider 15, and outputs to the low-pass filter 13.

The low-pass filter 13 allows the low-pass voltage of the output voltage of the phase comparator 12 to pass therethrough and outputs it to the VCO 14.

This VCO14 oscillates a clock of an integral multiple of the horizontal scanning frequency f _H (455k multiples in this embodiment, k is a natural number).

In this embodiment, the frequency divider 15 is a VCO 14
The output frequency 455kf _H is divided by 1 / 455k.

Thus, the phase comparator 12, low-pass filter 13, VCO1
4. The frequency divider 15 forms a second PLL circuit.

Further, the gate element 16 has a frequency output from the VCO 9.
The switching of the 2kf _SC clock is controlled by a switching control signal, and the clock of an integral multiple of the color subcarrier frequency and the clock of an integral multiple of the horizontal scanning frequency have the same frequency. When the required sampling clock frequency condition is a frequency that is an integral multiple of the color subcarrier frequency, the frequency 2kf
Pass _SC clock, otherwise 2k frequency
f Block the _SC clock.

The current of the clock passing through the gate element 16 is
And only the AC component is mixed into the VCO 14 by the capacitor 18.

The VCO 14 outputs an image sampling clock of 455 kf _H.

Next, the operation will be described. The bandpass filter 1 extracts a signal in the color subcarrier frequency band from the NTSC composite video signal, and the burst separation circuit 2 extracts only the color burst portion, which is input to a phase comparator 7 as a reference phase.

The phase comparator 7 compares the comparison phase of the same frequency f _SC as the color burst output from the frequency divider 10 with the reference phase, and
The phase difference is output to the low-pass filter 8 as a voltage.

The low-pass filter 8 removes the high frequency band of the phase difference voltage and inputs the same to the VCO 9. In the VCO 9, the oscillation frequency 2kf _SC of the output clock is changed according to the change in the input phase difference voltage.

The clock generated by the VCO 9 is frequency-divided by the frequency divider 10 into 1 / 2k, and fed back to the phase comparator 7.

In this way, the phase comparator 7, the low-pass filter 8, the VCO 9, and the frequency divider 10 operate as a PLL circuit, and the oscillation frequency 2kf _SC of the VCO 9 is always synchronized with the chrominance subcarrier, and the integer of the chrominance subcarrier. It is controlled to double.

On the other hand, the horizontal sync separator 11 extracts a horizontal sync signal from the NTSC composite video signal, and inputs this horizontal sync signal to the phase comparator 12 as a reference phase. The phase comparator 12, the low-pass filter 13, the VCO 14, and the frequency divider 15 constitute a PLL circuit,
The phase comparator 7, the low-pass filter 8, the VCO 9, the frequency divider
The same operation as the PLL circuit configured by 10 is performed.

However, generating clock here VCO14 in synchronization with the horizontal scanning frequency f _H, and oscillates at an integral multiple of the frequency 455Kf _H of the horizontal scanning frequency f _H.

If the NTSC composite video signal input is Is determined as a standard signal (2 kf _SC = 455 kf _H ), the gate 16 is controlled by the switching control signal to pass the clock of 2 kf _SC , the current is limited by the resistor 17, and the capacitor 18 Then, the clock component of frequency 2kf _SC , which is extracted only by the AC component and attenuated to an extremely small amplitude, is mixed into the oscillation unit of the VCO 14.

Thus, the oscillation clock of the VCO 14 is synchronized with a clock that is an integral multiple of the color subcarrier. Therefore, a clock that satisfies the condition of an integral multiple of the color subcarrier is output as an image sampling clock.

Also, In the case of a video signal input that does not result in
The switching control signal works so as to prevent the clock of f _{SC from} being mixed into the VCO 14. In this case, a clock that satisfies only the condition of an integral multiple of the horizontal scanning frequency is output as an image sampling clock.

〔The invention's effect〕

According to the method of controlling the image sampling clock according to the present invention, since the first PLL circuit is used, the first clock output from the first PLL circuit is always synchronized with the color subcarrier, and the color Since the frequency of the sub-carrier frequency is an integral multiple of the frequency, the image sampling clock output from the second PLL circuit always has the color when the frequency twice the color sub-carrier frequency is equal to the frequency 455 times the horizontal synchronization frequency. Synchronized to the subcarrier,
It always has a frequency that is an integral multiple of the color subcarrier frequency.

Further, since the passage of the first clock is controlled by using the gate element in accordance with the output of the judging means, it is possible to eliminate interference between two kinds of clocks having different frequencies and to input a continuous NTSC composite video signal. The displacement of the image caused by switching between two types of clocks having different frequencies during the period can be minimized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an apparatus to which an image sampling clock control method according to one embodiment of the present invention is applied, and FIG. 2 is a block diagram showing a conventional image sampling clock control apparatus. 1 ... band-pass filter, 2 ... burst separation circuit, 7,
12… Phase comparator, 8,13 …… Low-pass filter, 9,14…
… VCO, 10, 15… Divider, 11… Horizontal sync separation circuit, 16
... Gate element. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A first clock for synchronizing with a chrominance subcarrier extracted from an input NTSC composite video signal and outputting a first clock having a frequency that is an integral multiple of the chrominance subcarrier frequency.
A PLL circuit, and a second clock synchronized with the horizontal synchronization signal extracted from the input NTSC composite video signal and having a frequency close to the frequency of the first clock and equal to an integral multiple of the horizontal synchronization frequency. A second PLL circuit that outputs the following: a determination circuit that determines whether a frequency twice as high as the color subcarrier frequency is equal to a frequency 455 times the horizontal synchronization frequency; A method of controlling an image sampling clock using a gate element for controlling passage of the first clock, wherein the determination means determines that a frequency twice as high as the color subcarrier frequency is 455 times as high as the horizontal synchronization frequency. If it is determined that the frequency is equal to the frequency, the first clock that has passed through the gate element is mixed into the voltage-controlled oscillator that constitutes the second PLL circuit, and the same as the first clock. The second clock is output to the second PLL circuit as an image sampling clock, and when the determination unit determines that the frequency twice as high as the color subcarrier frequency is not equal to the frequency 455 times as high as the horizontal synchronization frequency, Is a method for controlling an image sampling clock, wherein the second clock output from the second PLL circuit is directly output as an image sampling clock.