JPH08125884A - Pll circuit - Google Patents

Abstract

PURPOSE: To extend the lock range of a PLL circuit to generate a system clock to be used for video digital processing. CONSTITUTION: A voltage controlled oscillation circuit 4 to generate the first clock signal of required frequency, a frequency converting part 5 to convert the frequency of the first clock signal and output it as the second clock signal of the required frequency, a frequency divider 6 to frequency-divide the second clock signal into the required frequency, a phase comparing part 2 to phase- compare the clock signal from the frequency divider and a horizontal synchronizing signal S1, a low pass filter 3 to take an oscillation frequency control signal out of phase comparison output from the phase comparing part and impress the same oscillation frequency control signal to the voltage controlled oscillation circuit, a frequency comparing part 7 to compare the horizontal synchronizing signal and the second clock signal and output the signal based on this comparison, and a control part 8 to control the frequency converting part so that the second clock signal becomes the required frequency on the basis of a compared result by the frequency comparing part are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit (phase synchronizing circuit), and more particularly to extending the lock range of a PLL circuit for generating a system clock used for video digital processing.

[0002]

2. Description of the Related Art In the case of digitally processing a video signal in a television receiver or the like, a system clock signal synchronized with the video signal is required. A PLL circuit has been widely used as a method for generating the system clock signal. It was
FIG. 6 is a basic configuration diagram of a conventional PLL circuit. In the figure, the clock signal CK generated by the voltage controlled oscillator (VCO) 13 is frequency-divided into a required frequency by the frequency divider 14, and this is sent to the phase comparator 11 as a comparison signal. In-phase comparator
A horizontal synchronizing signal S1 as a reference signal is input to 11 and a phase comparison is performed between the horizontal synchronizing signal S1 and the comparison signal. The low-pass filter 12 extracts only the required oscillation frequency control signal from the output of the in-phase comparison section 11, and the oscillation frequency control signal controls the oscillation frequency of the VCO 13. As a result, the clock signal CK output from the VCO 13 is synchronized with the input horizontal synchronizing signal S1.

[0003]

Problem to be Solved by the Invention P in FIG.
In the case of the LL circuit, its lock range is determined by the performance of the VCO 13, and it is generally difficult to pull in a frequency that exceeds the frequency variable width of the VCO 13. As a method of expanding the lock range of the PLL circuit, for example, setting the VCO to L
Although there is a method of using (inductance) and C (capacitor), this method lacks frequency stability as the variable range increases, and is not suitable for digital systems that require high accuracy. On the other hand, in today's diversified video sources, it is desired that the video device can support video signals of various horizontal frequencies, and for that purpose, the wide range of the PLL circuit is required. The present invention has been made in view of such a background, and since it enables digital processing of various video signals having different horizontal frequencies and the like, a PLL circuit for generating a system clock having a wide lock range and high stability. The purpose is to provide.

[0004]

According to the present invention, there is provided a voltage controlled oscillator circuit for generating a first clock signal having a required frequency, and a second clock signal having a required frequency for converting the frequency of the first clock signal. , A frequency converter for dividing the second clock signal into a required frequency, a phase of the clock signal from the frequency divider, and a horizontal synchronizing signal as a reference signal. A comparison unit, a low-pass filter for extracting an oscillation frequency control signal from the phase comparison output from the phase comparison unit, and applying the same oscillation frequency control signal to the voltage controlled oscillation circuit, the horizontal synchronization signal, and the second clock signal. And a frequency comparison unit that outputs a signal based on the comparison, and based on the comparison result by the frequency comparison unit, the second clock signal is adjusted to have a required frequency. There is provided a PLL circuit formed by providing a control unit for controlling the frequency converter.

[0005]

The system clock signal currently being generated in the PLL loop is sent to a frequency divider and divided into a required frequency as a comparison signal.
While being used for phase comparison with the horizontal synchronizing signal which is the reference signal, it is also sent to the frequency comparing section. Further, the horizontal synchronizing signal is also input to the frequency comparing unit. The frequency comparison unit generates a frequency comparison signal based on the input system clock signal, compares the frequency comparison signal with the horizontal synchronization signal, and sends a signal according to the frequency difference between the two to the control unit. According to this frequency comparison, when the frequency of the horizontal synchronizing signal is outside the frequency variable range of the VCO, the center frequency of the VCO is changed by changing the multiplication ratio or the frequency division ratio in the frequency conversion unit via the control unit, and the horizontal synchronization is performed. The signal frequency is controlled to fall within the variable range of the VCO.

On the other hand, when the horizontal synchronizing signal is discontinuous, a dummy synchronizing signal is added to the horizontal synchronizing signal or the frequency divider (loop counter) is reset to input the phase difference of the phase comparator. To be kept to a minimum. This dummy sync signal addition or frequency divider reset is controlled based on the detection because the frequency comparator detects the continuity of the horizontal sync signal during the phase comparison.
Furthermore, when the dummy synchronization signal is added a predetermined number of times in succession, it is determined that the run is free-running, and the frequency comparison unit stops the output of the phase comparator to minimize the frequency deviation.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A PLL circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an essential part showing an embodiment of a PLL circuit according to the present invention, FIG. 2 is a block diagram of an essential part showing an embodiment of a frequency comparison part in FIG. 1, and FIG. 3 is a frequency comparison of the frequency comparison part. FIG. 4 is an essential part block diagram showing one embodiment of the multiplication / frequency division unit, and FIG. 5 is an essential part block diagram showing one embodiment of the low-pass filter of FIG.

In FIG. 1, S1 is a horizontal sync signal as a reference signal, 1 is a sync signal correction unit for adding a dummy sync signal when the continuity of the horizontal sync signal S1 is broken, and 2 is a sync signal correction unit 1. The phase comparison unit 3 that performs phase comparison between the reference signal and the comparison signal S2 that have passed through 3 is a low-pass filter (LPF) that extracts the oscillation frequency control signal S3 from the phase comparison output.
Is a voltage controlled oscillator (VCO) that is controlled by an oscillation frequency control signal S3 from the LPF3 to generate a clock signal (first clock signal) of a required frequency, and 5 is to multiply or divide the clock signal from the VCO4 as necessary. A frequency conversion unit that divides and outputs a system clock signal CK (second clock signal) of a required frequency, a frequency divider 6 divides the second clock signal into a required frequency, and is used for phase comparison by the phase comparison unit 2. A frequency divider for outputting the signal S2, 7 performs frequency comparison as to whether the frequency of the horizontal synchronizing signal S1 is within the frequency variable range of the second clock signal CK, and outputs a signal S4 based on the comparison. , Output of the sync signal addition control signal S5 for adding the dummy sync signal in the sync signal correction unit 1, and the frequency divider 6
Of the reset signal S6 for resetting the output of the phase comparison unit 2 and the output of the output stop control signal S7 for stopping the output of the phase comparison unit 2, and 8 is a frequency conversion unit based on the frequency comparison by the frequency comparison unit 7. 5 is a control unit for setting a multiplication ratio or a frequency division ratio.

Next, the operation of the present invention will be described. As shown in FIG. 1, in the present invention, a clock signal generation block is composed of a VCO 4 and a frequency conversion unit 5, and
Generate a clock signal (first clock signal) at 4,
The same clock signal is multiplied or divided as necessary to obtain a required system clock signal CK (second clock signal).
The system clock signal CK is sent to the frequency divider 6 and the frequency comparison unit 7. The frequency divider 6 divides the system clock signal CK by a predetermined frequency division ratio (1 / K) and outputs the comparison signal to the phase comparison unit 2.
Send as S2. A loop counter may be used as the frequency divider 6.

If the horizontal synchronizing signal S1 is normal without discontinuity, the signal S1 is input to the phase comparing unit 2 without being corrected by the synchronizing signal correcting unit 1. The phase comparison unit 2 compares the phase of the horizontal synchronization signal S1 with the comparison signal S2 using the horizontal synchronization signal S1 as a reference signal, and outputs the phase difference. The LPF3 extracts a signal (oscillation frequency control signal S3) necessary for oscillation control from the output of the phase comparison unit 2 and outputs it to the VCO4.
And the oscillation frequency of the VCO 4 is controlled by the control signal S3. The frequency divider 6, the phase comparison unit 2, and the LP described above
The operations of F3 and VCO4 are basically the same as those of the conventional PLL circuit. The present invention further includes the VCO as described above.
The frequency conversion unit 5 is provided in the subsequent stage of 4. FIG. 2 shows a specific configuration example of the frequency comparison unit 7, which is another destination of the system clock signal CK. The signal input / output of FIG. 2 is associated with FIG. As shown in FIG. 2, the frequency comparison unit 7
Is the first counter 7a, the logic section 7b, the second counter 7
c and the OR gate 7d are connected as shown.

The frequency comparing section 7 has the following three purposes. (1) V that is generating the current system clock signal CK
A frequency comparison is made as to whether or not the frequency of the horizontal synchronizing signal S1 is included in the frequency variable range of CO4, and a signal S4 based on the comparison is sent to the control unit 8. (2) Additional control of the dummy synchronization signal (synchronization signal correction unit 1) when the continuity of the horizontal synchronization signal S1 is lost, or the frequency divider 6
Reset. (3) Output stop control of the phase comparator 2 when the dummy synchronization signal is added a predetermined number of times. The first frequency comparison is performed as follows. NT as an example
Citing the SC method. In this case, the frequency of the horizontal sync signal S1
fh = 15.734KHz, 1H (1 horizontal period) number of samples = 91
It is 0. This is shown in FIG. 3 (A). The number of samples "910" is 4 with color subcarrier frequency fc = 3.58 MHz.
Since the sampling frequency is doubled (4fc = 14.318 MHz), it is determined from the same sampling frequency.

In the case of the above example, when the VCO 4 has a center frequency of 14.318 MHz and the frequency variable range is ± 0.2% and the frequency division ratio is 910, the first counter 7a is set to "3" as shown in FIG. 909 ", then the second counter
Make 7c count "3". Second counter 7c
Is counted as "3", it can be obtained from the following. Number of samples for 1H x VCO variable rate = 910 x (± 0.2
%) = ± 1.8 dots The width of ± 1.8 dots in the above formula is 3.6 dots, but the count is set to 3 counts (synchronization width ± 1 dot) (frequency comparison becomes impossible at 4 counts). This range of 3 counts (count area C2) is the frequency variable range of the VCO 4 in the frequency comparison, and when the horizontal synchronizing signal S1 is at the center, it indicates that the oscillation frequency of the VCO 4 is at the center of the variable range. From now on, the first counter 7a will count 909 (count area C
1) will be done [Fig.3 (A) (B)]. The signal thus generated becomes the frequency comparison signal S13 [Fig.
(B)].

In other words, the period of the count area C2 corresponds to the expected generation period of the input horizontal synchronizing signal S1, and when the horizontal synchronizing signal S1 is input within this period (symbol A), V
Since it is within the variable range of CO4, the PLL locks. On the other hand, judging from the current oscillation state, if the next horizontal sync signal is generated at the count area C1 (code B), the sync signal is early, and if it is count area C3 (code C), it is the same or slow. it can. Counting area
If it is C2 (sign a), it is judged to be the same. This is frequency comparison, and the signal S4 based on the comparison is sent to the control unit 8.

In counting by each of the above counters,
The first counter always starts counting from the starting point of the horizontal synchronizing signal S1, and after counting 909, starts counting by the second counting. The logic unit 7b controls both counters in this way. The logic unit 7b causes the first counter 7a to start counting the system clock signal CK input to the counter 7a based on the input horizontal synchronization signal S1 (LOAD). The counter 7a sends the count data S11 to the logic section 7b after a predetermined count (the 909 count). The logic unit 7b, which has received the count data S11 from the first counter 7a, moves to the second counter
For 7c, the count of the system clock signal CK which is similarly input is started (LOAD). The counter 7c sends count data S12 to the logic unit 7b after a predetermined count (3 counts). The logic unit 7b outputs to the control unit 8 a signal S4 corresponding to whether the current oscillation frequency is higher, normal, or lower than the horizontal synchronizing signal S1 based on the count results by the first counter 7a and the second counter 7c.

The control unit 8 is a signal indicating whether or not the current oscillation frequency is appropriate.
Based on S4, with respect to the horizontal synchronization signal S1, the multiplication ratio or frequency division ratio of the frequency conversion unit 5 is controlled so as to increase it if the current oscillation frequency is low, and conversely decrease it if it is high, and always The horizontal synchronizing signal S1 is made to appear in the count area C2. As a result, the PLL can always maintain the locked state. The frequency of the system clock CK after this multiplication or division control can be expressed as follows. System clock CK frequency = VCO4 center frequency x
(M / N) Here, M and N are the multiplication ratio (multiplier 5a) and the frequency division ratio (frequency divider 5b) of the frequency converter 5 shown in FIG. The above is frequency comparison.

Next, the second purpose of the frequency comparison unit 7 is to correct the discontinuity of the horizontal synchronizing signal as follows. When the continuity of the input horizontal synchronizing signal S1 is broken from the normal state, the input synchronizing signal appears in the count area C1 or C3 of FIG. In this case, count area C1 or the same
Whether the one appearing in C3 is due to the above-mentioned frequency comparison or due to discontinuity is determined by the first counter 7a or the second counter.
It is distinguished from the fact that the count of 7c is non-genuine and differs from the original count. When the sync signal indicating this discontinuity appears in the count area C1, the frequency divider 6 (loop counter) is reset, and when the sync signal does not appear by the count area C2 in the process of frequency comparison (count area C1).
The sync signal addition control signal S5 is output, and the dummy signal is added to the input sync signal S1 immediately after the count area C2 ends in the sync signal correction unit 1.

The frequency divider 6 is reset by the logical sum output S6 of the OR gate 7d of the frequency comparison signal S13 and the input horizontal synchronizing signal S1. For example, the OR gate 7d outputs H (high) when the synchronization signal position is the "a" position in FIG. 3, but outputs L (low) at the "b" position. At the time of this L output, the frequency divider 6 is reset. If the dummy sync signal is added a predetermined number of times (for example, three times) in succession, the logic unit 7b treats it as a free run (there is no input sync signal S1) and compares the phases by the output stop signal S7. The output of the section 2 is controlled to be stopped. This reduces the deviation of the oscillation frequency of the VCO 4. The control of the phase comparison unit 2 is the third purpose of the frequency comparison unit 7. The above is the description of the frequency comparison unit 7.

Next, the LPF 3 will be described. The present invention is intended to widen the lock range of the PLL circuit. Therefore, fixing the LPF 3 to one transfer characteristic may cause a problem in stability and the like. Therefore, LPF
As shown in FIG. 5, reference numeral 3 is composed of plural kinds having different transfer characteristics and a switching circuit for switching these. FIG. 5 shows an example in which three types of LPF are used, 3a, 3b, and 3c.
3a has a fast transfer characteristic, 3c has a slow transfer characteristic, and 3b has an intermediate transfer characteristic. Further, 3d is a switching circuit. These LPFs are assigned to the frequency band of the system clock in advance, and when the frequency band is high, L having a fast transfer characteristic is used.
When PF3a is selected and the same or low, LP with slow transfer characteristics
Select F3c, etc.

The selection of these LPFs is not limited to the frequency band of the system clock, but the frequency conversion unit 5
The LPF may be switched also when the ratio is switched. In this case, when switching the ratio, the LPF 3a having a fast transfer characteristic is selected, and when the control is transferred to the phase comparison unit 2, the LPF 3c having a slow transfer characteristic is selected. LP
The selection switching of F may be performed by the control unit 8 based on the comparison result by the frequency comparison unit 7. Further, manual switching is also possible as long as switching is performed only according to the frequency band of the system clock. By doing so, the stability of the PLL circuit is ensured.

[0020]

As described above, according to the present invention, V
PL without increasing the number of CO (voltage controlled oscillation circuit)
It is possible to extend the lock range of the L circuit, which makes it possible to support many kinds of dot clocks. Further, when the input horizontal synchronizing signal is discontinuous, the frequency divider (loop counter) is reset or a dummy synchronizing signal is added according to the discontinuous state, and further, the dummy synchronizing signal addition is predetermined. When the number of times occurs, it is treated as a free run, and the output of the phase comparator is stopped to minimize the phase comparison difference. As a result, the operation of the PLL circuit can be made stable. From the above,
The present invention can contribute to improving the performance of a PLL circuit that generates a system clock used for digital video processing.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts showing an embodiment of a PLL circuit according to the present invention.

2 is a principal block diagram showing an embodiment of a frequency comparison unit in FIG. 1. FIG.

FIG. 3 is an explanatory diagram of frequency comparison in a frequency comparison unit.

FIG. 4 is a principal block diagram showing an embodiment of a frequency conversion unit.

FIG. 5 is a block diagram of a main part showing an embodiment of a low-pass filter.

FIG. 6 is a principal block diagram showing an embodiment of a conventional PLL circuit.

[Explanation of symbols]

 S1 Horizontal sync signal 1 Sync signal corrector 2 Phase comparator 3 Low pass filter (LPF) 4 Voltage controlled oscillator (VCO) 5 Frequency converter 6 Frequency divider 7 Frequency comparator 8 Controller CK System clock 7a First counter 7b Logic part 7c Second counter 7d OR gate 3a First low-pass filter (LPF) 3b Second low-pass filter (LPF) 3c Third low-pass filter (LPF) 3d Switching circuit

Claims (8)

[Claims] 1. A voltage controlled oscillator circuit for generating a first clock signal of a required frequency, and a frequency conversion unit for converting the frequency of the first clock signal and outputting it as a second clock signal of the required frequency. A frequency divider that divides the second clock signal to a required frequency, a phase comparison unit that makes a phase comparison between the clock signal from the frequency divider and a horizontal synchronization signal as a reference signal, and the phase comparison unit. From the phase comparison output, and compares the low-pass filter for applying the oscillation frequency control signal to the voltage controlled oscillation circuit with the horizontal synchronization signal and the second clock signal. A frequency comparison unit that outputs a signal based on the frequency, and a control unit that controls the frequency conversion unit so that the second clock signal has a required frequency based on the comparison result by the frequency comparison unit. A PLL circuit comprising a control section. 2. The frequency comparing unit counts the second clock signal with the horizontal synchronizing signal as a reference, and outputs a count data after a predetermined number of counts, and outputs the count data. A second counter that starts counting the second clock signal after a predetermined number of counts and outputs count data after a predetermined number of counts, and a first counter that performs the counting based on the horizontal synchronization signal. While controlling the second counter, the count data from the first counter and the second counter
A frequency comparison signal is generated from the count data from the counter, the frequency comparison signal is compared with the horizontal synchronization signal, and a logic unit that outputs a signal according to the frequency difference between the two is formed. The PLL circuit according to claim 1, which is characterized in that. 3. The frequency comparing unit calculates a logical sum of the frequency comparison signal and the horizontal synchronizing signal, and resets the frequency divider when the horizontal synchronizing signal has a predetermined frequency higher than the frequency comparing signal. The PLL circuit according to claim 1 or 2, further comprising an arithmetic circuit that outputs a reset signal. 4. The PLL circuit according to claim 1, wherein the arithmetic circuit is composed of an OR gate. 5. In the comparison in the frequency comparison unit, when the horizontal synchronization signal is lower than the frequency comparison signal by a predetermined frequency, the logic unit outputs the synchronization signal addition control signal from the second counter and the synchronization signal addition is performed. A control signal is input, and when there is the same input, a sync signal correction unit that adds a dummy sync signal to a predetermined position of the horizontal sync signal is provided, and the horizontal sync signal after the addition is input to the phase comparison unit. The PLL circuit according to claim 1 or 2, wherein the PLL circuit is provided. 6. The logic unit outputs the output stop signal for stopping the output of the phase comparison unit when the addition of the dummy synchronization signal continues for a predetermined number of times. 2 or the PLL according to claim 5.
circuit. 7. The low-pass filter comprises a plurality of low-pass filters each having a different transfer characteristic, and a switching circuit for switching the plurality of low-pass filters, and the control unit is configured to operate in accordance with the frequency of the second clock signal. The PLL according to claim 1, wherein the switching circuit is switched.
circuit. 8. The PLL circuit according to claim 1, wherein the frequency conversion unit is composed of a series circuit of a variable multiplication circuit and a variable frequency dividing circuit.