JP2002043929A - Variable frequency divider circuit, and clock frequency division method using the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable frequency divider circuit that is synchronized with an input reference clock and provides frequency division clocks with a different frequency division ratio and to provide a clock frequency division method using the circuit. SOLUTION: The variable frequency divider circuit comprises frequency divider circuit sections 12, 14 with a different frequency division ratio that receive input reference clocks, a selection section 16 that selects and outputs a frequency division clock from the frequency divider circuit sections 12, 14, and a control section 22 that monitors the frequency division clock of the frequency divider circuit sections 12, 14 to control the selection of the selection section 16 on the basis of it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency divider, and more particularly to a variable frequency divider for generating an output clock in which a reference input clock is continuously varied at a plurality of frequency division ratios, and a clock frequency dividing method using the same. .

[0002]

2. Description of the Related Art A frequency dividing circuit or a PLL (Phase Locked Loop) circuit using the same is widely used in a local oscillation circuit of a heterodyne radio receiver. The prior art of such a frequency dividing circuit is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-52516, "Division Circuit and PLL Circuit Using It", Japanese Patent Application Laid-Open No. 5-63565, "Frequency Synthesizer" and Japanese Patent Application Laid-Open No. This is disclosed in, for example, “Circuit Device for Correcting Phase in Output Signal Group of Frequency Divider” in 95058.

FIG. 6 shows an example of a conventional general frequency dividing circuit or frequency synthesizer. This circuit includes an L divider 1, a PLL circuit 2, a VCO to which an input (reference) clock is input.
(Voltage Controlled Oscillator) 3, M frequency divider 4 and N frequency divider 5. The outputs of the L frequency divider 1 and the M frequency divider 4 are P
The signal is input to the LL circuit 2 and the phases are compared. This PLL circuit 2
Is input to the VCO 3 to control its oscillation frequency. Further, the output of the VCO 3 is input to the M frequency divider 4 and the N frequency divider 5. The output clock is obtained from the N frequency divider 5.

Next, the operation of the circuit shown in FIG. 6 will be described. A clock having a frequency of fc / L obtained by dividing an input clock (frequency is fc) by an L frequency divider 1 and an oscillation frequency of the VCO 3 (this frequency is represented by fc) are frequency-divided by an M frequency divider 4. The phase of fv / M is compared by the PLL circuit 2. This P
Generally, the pulse output from the LL circuit 2 is obtained through a low-pass filter (not shown) to obtain a DC control voltage to control the oscillation frequency of the VCO 3.

Therefore, the control loop including the PLL circuit 2 operates so that the relationship of fc / L = fv / M is established. As a result, the output frequency fv of the VCO 3 becomes fv =
(M / L) xfc. Output clock frequency f0
Since the oscillation output fv of the VCO 3 is further divided by N by the N divider 5, f0 = (M / NL) × fc. As a result, the output clock frequency f0 has a fixed relation to the input clock frequency fc, that is, M / NL times. Therefore, the division ratios L, M, and N of the frequency dividers 1, 4, and 5 are appropriately selected. By doing so, it is possible to make any non-integer relationship.

[0006]

The problem of the prior art is that when a low-frequency clock synchronized with a reference clock is generated, the low-frequency clock frequency to be generated when the clock is generated by a frequency divider is: 1 / n of the reference clock frequency
(N is an integer). The reason is that when the low frequency clock frequency to be generated is 1 / n of the reference clock frequency, it is possible to generate the reference clock by an integer frequency division.

However, if n is not an integer, a VCO frequency is selected so that the frequency can be divided by an integer. Then, a PLL circuit is used to synchronize this expensive VCO with a reference clock. As a result, VC
It was necessary to divide the clock output from O by m (m is an integer).

[0008]

OBJECTS OF THE INVENTION Accordingly, an object of the present invention is to provide an expensive VCO
A simple and inexpensive frequency dividing circuit and a clock frequency dividing method using the same can be provided by making it possible to generate a low-frequency clock synchronized with a reference clock without using the same.

[0009]

A variable frequency dividing circuit according to the present invention is a frequency dividing circuit which synchronizes with an input reference clock and generates a frequency dividing clock having an arbitrary frequency dividing ratio selected in advance.
A plurality of frequency dividers having different frequency division ratios to which an input reference clock is input, a selector for selecting a frequency-divided clock from the plurality of frequency dividers, and a frequency-divided clock of the plurality of frequency dividers. And a control unit that monitors and controls the reset operation of the plurality of frequency division circuit units and the selection operation of the selection unit. According to a preferred embodiment of the present invention, the control unit includes a counter for counting the frequency-divided clock from each frequency dividing circuit unit, and a comparator for comparing the count value of the counter with a set value. The set value of each comparator can be arbitrarily changed. The control unit is
A latch circuit that receives an output of the comparator as an input;

Here, the control section comprises a counter for counting the frequency-divided clock from each of the frequency-dividing circuit sections, and a comparator for comparing the count value of the counter with a set value. Further, the set value of each of the comparators can be changed to an arbitrary value, and the selection unit includes a latch circuit that receives an output of the comparator as an input.

The clock dividing method according to the present invention is a clock dividing method for synchronizing with an input reference clock and generating a divided clock having an arbitrary dividing ratio, which is predetermined by a first dividing circuit unit. A predetermined number of first frequency-divided clocks obtained by dividing the input reference clock at the first frequency division ratio are output as output clocks, and input at a different second frequency division ratio predetermined by the second frequency dividing circuit unit. The second obtained by dividing the reference clock
A predetermined number of frequency-divided clocks are output as output clocks, and frequency-divided clocks of a predetermined frequency and a predetermined number are sequentially output by frequency division circuits below the third frequency division circuit. The step of returning to the frequency dividing operation of the frequency dividing circuit is repeated. According to the preferred embodiment, one or both of the frequency division ratio and the number of output clocks of each frequency dividing circuit unit can be changed.

Here, one or both of the frequency division ratio and the number of output clocks of each frequency dividing circuit section can be changed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure and operation of a preferred embodiment of a variable frequency dividing circuit according to the present invention and a clock frequency dividing method using the same will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the basic principle of the variable frequency dividing circuit according to the present invention. This variable frequency dividing circuit includes a frequency dividing circuit section 10 and a frequency division ratio control section 20. The frequency dividing circuit section 10 receives an input (reference) clock and an output of the frequency division ratio control section 20, and outputs an output clock. The output clock of the frequency dividing circuit unit 10 is input to the frequency dividing ratio control unit 20. According to this variable frequency dividing circuit, the frequency dividing circuit section 10 includes a frequency dividing ratio control section 20 controlled by its output.
The input clock is frequency-divided by the frequency division ratio (N) determined by the output of (1), and is output as an output clock.

FIG. 2 is a block diagram showing a preferred embodiment of the variable frequency dividing circuit according to the present invention based on the basic principle shown in FIG. The variable frequency divider includes a first frequency divider (or frequency divider 1) 12, an i-th frequency divider (or frequency divider i).
14, selection unit 16 and monitoring control unit (or control unit) 22
It is composed of An input (reference) clock is commonly input to the two frequency divider circuits 12 and 14. The outputs of the two frequency dividers 12 and 14 are input to the selector 16 and also to the monitor controller 22. The monitoring control unit 22 transmits the first reset signal (reset signal 1) and the i-th reset signal (reset signal i) to the first frequency dividing circuit unit 1 respectively.
2 and the i-th frequency divider 14. The monitoring control unit 22 outputs a selection signal to the selection unit 16 and obtains an output clock from the selection unit 16.

Therefore, in the preferred embodiment of the variable frequency dividing circuit according to the present invention shown in FIG. 2, one input (reference) clock is inputted to a plurality of frequency dividing circuit sections 12 and 14 having different frequency dividing ratios, respectively. Generates divided clocks having different division ratios. Then, the output frequency-divided clocks from the frequency-dividing circuit units 12 and 14 are input to the monitoring control unit 22 and the selecting unit 16. The monitoring control unit 22 counts (counts) each of the input divided clocks and compares the counted clock with a preset count value. The frequency dividers 12 and 14 are reset (restarted) based on the reset signal 1 and the reset signal i, and control the selection of the frequency-divided clock to the selector 16 by the selection signal. It is.

Next, the operation of the variable frequency dividing circuit shown in FIG.
This will be described with reference to the flowchart shown in FIG. When the circuit operation starts, the first frequency dividing circuit section (frequency dividing circuit 1) 12 starts (step S1 in FIG. 4), and the selecting section 16 outputs the first frequency dividing signal from the first frequency dividing circuit section 12 as an output clock. The peripheral clock is selected (step S2). The output of the first frequency dividing circuit unit 12 is input to a first counter (or counter 1) (not shown) constituting the first frequency dividing circuit unit 12 (step S3), and the counter 1 is incremented or counted up. (Step S4). The count value of the counter 1 is compared with the first set value (set value 1) set in the counter 1 to determine whether or not (counter 1 value = set value 1) (step S5).

If the comparison results are not equal (step S5: No), the flow returns to step S3 again, and
Until they match, the first frequency dividing circuit section (frequency dividing circuit 1) 12 continues to operate, and the frequency-divided clock 1 is output as the output clock.

When the comparison results match (step S5: Yes), the frequency divider 2 operates (step S1).
1) The selecting unit 16 selects the frequency dividing circuit 2 (Step S)
12), and outputs the divided clock 2 as an output clock (step S13). Then, the counter 2 of the frequency dividing circuit 2 counts up or increments (step S14). Next, it is determined whether the count value of the counter 2 matches the set value 2 of the counter 2 (counter 2 value = set value 2) (step S15). If they do not match (step S
(15: NO), the process returns to step S13 until the values match, and steps S13 to S15 are repeated. During that time, the frequency dividing circuit 2 continues to operate, and the frequency-divided clock 2 becomes the output clock.

Thereafter, the same operation is performed to sequentially select frequency-dividing circuit sections having different frequency-dividing ratios, and respective frequency-divided clocks are output as output clocks. Finally, steps S21 to S25 are executed by the i-th frequency dividing circuit 14 in the same manner as described above, and the frequency-divided clock i from the i-th frequency dividing circuit 14 becomes the output clock. Here, if the value of the counter i matches the set value i (step S25: Yes), the process returns to step S1 and repeats the above-described operation.

Next, FIG. 3 is a specific configuration diagram of the variable frequency dividing circuit according to the present invention shown in FIG. In this variable frequency dividing circuit, an n frequency dividing circuit section (n frequency divider) 30, a first counter (counter 1) 32, a first comparator (comparator 1) 34,
m frequency dividing circuit section (m frequency divider) 40, second counter (counter 2) 42, second comparator (comparator 2) 44, latch circuit (RS latch) 50, inverter 52, and selecting section (S
EL) 60.

N frequency dividing circuit section 30 and m frequency dividing circuit section 40
Is supplied with an input (reference) clock. The n-divided clock and the m-divided clock of the n-divided circuit section 30 and the m-divided circuit section 40 are inputted to the first counter 32 and the second counter 42 and also inputted to the selecting section 60, respectively. First counter 32 and second counter 4
2 are input to the first comparator 34 and the second comparator 44, respectively. A first set value (or set value 1) and a second set value (or set value 2) are also input to the first comparator 34 and the second comparator 44, respectively.

The first counter expiration pulse (or counter expiration pulse 1) output from the first comparator 34 is input to the latch circuit 50 and the m frequency dividing circuit section 40. The second counter expiration pulse (or counter expiration pulse 2) output from the second comparator 44 is supplied to the latch circuits 50 and n
The signal is input to the frequency divider 30. The selection control signal output from the latch circuit 50 is input to the selection unit 60,
The selection control operation of the selection unit 60 is performed, and the first counter 32 is directly controlled, and the second counter 42 is controlled by the inverter 5.
2, and the signal is input as the above-described reset signal.

Next, the operation of the variable frequency dividing circuit according to the present invention shown in FIG. 3 will be described with reference to a timing chart shown in FIG. Here, the division ratio n of the n division circuit unit 30 is set to n = 2, and the division ratio m of the m division circuit unit 40 is set to m = 3, and the first setting input to the first comparator 34 and the second comparator 44 is performed. Value (set value 1) and second set value (set value 2)
The case where the setting value 2 = 3 will be described. Note that the frequency division ratios n and m and the values of the set value 1 and the set value 2 can be arbitrarily changed according to the specific application.

In the timing chart shown in FIG.
(A) is an input clock input to the n and m frequency dividing circuit units 30 and 40. (B) is a frequency-divided-n clock output from the frequency-divided-n circuit section 30. (C) is an m-divided clock output from the m-divider circuit unit 40.
(D) is the counter expiration pulse 1 output from the first comparator (comparator 1) 34. (E) is a counter expiration pulse 2 output from the second comparator (comparator 2) 44.
It is. (F) is a selection control signal output from the latch circuit 50 to the selection unit 60, the first counter 32, and the inverter 52. (G) is an output clock output from the selection unit 60.

As apparent from FIGS. 5 (a), 5 (b) and 5 (c), when n = 2 and m = 3, the n-divided clock (see FIG. 5 (b)) is the input clock. (See FIG. 5 (a).) Each time two rising edges are counted, it is inverted to become a clock having a quarter frequency of the input clock.
The frequency-divided clock (see (c) of FIG. 5) is inverted every time three rising edges are counted, and becomes a clock having a frequency of 1/6 of the input clock. When setting value 1 = setting value 2 = 3 as described above, the n-divided clock (see FIG. 5 (b)) and the m-divided clock (see FIG. 5 (c)) become three clocks each. Each time, the selection control signal of the latch circuit 50 (see (f) of FIG. 5) is inverted,
An output clock that alternately switches the n-divided clock and the m-divided clock every three clocks (see FIG. 5 (g))
Output as

The configuration and operation of the preferred embodiment of the variable frequency dividing circuit and the clock frequency dividing method using the same according to the present invention have been described in detail. However, it should be understood that such embodiments are merely examples of the present invention and do not limit the present invention in any way. It will be readily apparent to those skilled in the art that various modifications can be made in accordance with the particular application without departing from the spirit of the invention.

[0028]

As will be understood from the above description, according to the variable frequency dividing circuit of the present invention and the clock frequency dividing method using the same, the following remarkable practical effects can be obtained. First, a variable frequency dividing circuit can be obtained at low cost. The reason is that it is not necessary to use an expensive VCO or the like. Second, the configuration of the variable frequency dividing circuit is simple. The reason is that since a VCO or the like is not required, the VCO and peripheral components are not required, and the number of components can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a basic principle of a variable frequency dividing circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a preferred embodiment of a variable frequency dividing circuit according to the present invention.

FIG. 3 is a specific circuit configuration example of the variable frequency dividing circuit shown in FIG. 2;

FIG. 4 is a flowchart for explaining the operation of the variable frequency dividing circuit of the present invention shown in FIG. 2;

FIG. 5 is a timing chart showing an operation of the variable frequency dividing circuit according to the present invention shown in FIG. 3;

FIG. 6 is a block diagram showing a configuration of a conventional example of a variable frequency dividing circuit.

[Explanation of symbols]

 10, 12, 14, 30, 40 Dividing circuit section 16, 60 Selecting section 20, 22 Dividing ratio control section (control section) 32, 42 Counter 34, 44 Comparator 50 Latch circuit 52 Inverter

Claims (6)

[Claims] 1. A variable frequency dividing circuit which synchronizes with an input reference clock and generates a divided clock having an arbitrary dividing ratio selected in advance, comprising: A circuit unit, a selecting unit that selects a divided clock from the plurality of divided circuit units, monitors the divided clocks of the plurality of divided circuit units, resets the plurality of divided circuit units, and A variable frequency dividing circuit comprising: a control unit that controls a selecting operation of the selecting unit. 2. The apparatus according to claim 1, wherein the control section includes a counter for counting the frequency-divided clock from each of the frequency-dividing circuit sections, and a comparator for comparing the count value of the counter with a set value. The variable frequency dividing circuit according to claim 1. 3. The variable frequency divider according to claim 2, wherein the set value of each of the comparators can be changed to an arbitrary value. 4. The variable frequency dividing circuit according to claim 2, wherein said selecting section includes a latch circuit which receives an output of said comparator as an input. 5. A clock dividing method for synchronizing with an input reference clock and generating a divided clock having an arbitrary dividing ratio, wherein said input reference clock is generated at a first dividing ratio predetermined by a first dividing circuit unit. A predetermined number is output as a first frequency-divided clock obtained by dividing the input reference clock, and a second frequency obtained by dividing the input reference clock at a different second frequency-division ratio predetermined by a second frequency dividing circuit unit. A predetermined number of frequency-divided clocks are output as the output clocks, and the frequency-divided clocks of a predetermined frequency-division ratio and a predetermined number are sequentially output by the remaining frequency dividers below the third frequency divider. A clock frequency dividing method comprising repeating a step of returning to a frequency dividing operation of a frequency dividing circuit unit. 6. The clock frequency dividing method according to claim 5, wherein one or both of the frequency dividing ratio and the number of output clocks of each frequency dividing circuit section can be changed.