JP3034388B2 - Phase locked oscillator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked oscillator used in a clock section of a transmission apparatus.

[0002]

2. Description of the Related Art In a transmission system, a network synchronization system is generally employed in which all stations in the system are operated by the same clock. A subordinate station transmits a clock component from a signal transmitted from a higher-level station via a transmission line. Is extracted, and a clock synchronized with this is generated to operate each device in the own station. A phase-locked oscillator is used to generate this clock.

FIG. 2 is a block diagram showing an example of a conventional phase locked oscillator. This phase-locked oscillator generates a feedback clock by dividing the output of a voltage controlled oscillator 3 by a feedback frequency divider 4, and outputs an external input clock (a clock extracted from a transmitted signal) by a phase comparator 1. ) And the phase difference between the feedback clock and the detected voltage are fed back to the voltage controlled oscillator 3 via the low-pass filter 2, and the oscillation frequency is controlled to synchronize the feedback clock with the input clock and output it. It is output as clock 2. This output clock 2
And various clocks used in the device based on the output of the voltage controlled oscillator 1 (output clock 1).

A window processor 5 shown in FIG. 2 is used to speed up pull-in of a phase-locked oscillator.
That is, when the phase of the input clock jumps and the phase difference between the input clock and the feedback clock exceeds a certain range (window), the feedback frequency divider 4 is reset, and the phase of the feedback clock is changed to the phase of the input clock. Perform the process of forcibly combining quickly. This allows
The phase difference between the feedback clock and the input clock can be made within the window width, and the feedback clock synchronized with the input clock, that is, the output clock 2 can be obtained.

[0005]

However, in the phase-locked oscillator having the above structure, when the phase of the input clock jumps greatly and deviates from the window width, the synchronization is quickly performed by the window processing. That is, there is a problem that a phase jump occurs in the output clock 2 and also a phase jump occurs in various clocks used in a device that is generated based on the output clock, so that data cannot be transmitted properly.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is possible to generate an output clock synchronized with an input clock which does not cause a phase jump even if a phase jump outside the window width occurs in the input clock. An object of the present invention is to provide an excellent phase synchronization generator.

[0007]

According to the present invention, to achieve the above object, a first output clock output from a voltage controlled oscillator is divided by a feedback frequency divider to detect a phase difference from an input clock. A phase-locked oscillator that controls the oscillation frequency of the voltage-controlled oscillator so that the phase difference becomes zero, and resets the feedback frequency divider by a window processor when the phase of the input clock jumps over a certain value. An output frequency divider for outputting a second output clock obtained by dividing the first output clock output from the voltage controlled oscillator to the frequency of the input clock and not resetting by the window processor; It is.

[0008]

Since the voltage controlled oscillator is not affected by the reset of the feedback divider, the output of the voltage controlled oscillator is divided by the output divider to be affected by the reset by the window processor. No, a clock synchronized with the input clock can be generated.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, an output frequency divider 6 having the same function as the feedback frequency divider 4 is provided on the output side of the voltage controlled oscillator 3 of the conventional phase locked oscillator shown in FIG. The configuration is such that the output clock 2 is output.

Next, the operation of this embodiment will be described with reference to FIG. First, when no phase jump occurs in the input clock, the phase-locked oscillator controls the oscillation frequency of the voltage-controlled oscillator 3 so that the phase of the feedback clock matches the phase of the input clock, as described with reference to FIG. Since the output frequency divider 6 has the same function as the feedback frequency divider 4, the output frequency divider 6 outputs an output clock 2 similar to the feedback clock. That is, an output clock 2 synchronized with the input clock is obtained.

Next, the operation when a jump occurs in the phase of the input clock will be described. Note that such a phase jump may occur, for example, when a higher-level station switches devices. When the phase of the input clock jumps and the phase difference between the input clock and the feedback clock deviates from the window width, the window processor 5 detects this and resets the feedback frequency divider 4. Due to this reset, the feedback clock output from the feedback frequency divider 4 causes a phase jump, and quickly follows the phase jump of the input clock. That is, quick synchronization is performed, and phase synchronization between the input clock and the feedback clock is maintained.

As described above, since the input clock and the feedback clock which are inputted to the phase comparator 1 and compared in phase are maintained in the same phase before and after the window processing, the phase-locked oscillator is not affected by the window processing. The constant feedback operation is continued, and the voltage controlled oscillator 3 continues to oscillate at a constant frequency. Therefore, if the output of the voltage controlled oscillator 3 is frequency-divided, it is possible to obtain a clock synchronized with the input clock which is not affected by the window processing, that is, the phase does not jump even if the window processing is performed. The output clock 2 output from the output frequency divider 6 shown in FIG. 1 is this output clock.

In this case, the phase of the output clock 2 is shifted from the input clock by the amount of the phase jump generated in the input clock.

[0014]

As described above in detail, according to the present invention, an output frequency divider that does not perform resetting by a window processor is provided on the output side of a voltage controlled oscillator to provide a clock synchronized with an input clock. Since the clock is generated, it is possible to obtain a clock that does not cause a phase jump even when the window processing is performed.

Therefore, the present invention can be applied to a transmission device in which clock phase fluctuation cannot be tolerated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional phase locked oscillator.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 phase comparator 2 low-pass filter 3 voltage-controlled oscillator 4 feedback divider 5 window processor 6 output divider

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 7/00 H04J 3/06

Claims (1)

(57) [Claims] 1. A first output output from a voltage controlled oscillator.
The input clock is divided by the feedback frequency divider to detect a phase difference from the input clock, and the oscillation frequency of the voltage controlled oscillator is controlled so that the phase difference becomes zero. in the phase locked oscillator to reset by window processor the feedback divider when jumping above a certain value, for outputting the second output clock of the first output clock obtained by dividing up the frequency of the input clock And said
A phase-locked oscillator provided with an output frequency divider that is not reset by a window processor .