KR930011482B1 - Phase synchronization loop circuit for digital video optical transmitting apparatus - Google Patents

Abstract

The circuit comprises a loop circuit which generates a comparison frequency signal which has the same frequency as the image line frequency; the phase detector which generates the phase difference signal in response to the signals; the low pass filter (2) which eliminates the harmonic frequency components of the phase detection signal; the voltage controlled oscillator (3) generating the standard frequency signal; the first gate (51) outputting the first state signal which has a defined delay time; and the reset generator including the fourth gate (56,57,58).

Description

Phase-locked Loop Circuits for Stabilization of Synchronization Time in Digital Video Optical Transmission Devices

1 is a block diagram of a conventional phase locked loop circuit.

2 is a block diagram of a phase locked loop circuit according to the present invention.

3 is a diagram illustrating a relationship between a reference frequency and a comparison frequency during synchronization.

4 is a circuit diagram of the reset circuit of the phase-locked loop circuit of FIG. 2 in more detail.

* Explanation of symbols for main parts of the drawings

1: Phase detector 2: Low pass filter

3: voltage controlled oscillator 4: loop circuit

5: reset generator

The present invention relates to the stabilization of the synchronous time of the video signal phase synchronization loop (PLL) of the digital video optical transmission device, and in particular, to reduce the synchronous time of the video signal by reducing the image output delay time generated when the input image is disconnected and input again. It relates to a stabilized PLL circuit.

In general, in a digital transmitter, a PLL circuit for an image signal used for signal synchronization is for generating a sampling signal synchronized with a line synchronization signal, and a sampling frequency having a sampling frequency as shown in FIG. A loop (4) for generating a comparison frequency signal having a variable frequency (Vf) by inputting a signal, and a reference frequency (Rf) signal that is an image line synchronization signal having the comparison signal and an image line frequency; A phase detector 1 for detecting a phase difference between signals, a low pass filter 2 for inputting a signal from the phase detector 1 to output a signal from which high frequency components are removed, and the low pass filter 2 And a voltage controlled oscillator (VCO) 3 for inputting the phase difference signal from to have a reference frequency.

In this case, as is well known to those skilled in the art, the PLL synchronized when the comparison frequency (Vf) signal and the reference frequency (Rf) signal output from the loop circuit 4 are matched in the phase detector 1. Find the clock. However, when the image input signal is switched on / off, the phase does not always coincide, so the difference in time when the comparison frequency (Vf) signal from the loop circuit 4 coincides with the reference frequency (Rf) signal may be different in a few seconds. To this. In addition, when the synchronization maintenance range is wide, the time becomes longer. This delay time has a wide synchronization range, and there is a problem that the transmission apparatus for transmitting a signal has various bad effects.

Accordingly, an object of the present invention is to maximize the PLL synchronization time regardless of the synchronization period of the reference frequency signal of the image signal when switching on / off to stabilize the PLL synchronization time of the image signal that is changed when the image input signal is switched on / off It is to provide a PLL circuit that can be reduced.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a schematic block diagram of a PLL circuit according to the present invention, wherein the PLL circuit has a loop circuit 4, a phase detector 1, a low pass filter 2 and a voltage controlled oscillator 3 as described above. And a first frequency divider circuit (3a) for dividing the sampling frequency signal from the voltage controlled oscillator (3) and supplying it to the loop circuit (4) and a reference frequency in response to a reference frequency (Rf) signal. If the phase of the (Vf) signal is out of phase, it further includes a reset signal generator 5 capable of generating a reset signal without waiting for the next period of the comparison frequency signal. Therefore, the comparison frequency Vf signal can be received again with respect to the reference frequency signal Rf as described above.

Here, for the control of the synchronization range, the signal frequency of the voltage controlled oscillator 3 is 42.923072 MHz, and the frequency is divided by 4 in the first division circuit 3a to obtain a sampling frequency of the video signal, which is 1364 in the loop circuit 4. By dividing, a comparison frequency signal of the same frequency as that of the synchronization signal can be obtained.

Referring to FIG. 4, the reset generator 5 of FIG. 2 inputs the reference frequency signal Rf and outputs a first state signal, i.e., HH, from the falling edge of the reference frequency signal Rf. The first gate means (51) for holding, the second gate means (53) and (54) for synchronizing the reference frequency (Rf) signal synchronized with the transmission clock with the sampling clock, and the first gate means (51). Inputs a signal from the loop circuit 4 and a signal from the loop circuit 4, and outputs a second state signal, i.e., a LV signal, if the phases do not match. A first delay means for inputting signals from the three-gate means 52, the second gate means 53, and 54 to output a second state signal, i.e., the L signal at the falling edge of the reference frequency signal ( 55) a signal from the third gate means 52 and a signal from the first delay means 55 are inputted. The loop circuit 4, i.e., the counter, outputs the? L? Signal only when the signal from the third gate means 52 is the second state signal and the signal from the first delay means is the second state signal. Fourth gate means (56), (57), and (58) for resetting.

Therefore, the output from the NAND gate 58 among the fourth gates maintains the first state signal, i.e., the HH signal and is not synchronized only when the signal of the reference frequency Rf and the comparison frequency signal are synchronized. In this case, the second state signal, i.e., LV signal is output from the falling edge of the reference frequency Rf, and the loop circuit 4 can be reset to force synchronization quickly and forcibly.

The gate 42 or NAND gate, which is not described herein, is for transmitting the output of the counter 41, which is a looping circuit 4, for example, a 1364 frequency division circuit, to the phase comparator 1, and the first gate means described above. The 51, the second gate means 53 and 54, and the third gate means can use commercially available 74LS123 and 74LS74, which are D flip-flops, respectively, and the counter 41 can counter 74SL169 for 1363 dispensing. It can be configured with three.

Therefore, in the phase locked loop circuit of the present invention, the position of the reference frequency is not always constant when the image input signal is switched on / off so that the reference frequency and the comparison frequency signal are quickly matched. As shown in FIG. 3, the synchronization time of the phase-locked loop signal is improved by always being located near the falling end of the reference frequency (Rf) signal, and it is possible to reduce the latch time of the screen when switching on / off. It works.

Claims (1)

A looping circuit (4) for inputting a sampling frequency signal to generate a comparison frequency signal having the same frequency (Vf) as the image line frequency signal, and inputting a reference frequency (Rf) signal having the comparison frequency signal and the image line frequency A phase detector 1 generating a phase difference signal corresponding to the phase difference between the signals, a low pass filter 2 for inputting a signal from the phase detector 1 to remove high frequency components, and the low pass filter 2 A phase-locked loop circuit comprising a voltage controlled oscillator (3) for inputting a phase difference signal from to generate the sampling frequency, comprising: a phase having a predetermined duration in response to a falling edge of the reference frequency (Rf) signal; First gate means (51) for outputting one state signal; Second gate means (53) and (54) for synchronizing said reference frequency (Rf) signal with said sampling frequency signal in response to said reference frequency (Rf) signal; A third gate for inputting a signal from the first gate means 51 and a signal from the loop circuit 4 and outputting a second state signal if the phases thereof are in agreement with each other; Means 52; First delay means (55) for inputting signals from the second gate means (53) and (54) to output the second state signal at the reference frequency falling edge; The signal from the third gate means 52 and the signal from the first delay means 55 are input, and the signal from the third gate means 52 is a second state signal, Fourth gate means 56, 57, and 58 for outputting a second state signal for resetting the loop circuit 4 only if the signal from the one delay means is a second state signal; And a reset generator (5).