JP3070053B2 - Digital PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A digital PLL (Phase) used for an FM multiplex demodulation circuit, a television synchronization signal generation circuit, etc.
Regarding the complete digitalization of Locked Loop (Clocked Loop) circuits, digital PLL circuits convert external input signals with a clock precision equal to or lower than the system clock, instead of digital PLL circuits that include analog circuits that require capacitance and inductance components.
Digital voltage variable oscillating means for inputting clock number data having an integer part and a decimal part, and outputting an output signal having a phase corresponding to the clock number data for the purpose of processing, an external input signal and the output signal Input, for each input of the foreign input signal, count the integer part and the decimal part of the system clock that divides one cycle of the foreign input signal,
Digital phase difference detection means for detecting an integer part and a decimal part of a phase difference between the external input signal and the output signal based on the result and outputting phase difference data, and a specific clock number corresponding to the phase difference data A digital low-pass filter that outputs data, and a clock number data output unit that outputs the clock number data based on the specific clock number data and the clock number of the reference cycle, and when detecting the phase difference, The method includes calculating and processing each of the integer part and the decimal part.

[Industrial applications]

The present invention relates to a digital PLL circuit, and more particularly, to complete digitization of a PLL (Phase Locked Loop) circuit used in an FM multiplex demodulation circuit, a television synchronization signal generation circuit, and the like.

In recent years, a capacitance component and an inductance component have been required in an analog PLL circuit, and it has been difficult to make them into ICs.

However, VTR (Video Tape Recorder) and LASER DISC
Digital signal information is required as phase information in a digital television video signal processing circuit or the like that requires correction of a video signal corresponding to the phase of a color burst carrier and a horizontal synchronizing signal when a non-standard signal such as that described above is input. There are cases.

[Conventional technology]

FIG. 6 is a diagram illustrating a digital PLL circuit according to a conventional example.

In the figure, reference numeral 1 denotes a change point detection circuit for detecting a change point of the external input signal Si. The external input signal Si is a horizontal synchronization signal included in a composite video signal such as a television signal or a baseband signal included in an FM (frequency modulation) wave.
Reference numeral 2 denotes an internal circuit that operates using the system clock φ as a minimum unit, and a phase difference detection circuit that detects a phase difference from the external input signal Si.
4 operates with the system clock φ as the minimum unit, and V
CO (Voltage Controlled Oscillator)
Is a Si / So match detection circuit, and the external input signal Si and the output signal So synchronized or locked to the external input signal Si match,
This is to detect a value of “0”.

In the operation, the change point detection circuit 1 detects a change such as a rise or a fall of the external signal Si, and the value of the counter is held by the phase difference detection circuit 2, which becomes the phase difference information. The digital low-pass filter 3 performs processing along the PLL logic based on the VCO of the analog PLL.
(Voltage Controlled Oscillator) to control the program counter 4 to output an output signal So synchronized or locked to the external input signal Si.

For example, when the phase of the output signal So is delayed with respect to the external input signal Si, the positive phase difference information is detected by the phase difference detection circuit 2, and the phase difference detection circuit 2 passes through the digital low-pass filter 3. To instruct the program counter 4 to increase the count cycle.

When the phase of the output signal So is advanced with respect to the external input signal Si, negative information is output from the phase difference detection circuit 2.
And the phase difference detection circuit 2 instructs through the digital low-pass filter 3 to decrease the cycle of the program counter 4. This operation is repeated several times until the external input signal Si matches the output signal So,
Eventually, both will be in a synchronized or locked state.

[Problems to be solved by the invention]

FIG. 7 is an explanatory diagram of a problem of a digital PLL circuit according to a conventional example.

In the figure, 6 is a screen of a CRT device or the like, and 7 is a horizontal scanning line in which the electron beam 7a moves from one end to the other end of the screen. The horizontal cycle is 63.5 [μs].

In addition, digital PLL such as digital TV signal processing circuit
When the circuit locks the horizontal synchronizing signal by PLL, the system clock φ is 4 fsc, for example, four times the color subcarrier, that is, about 70 [ns] period, so that the clock accuracy on the screen is ± 70 [ns]. Becomes As a result, on the left and right of the screen,
Screen shake 8 may occur.

In other words, in the conventional digital PLL circuit, the VCO (V
The program counter 4 and the phase difference detection circuit 2 for detecting a phase difference operate using the system clock φ as a minimum unit.

For this reason, since the accuracy of the digital PLL circuit generally depends on the system clock φ, when accuracy less than the cycle of the system clock φ is required, for example, a horizontal synchronization signal of a TV signal or the like is PLL-processed to obtain an accurate horizontal signal. Synchronous signal and phase difference information cannot be obtained.

As a result, the conventional digital PLL circuit which performs the minimum operation by the system clock φ cannot achieve the accuracy of the clock accuracy of 70 [ns] or less, and the screen shake 8 may occur as shown in FIG. There is.

The present invention has been made in view of the problem of the conventional example, and replaces a digital PLL circuit in which an analog circuit requiring a capacitance component and an inductance component is mixed, with an external input signal having a clock accuracy equal to or less than a system clock. The purpose of the present invention is to provide a digital PLL circuit capable of performing digital PLL processing.

[Means for solving the problem]

As shown in FIG. 1, the digital PLL circuit of the present invention receives clock number data Z having an integer part and a decimal part and outputs an output signal So having a phase corresponding to the clock number data Z. Digital voltage variable oscillating means 13 for inputting an external input signal Si and the output signal So, and for each input of the external input signal Si, an integer part and a decimal part of a system clock for dividing one cycle of the external input signal Count the parts,
Digital phase difference detection means 11 for detecting an integer part and a decimal part of a phase difference between the external input signal Si and the output signal So based on the result and outputting phase difference data, and according to the phase difference data. A digital low-pass filter 12 that outputs specific clock number data; and a clock number data output unit 14 that outputs the clock number data based on the specific clock number data and the reference synchronous clock number. The above object is achieved by a digital PLL circuit which calculates and processes each of an integer part and a decimal part upon detection.

The digital voltage variable oscillating means includes an integer part calculating means for calculating an integer part of the number of clocks for one cycle based on the integer part of the clock number data, and one cycle based on the decimal part of the clock number data. A decimal part calculating means for calculating a decimal part of the number of clocks in a period, wherein the digital phase difference detecting means includes a change point detecting circuit for detecting a change point of the external input signal, and one cycle of the external input signal. A phase difference detection circuit that detects a fractional part of a phase difference for each phase, a first register that stores an output of the phase difference detection circuit in accordance with an output of the change point detection circuit, A second register for storing an output of the decimal part operation means, and an adder for adding values of the first and second registers;
Thus, a decimal part of a phase difference between the external input signal and the output signal is detected.

[Action]

According to the present invention, one cycle of the external input signal Si is divided by the system clock by the digital phase difference detecting means, and the number of clocks of the system clock included in the one cycle is not only an integer part but also a decimal part, for example, a decimal point. Hereinafter, counting is performed to the second to third places, and based on the result, an integer part and a decimal part of a phase difference between the output signal and the external input signal are detected, and phase difference data is output. Then, since the phase difference data is fed back to the digital voltage variable oscillation (VCO) means via the digital low-pass filter and the clock number data output means, an output synchronized with the external input signal Si with an accuracy depending on the decimal part of the system clock. The signal So can be output.

As a result, a completely digital PLL circuit can be configured in place of the conventional digital PLL circuit in which an analog circuit is mixed, and digital PLL processing can be performed with a clock accuracy equal to or less than the system clock.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIGS. 1 to 5 are diagrams for explaining a digital PLL circuit according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of a digital PLL circuit according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a digital phase difference detecting means, which outputs a horizontal synchronizing signal Hi such as a television signal to an external input signal Si.
And outputs the phase difference data PD. The digital phase difference detecting means 11 divides one cycle of the horizontal synchronizing signal Hi by the system clock φs, and counts the fractional part from the second to third decimal places, for example, and outputs it as phase data. A circuit 24, registers 31, 32, 36 and an adder 34 for calculating a fractional part of the number of clocks Z, which will be described later, based on the phase data output from the phase difference detection circuit 24; , A change point circuit 23 for detecting a change point, and registers 30, 35 and an adder 33 for calculating the integer part of the clock number Z.

Reference numeral 12 denotes a digital low-pass filter, which converts the phase difference data PD output from the digital phase difference detecting means 11 into a PL.
It has a function of processing according to the L logic and outputting a specific clock number Zo representing the phase difference by the clock number.

Numeral 13 denotes a digital voltage variable oscillation (VCO) means, which receives the horizontal synchronizing signal Hi based on data representing the number of clocks Z output from the digital low-pass filter 12 via an adder (clock number data output means) 37. Has a function of outputting a horizontal synchronizing signal Ho that has been synchronized. The digital VCO means 13 includes an adder 22 and a register 27 for calculating the fractional part of the clock number Z, and an adder 21, a counter 25, and a register for calculating the integer part of the clock number Z.
26 and 29 and a coincidence detecting circuit 28.

Reference numeral 37 denotes an adder which adds the number of specific clocks Zo and the number of clocks Zs of the reference cycle to obtain data representing the number of clocks Z.
And to output the D _2. The number of clocks Z represents one cycle of the oscillation frequency of the digital VCO 13.

Thus, a digital PLL circuit according to an embodiment of the present invention is configured.

FIG. 3 shows an operation time chart of the digital voltage variable oscillation means according to the embodiment of the present invention.

In the figure, the digital VCO means 13 uses the horizontal synchronizing signal Hi (period 63.5 [μs]) as the external input signal Si, the system clock φs (four times the color subcarrier fsc 4fsc (period 70 [ns])).
7 is a time chart showing a case where one cycle of the horizontal synchronizing signal Si changes from 910 clock operation to 1000 clock operation when digital PLL processing is performed.

In the figure, the output data of the D ₁ counter 25, D ₂ is data representing the number of clocks Z, D ₃ is the output data of the register 26, D ₄
The coincidence (detected) data, D ₅ is the output data of the register 29. Note the horizontal synchronizing signal Ho synchronized with the output data D ₅ is input horizontal synchronizing signal Si.

Here, the clock number Z will be described in detail. This expresses the cycle of the oscillation frequency of the digital VCO 13 in units of one cycle clock number. The number of clocks Z includes a part indicating the number of system clocks included in one cycle (hereinafter referred to as an integer part) and a part indicating a phase difference equal to or less than the cycle of the system clock (hereinafter referred to as a decimal part). The decimal part is processed by the adder 22 and the register 27, and the decimal part and the integer part are linked and connected by a carry connecting the adders 21 and 22. Since the decimal part and the integer part behave the same,
First, the operation of the integer part will be described, and then the operation when the circuit has a decimal part will be described.

The operation of the integer part (when the decimal part is not considered) is shown in the time chart of FIG.

First, the number of clocks Z passed by the counter 25 is quantified, and the lapse of time is expressed numerically with reference to the system clock. In the case of expressing an infinite numerical value, an infinitely large counter 25 is required and cannot be realized. There is no problem in operation. However, for the sake of clarity, it is assumed that the counter 25 has an infinite counter function.

As mentioned earlier, the number of clocks Z is
Expresses the cycle of O13. The elapsed time is stored in the register 29 updated every cycle. For example, the completion point of the first first cycle is 910, the completion point of the next second cycle is 1820, the completion point of the third cycle is 2730, and the elapsed time of each cycle of the cycle 1, 2, 3,. Stored in 29.

Further, the elapsed time at the completion of the next cycle is input to the register 26.

The operation will be described step by step. First, it is assumed that the initial constant 910 is initially stored in the register 26 and the counter 25 starts operating from the initial value 0. Next, when the value of the counter 25 reaches 910, the following operation is started. First,
A match signal (match data D ₄ ) is output from a match detection circuit 28 which detects a match between the value of the counter 25 and the value of the register 26. Using this coincidence signal as a trigger, the time when the cycle is completed is stored in the time lapse recording register 29 at the time of completion of one cycle. The time when the cycle is completed plus the cycle of the VCO 13 (the number of clocks Z) is added to the register 26, and as a result, the completion time of the cycle is stored. The time chart in the figure illustrates this operation.

When the number of clocks Z, that is, the number of clocks in one cycle is changed from 910 to 1000, the value obtained by adding 1000 to the time at the time of completion of one cycle is added to the register 26 at the completion of one cycle, The period changes from 910 clocks to 1000 clocks.

Next, for example, if the clock number Z contains a value of 910.2 including a fractional part, 910.2
When this is repeated five times, a plus one carry is generated from the decimal part (adder 22) to the integer part (adder 21).

As described above, the system clock (4fsc about 70 [n
s]) The digital VCO 13 that operates with the following clock accuracy can be configured.

FIG. 4 is an explanatory diagram relating to the digital low-pass filter circuit of the embodiment of the present invention and the number of clocks Z.

In the figure, the digital low-pass filter circuit 12 is a PLL
It is composed of a logic circuit 12a performing a logical operation and a register 12b, and has a function of inputting the phase difference data PD and outputting the specific clock number Zo. Note that the specific clock number Zo and the reference clock number Zs are added by the adder 37, and the digital VCO 1
The number of clocks Z to be input to 3 is created.

FIG. 5 is an operation time chart according to the digital PLL circuit of the embodiment of the present invention, and shows, for example, an operation of performing a PLL process on a horizontal synchronization signal of a television signal.

In the figure, the time of the horizontal synchronizing signal of T1 television (TV), Hi is the horizontal synchronizing signal of the TV, Z is the number of clocks, D _3, the output data of the D ₆ register 26, 27, D ₄ is coincidence detection data, D _5, D ₇ is output data of the register 29, the output data of D _7, D ₈ registers 30 and 32, the phase difference data PD representing the data difference register 35 and 36, Zo is the digital low-pass filter 12 This is output data and represents the number of specific clocks.

It is to be noted that this is an operation chart in the case where the registers 26 and 27 have an initial value of 1000 and the digital low-pass filter 12 has an initial value of 0.
Assuming that the period of the horizontal synchronizing signal Hi is 1000, assuming that the phase difference between the horizontal synchronizing signal Hi and the end of the cycle of the digital VCO (internal counter 25) is initially 3, the period of the horizontal synchronizing signal Hi is 1000
And an operation example on the assumption that the number of clocks of the reference cycle matches 1000.

Next, the digital PLL operation will be described with reference to the circuit of FIG. 2 together with the means for detecting the phase difference between the output of the VCO and the external signal (in this case, the horizontal synchronization signal of the television). As described for the digital VCO 13, the elapsed time at the completion of one cycle of the digital VCO 13 is stored in the register 29 for the integer part and in the register 31 for the decimal part. If the difference between this value and the elapsed time when the horizontal synchronization signal Hi of the television arrives, for example, T1 = 1003, the time difference between the horizontal synchronization signal Hi of the television and the completion time of one cycle of the digital VCO, for example, T1 = 1000, is obtained. I understand. The integer part of the time when the TV horizontal synchronization signal Hi is input is a counter
It is possible to extract from 25 outputs. Therefore, the transition point of the horizontal synchronization signal Hi is detected by the transition point detection circuit 23 which detects the input of the horizontal synchronization signal Hi of the television, and the time at that time, that is, the value of the counter 25 is stored in the register 30. For the decimal part, a circuit 24 for detecting a phase difference equal to or less than the cycle of the system clock detects the decimal part.
The phase difference detection circuit 24 is composed of, for example, an n-stage delay element and an n-bit register, and outputs phase data having second to third decimal places. Note that this phase difference detection circuit
24 can have various configurations, but the point is that the horizontal synchronization signal 1
What is necessary is just to be able to detect the fractional part of the number of system clocks that divides the period.

In this way, the time when the horizontal synchronizing signal Hi is input is stored in the register 30 for the integer part and the register 32 for the decimal part. After that, the registers 29 and 3 storing the change time of one cycle
The difference between 1 and registers 30 and 32 is added to adder 33 (integer part operation) and 34
(Decimal part operation). The adders 33 and 34 are ordinary adders, and the carry of the adder 34 is connected to the adder 33 to cooperate with the integer part and the decimal part. Regarding the outputs of the adders 33 and 34, the integer part is stored in the register 35 and the decimal part is stored in the register 36.

In these registers 35 and 36, phase difference information PD between the horizontal synchronization signal Hi of the television and the completion time of one cycle of the digital VCO is stored.

The detected phase difference information PD is input to the low-pass filter 12 calculated based on the PLL theory. The output Zo (the number of specific clocks) of the low-pass filter 12 basically operates to control the digital VCO 13 as described below.

If the detected phase difference is a positive value,
The phase of the horizontal synchronizing signal Hi leads the end of one cycle of the VCO 13 by that much. Therefore, the value of the number of clocks Z input to the digital VCO 13 is increased. As the number of clocks Z increases, the oscillation frequency of the VCO 13 decreases accordingly. At the next time, the end of one cycle of the digital VCO 13 and the advance of the horizontal synchronizing signal Hi slightly decrease from the previous time. However, since the phase detected by the digital phase difference detecting means 11 is still advanced, this information is added to the clock number Z through the low-pass filter 12. In this way, the time difference (phase difference) between the horizontal synchronizing signal Hi and the end of one cycle sequentially decreases.

In general, depending on the type of low-pass filter, this operation is repeated, and at some point, the phase difference becomes negative once (that is, it goes too far in trying to match the phase), and this time, conversely, The output Zo of the low-pass filter 12 works in the direction of decreasing the number of clocks Z. After repeating this several times, the horizontal sync signal Hi and digital VCO13
The control is performed so that the timings at the end of one cycle of the above exactly match.

Thus, the horizontal synchronization signal Hi can be subjected to digital PLL processing, and the horizontal synchronization signal Ho synchronized with the horizontal synchronization signal Hi can be output.

In this way, the external input signal Si, for example, during the horizontal synchronization
One period of Hi is divided by, for example, a system clock φs (four times the color subcarrier fsc, a clock of 4 fsc of about 70 [ns]), and the number of system clocks included in the one period is an integer part and a decimal number. For example, the second to third decimal places are counted, compared with the number of reference clocks of the system clock included in the external input signal Si in advance, and the phase difference data PD is passed through the digital low-pass filter 12 to the digital voltage variable oscillation. Since it is fed back to the means (VCO) 13, the accuracy depends on the fractional part of the system clock, for example, 70 [n
s] × The output signal So synchronized with the external input signal Si can be output with the clock precision represented by the value of the decimal part.

As a result, a completely digital PLL circuit can be configured instead of a digital PLL circuit in which an analog circuit is mixed as in the related art, and a digital PLL process can be performed with a clock accuracy equal to or lower than the system clock.

Also, for example, in FIG.
In the case of division, the divided period becomes about 5 to 10 [ns]. If PLL processing of the horizontal synchronization signal is performed in this clock range, screen shaking (blur) is eliminated, and visually high image quality and
High quality images can be obtained. In the present invention, since the phase difference is counted down to the fractional part of the system clock, 70 [ns]
× Since a phase-locked signal is obtained with the precision represented by the decimal part, a high-quality and high-quality image can be obtained.

〔The invention's effect〕

As described above, according to the present invention, an integer part and a decimal part of a system clock that divides an external input signal can be added, so that a digital PLL circuit including an analog circuit can be used instead of a system clock. With the clock accuracy described above, digital PLL processing of an external input signal can be performed.

As a result, it is possible to eliminate a jitter phenomenon caused by a phase shift of a horizontal synchronizing signal or the like, and it is possible to configure a high-quality, high-quality digital television display control device or the like.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of a digital PLL circuit according to an embodiment of the present invention, FIG. 2 is a diagram illustrating the configuration of a digital PLL circuit according to an embodiment of the present invention, and FIG. FIG. 4 is an explanatory diagram relating to the digital low-pass filter circuit and the number of clocks Z according to the embodiment of the present invention. FIG. 5 is a digital PLL circuit according to the embodiment of the present invention. FIG. 6 is a system block diagram illustrating a digital PLL circuit according to a conventional example, and FIG. 7 is a diagram illustrating problems of a digital PLL circuit according to a conventional example. (Explanation of symbols) 11: Digital phase difference detection means 12, 3, 3 ... Digital low-pass filter 13, Digital voltage variable oscillation means 1, 23: Change point detection circuit 2, 24: Phase difference detection Circuit, 25, Program counter (counter), 5, 28 Si / So match detection circuit, 6 Screen, 7 Horizontal scan line, 8 Screen shake, 7a Electron beam, 21 , 22,33,34,37… Adder, 26,27,29,30,31,32,35,36,12b… Register, 12a… Logic circuit, Z… Number of clocks, Zo… Ratio Number of clocks (output data of digital low-pass filter), Zs: Number of clocks in reference cycle, Si, (Hi): External input signal (horizontal synchronization signal), SO, (Ho): Locked to external input signal output signal (synchronization lock is horizontal synchronizing signals), φ, φS ...... system clock, PD ...... phase difference data, the output data of the D ₁ ...... counter 25 D ₂ ...... data representing the number of clocks Z, D ₃ output data ...... register 26, D ₄ ...... matching (detection) data, the output data of the D ₅ ...... register 29, the output data of the D ₆ ...... register 27 , D ₇ ... Output data of the register 30, D ₈ .

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-292825 (JP, A) JP-A-63-10823 (JP, A) JP-A-63-82127 (JP, A) 9374 (JP, B2) JP-B-54-5982 (JP, B2)

Claims (2)

(57) [Claims] A digital voltage variable oscillating means for inputting clock number data having an integer part and a decimal part and outputting an output signal having a phase corresponding to the clock number data, and inputting an external input signal and the output signal. Calculating, for each input of the external input signal, an integer part and a decimal part of a system clock that divides one cycle of the external input signal, and calculates a phase difference between the external input signal and the output signal based on the result. Digital phase difference detecting means for detecting an integer part and a decimal part of the phase difference data and outputting phase difference data; a digital low-pass filter for outputting specific clock number data according to the phase difference data; and a reference synchronization with the specific clock number data. Clock number data output means for outputting the clock number data based on the number of clocks, when detecting the phase difference, that of the integer part and the decimal part A digital PLL circuit that calculates and processes each. 2. The digital voltage variable oscillation means according to claim 1, wherein said digital number variable oscillating means calculates an integer part of the number of clocks in one cycle based on the integer part of said clock number data; Further comprising a decimal part calculating means for calculating a decimal part of the number of clocks during one cycle, wherein the digital phase difference detecting means comprises a change point detecting circuit for detecting a change point of the external input signal, and the external input signal A phase difference detection circuit for detecting a fractional part of a phase difference for each cycle of the period, a first register for storing an output of the phase difference detection circuit in accordance with an output of the change point detection circuit, Means for storing the output of the decimal part calculation means, and an adder for adding the values of the first and second registers. The fractional part of the phase difference The digital PLL circuit according to claim 1, wherein the detection is performed.